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aiot
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waterDataPreprocessing
/
dataProcessing
/
levelDataPreprocessingThread.h

levelDataPreprocessingThread.h 28 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF538_H
    8. 

  8. #define _DEF_BF538_H
    9. 

  9. 

  10. /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
    11. 

  11. #define	PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
    12. 

  12. #define	PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
    13. 

  13. #define	VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    14. 

  14. #define	PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
    15. 

  15. #define	PLL_LOCKCNT		0xFFC00010	/* PLL Lock	Count register (16-bit) */
    16. 

  16. #define	CHIPID			0xFFC00014	/* Chip	ID Register */
    17. 

  17. 

  18. /* CHIPID Masks */
    19. 

  19. #define CHIPID_VERSION         0xF0000000
    20. 

  20. #define CHIPID_FAMILY          0x0FFFF000
    21. 

  21. #define CHIPID_MANUFACTURE     0x00000FFE
    22. 

  22. 

  23. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
    24. 

  24. #define	SWRST			0xFFC00100  /* Software	Reset Register (16-bit) */
    25. 

  25. #define	SYSCR			0xFFC00104  /* System Configuration registe */
    26. 

  26. #define	SIC_RVECT		0xFFC00108
    27. 

  27. #define	SIC_IMASK0		0xFFC0010C  /* Interrupt Mask Register */
    28. 

  28. #define	SIC_IAR0		0xFFC00110  /* Interrupt Assignment Register 0 */
    29. 

  29. #define	SIC_IAR1		0xFFC00114  /* Interrupt Assignment Register 1 */
    30. 

  30. #define	SIC_IAR2		0xFFC00118  /* Interrupt Assignment Register 2 */
    31. 

  31. #define	SIC_IAR3			0xFFC0011C	/* Interrupt Assignment	Register 3 */
    32. 

  32. #define	SIC_ISR0			0xFFC00120  /* Interrupt Status	Register */
    33. 

  33. #define	SIC_IWR0			0xFFC00124  /* Interrupt Wakeup	Register */
    34. 

  34. #define	SIC_IMASK1			0xFFC00128	/* Interrupt Mask Register 1 */
    35. 

  35. #define	SIC_ISR1			0xFFC0012C	/* Interrupt Status Register 1 */
    36. 

  36. #define	SIC_IWR1			0xFFC00130	/* Interrupt Wakeup Register 1 */
    37. 

  37. #define	SIC_IAR4			0xFFC00134	/* Interrupt Assignment	Register 4 */
    38. 

  38. #define	SIC_IAR5			0xFFC00138	/* Interrupt Assignment	Register 5 */
    39. 

  39. #define	SIC_IAR6			0xFFC0013C	/* Interrupt Assignment	Register 6 */
    40. 

  40. 

  41. 

  42. /* Watchdog Timer (0xFFC00200 -	0xFFC002FF) */
    43. 

  43. #define	WDOG_CTL	0xFFC00200  /* Watchdog	Control	Register */
    44. 

  44. #define	WDOG_CNT	0xFFC00204  /* Watchdog	Count Register */
    45. 

  45. #define	WDOG_STAT	0xFFC00208  /* Watchdog	Status Register */
    46. 

  46. 

  47. 

  48. /* Real	Time Clock (0xFFC00300 - 0xFFC003FF) */
    49. 

  49. #define	RTC_STAT	0xFFC00300  /* RTC Status Register */
    50. 

  50. #define	RTC_ICTL	0xFFC00304  /* RTC Interrupt Control Register */
    51. 

  51. #define	RTC_ISTAT	0xFFC00308  /* RTC Interrupt Status Register */
    52. 

  52. #define	RTC_SWCNT	0xFFC0030C  /* RTC Stopwatch Count Register */
    53. 

  53. #define	RTC_ALARM	0xFFC00310  /* RTC Alarm Time Register */
    54. 

  54. #define	RTC_FAST	0xFFC00314  /* RTC Prescaler Enable Register */
    55. 

  55. #define	RTC_PREN		0xFFC00314  /* RTC Prescaler Enable Register (alternate	macro) */
    56. 

  56. 

  57. 

  58. /* UART0 Controller (0xFFC00400	- 0xFFC004FF) */
    59. 

  59. #define	UART0_THR	      0xFFC00400  /* Transmit Holding register */
    60. 

  60. #define	UART0_RBR	      0xFFC00400  /* Receive Buffer register */
    61. 

  61. #define	UART0_DLL	      0xFFC00400  /* Divisor Latch (Low-Byte) */
    62. 

  62. #define	UART0_IER	      0xFFC00404  /* Interrupt Enable Register */
    63. 

  63. #define	UART0_DLH	      0xFFC00404  /* Divisor Latch (High-Byte) */
    64. 

  64. #define	UART0_IIR	      0xFFC00408  /* Interrupt Identification Register */
    65. 

  65. #define	UART0_LCR	      0xFFC0040C  /* Line Control Register */
    66. 

  66. #define	UART0_MCR			 0xFFC00410  /*	Modem Control Register */
    67. 

  67. #define	UART0_LSR	      0xFFC00414  /* Line Status Register */
    68. 

  68. #define	UART0_SCR	      0xFFC0041C  /* SCR Scratch Register */
    69. 

  69. #define	UART0_GCTL		     0xFFC00424	 /* Global Control Register */
    70. 

  70. 

  71. 

  72. /* SPI0	Controller (0xFFC00500 - 0xFFC005FF) */
    73. 

  73. 

  74. #define	SPI0_CTL			0xFFC00500  /* SPI0 Control Register */
    75. 

  75. #define	SPI0_FLG			0xFFC00504  /* SPI0 Flag register */
    76. 

  76. #define	SPI0_STAT			0xFFC00508  /* SPI0 Status register */
    77. 

  77. #define	SPI0_TDBR			0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
    78. 

  78. #define	SPI0_RDBR			0xFFC00510  /* SPI0 Receive Data Buffer	Register */
    79. 

  79. #define	SPI0_BAUD			0xFFC00514  /* SPI0 Baud rate Register */
    80. 

  80. #define	SPI0_SHADOW			0xFFC00518  /* SPI0_RDBR Shadow	Register */
    81. 

  81. #define SPI0_REGBASE			SPI0_CTL
    82. 

  82. 

  83. 

  84. /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
    85. 

  85. #define	TIMER0_CONFIG			0xFFC00600     /* Timer	0 Configuration	Register */
    86. 

  86. #define	TIMER0_COUNTER				0xFFC00604     /* Timer	0 Counter Register */
    87. 

  87. #define	TIMER0_PERIOD			0xFFC00608     /* Timer	0 Period Register */
    88. 

  88. #define	TIMER0_WIDTH			0xFFC0060C     /* Timer	0 Width	Register */
    89. 

  89. 

  90. #define	TIMER1_CONFIG			0xFFC00610	/*  Timer 1 Configuration Register   */
    91. 

  91. #define	TIMER1_COUNTER			0xFFC00614	/*  Timer 1 Counter Register	     */
    92. 

  92. #define	TIMER1_PERIOD			0xFFC00618	/*  Timer 1 Period Register	     */
    93. 

  93. #define	TIMER1_WIDTH			0xFFC0061C	/*  Timer 1 Width Register	     */
    94. 

  94. 

  95. #define	TIMER2_CONFIG			0xFFC00620	/* Timer 2 Configuration Register   */
    96. 

  96. #define	TIMER2_COUNTER			0xFFC00624	/* Timer 2 Counter Register	    */
    97. 

  97. #define	TIMER2_PERIOD			0xFFC00628	/* Timer 2 Period Register	    */
    98. 

  98. #define	TIMER2_WIDTH			0xFFC0062C	/* Timer 2 Width Register	    */
    99. 

  99. 

  100. #define	TIMER_ENABLE				0xFFC00640	/* Timer Enable	Register */
    101. 

  101. #define	TIMER_DISABLE				0xFFC00644	/* Timer Disable Register */
    102. 

  102. #define	TIMER_STATUS				0xFFC00648	/* Timer Status	Register */
    103. 

  103. 

  104. 

  105. /* Programmable	Flags (0xFFC00700 - 0xFFC007FF) */
    106. 

  106. #define	FIO_FLAG_D				0xFFC00700  /* Flag Mask to directly specify state of pins */
    107. 

  107. #define	FIO_FLAG_C			0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
    108. 

  108. #define	FIO_FLAG_S			0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
    109. 

  109. #define	FIO_FLAG_T					0xFFC0070C  /* Flag Mask to directly toggle state of pins */
    110. 

  110. #define	FIO_MASKA_D			0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
    111. 

  111. #define	FIO_MASKA_C			0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
    112. 

  112. #define	FIO_MASKA_S			0xFFC00718  /* Flag Mask Interrupt A Register (set) */
    113. 

  113. #define	FIO_MASKA_T			0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
    114. 

  114. #define	FIO_MASKB_D			0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
    115. 

  115. #define	FIO_MASKB_C			0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
    116. 

  116. #define	FIO_MASKB_S			0xFFC00728  /* Flag Mask Interrupt B Register (set) */
    117. 

  117. #define	FIO_MASKB_T			0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
    118. 

  118. #define	FIO_DIR				0xFFC00730  /* Peripheral Flag Direction Register */
    119. 

  119. #define	FIO_POLAR			0xFFC00734  /* Flag Source Polarity Register */
    120. 

  120. #define	FIO_EDGE			0xFFC00738  /* Flag Source Sensitivity Register */
    121. 

  121. #define	FIO_BOTH			0xFFC0073C  /* Flag Set	on BOTH	Edges Register */
    122. 

  122. #define	FIO_INEN					0xFFC00740  /* Flag Input Enable Register  */
    123. 

  123. 

  124. 

  125. /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
    126. 

  126. #define	SPORT0_TCR1				0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
    127. 

  127. #define	SPORT0_TCR2				0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
    128. 

  128. #define	SPORT0_TCLKDIV			0xFFC00808  /* SPORT0 Transmit Clock Divider */
    129. 

  129. #define	SPORT0_TFSDIV			0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
    130. 

  130. #define	SPORT0_TX			0xFFC00810  /* SPORT0 TX Data Register */
    131. 

  131. #define	SPORT0_RX			0xFFC00818  /* SPORT0 RX Data Register */
    132. 

  132. #define	SPORT0_RCR1				0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
    133. 

  133. #define	SPORT0_RCR2				0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
    134. 

  134. #define	SPORT0_RCLKDIV			0xFFC00828  /* SPORT0 Receive Clock Divider */
    135. 

  135. #define	SPORT0_RFSDIV			0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
    136. 

  136. #define	SPORT0_STAT			0xFFC00830  /* SPORT0 Status Register */
    137. 

  137. #define	SPORT0_CHNL			0xFFC00834  /* SPORT0 Current Channel Register */
    138. 

  138. #define	SPORT0_MCMC1			0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
    139. 

  139. #define	SPORT0_MCMC2			0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
    140. 

  140. #define	SPORT0_MTCS0			0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
    141. 

  141. #define	SPORT0_MTCS1			0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
    142. 

  142. #define	SPORT0_MTCS2			0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
    143. 

  143. #define	SPORT0_MTCS3			0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
    144. 

  144. #define	SPORT0_MRCS0			0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
    145. 

  145. #define	SPORT0_MRCS1			0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
    146. 

  146. #define	SPORT0_MRCS2			0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
    147. 

  147. #define	SPORT0_MRCS3			0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
    148. 

  148. 

  149. 

  150. /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
    151. 

  151. #define	SPORT1_TCR1				0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
    152. 

  152. #define	SPORT1_TCR2				0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
    153. 

  153. #define	SPORT1_TCLKDIV			0xFFC00908  /* SPORT1 Transmit Clock Divider */
    154. 

  154. #define	SPORT1_TFSDIV			0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
    155. 

  155. #define	SPORT1_TX			0xFFC00910  /* SPORT1 TX Data Register */
    156. 

  156. #define	SPORT1_RX			0xFFC00918  /* SPORT1 RX Data Register */
    157. 

  157. #define	SPORT1_RCR1				0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
    158. 

  158. #define	SPORT1_RCR2				0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
    159. 

  159. #define	SPORT1_RCLKDIV			0xFFC00928  /* SPORT1 Receive Clock Divider */
    160. 

  160. #define	SPORT1_RFSDIV			0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
    161. 

  161. #define	SPORT1_STAT			0xFFC00930  /* SPORT1 Status Register */
    162. 

  162. #define	SPORT1_CHNL			0xFFC00934  /* SPORT1 Current Channel Register */
    163. 

  163. #define	SPORT1_MCMC1			0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
    164. 

  164. #define	SPORT1_MCMC2			0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
    165. 

  165. #define	SPORT1_MTCS0			0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
    166. 

  166. #define	SPORT1_MTCS1			0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
    167. 

  167. #define	SPORT1_MTCS2			0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
    168. 

  168. #define	SPORT1_MTCS3			0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
    169. 

  169. #define	SPORT1_MRCS0			0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
    170. 

  170. #define	SPORT1_MRCS1			0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
    171. 

  171. #define	SPORT1_MRCS2			0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
    172. 

  172. #define	SPORT1_MRCS3			0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
    173. 

  173. 

  174. 

  175. /* External Bus	Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
    176. 

  176. /* Asynchronous	Memory Controller  */
    177. 

  177. #define	EBIU_AMGCTL			0xFFC00A00  /* Asynchronous Memory Global Control Register */
    178. 

  178. #define	EBIU_AMBCTL0		0xFFC00A04  /* Asynchronous Memory Bank	Control	Register 0 */
    179. 

  179. #define	EBIU_AMBCTL1		0xFFC00A08  /* Asynchronous Memory Bank	Control	Register 1 */
    180. 

  180. 

  181. /* SDRAM Controller */
    182. 

  182. #define	EBIU_SDGCTL			0xFFC00A10  /* SDRAM Global Control Register */
    183. 

  183. #define	EBIU_SDBCTL			0xFFC00A14  /* SDRAM Bank Control Register */
    184. 

  184. #define	EBIU_SDRRC			0xFFC00A18  /* SDRAM Refresh Rate Control Register */
    185. 

  185. #define	EBIU_SDSTAT			0xFFC00A1C  /* SDRAM Status Register */
    186. 

  186. 

  187. 

  188. 

  189. /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
    190. 

  190. 

  191. #define	DMAC0_TC_PER			0xFFC00B0C	/* DMA Controller 0 Traffic Control Periods Register */
    192. 

  192. #define	DMAC0_TC_CNT			0xFFC00B10	/* DMA Controller 0 Traffic Control Current Counts Register */
    193. 

  193. 

  194. 

  195. 

  196. /* DMA Controller 0 (0xFFC00C00	- 0xFFC00FFF)							 */
    197. 

  197. 

  198. #define	DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
    199. 

  199. #define	DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register */
    200. 

  200. #define	DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register */
    201. 

  201. #define	DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register */
    202. 

  202. #define	DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register */
    203. 

  203. #define	DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register */
    204. 

  204. #define	DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
    205. 

  205. #define	DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
    206. 

  206. #define	DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register */
    207. 

  207. #define	DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
    208. 

  208. #define	DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map	Register */
    209. 

  209. #define	DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register */
    210. 

  210. #define	DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
    211. 

  211. 

  212. #define	DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
    213. 

  213. #define	DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register */
    214. 

  214. #define	DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register */
    215. 

  215. #define	DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register */
    216. 

  216. #define	DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register */
    217. 

  217. #define	DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register */
    218. 

  218. #define	DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
    219. 

  219. #define	DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
    220. 

  220. #define	DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register */
    221. 

  221. #define	DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
    222. 

  222. #define	DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map	Register */
    223. 

  223. #define	DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register */
    224. 

  224. #define	DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
    225. 

  225. 

  226. #define	DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
    227. 

  227. #define	DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register */
    228. 

  228. #define	DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register */
    229. 

  229. #define	DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register */
    230. 

  230. #define	DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register */
    231. 

  231. #define	DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register */
    232. 

  232. #define	DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
    233. 

  233. #define	DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
    234. 

  234. #define	DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register */
    235. 

  235. #define	DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
    236. 

  236. #define	DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map	Register */
    237. 

  237. #define	DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
    238. 

  238. #define	DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
    239. 

  239. 

  240. #define	DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
    241. 

  241. #define	DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register */
    242. 

  242. #define	DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register */
    243. 

  243. #define	DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register */
    244. 

  244. #define	DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register */
    245. 

  245. #define	DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register */
    246. 

  246. #define	DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
    247. 

  247. #define	DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
    248. 

  248. #define	DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register */
    249. 

  249. #define	DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
    250. 

  250. #define	DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map	Register */
    251. 

  251. #define	DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
    252. 

  252. #define	DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
    253. 

  253. 

  254. #define	DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
    255. 

  255. #define	DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register */
    256. 

  256. #define	DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register */
    257. 

  257. #define	DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register */
    258. 

  258. #define	DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register */
    259. 

  259. #define	DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register */
    260. 

  260. #define	DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
    261. 

  261. #define	DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
    262. 

  262. #define	DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register */
    263. 

  263. #define	DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
    264. 

  264. #define	DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map	Register */
    265. 

  265. #define	DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register */
    266. 

  266. #define	DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
    267. 

  267. 

  268. #define	DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
    269. 

  269. #define	DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register */
    270. 

  270. #define	DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register */
    271. 

  271. #define	DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register */
    272. 

  272. #define	DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register */
    273. 

  273. #define	DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register */
    274. 

  274. #define	DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
    275. 

  275. #define	DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
    276. 

  276. #define	DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register */
    277. 

  277. #define	DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
    278. 

  278. #define	DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map	Register */
    279. 

  279. #define	DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register */
    280. 

  280. #define	DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
    281. 

  281. 

  282. #define	DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
    283. 

  283. #define	DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register */
    284. 

  284. #define	DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register */
    285. 

  285. #define	DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register */
    286. 

  286. #define	DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register */
    287. 

  287. #define	DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register */
    288. 

  288. #define	DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
    289. 

  289. #define	DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
    290. 

  290. #define	DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register */
    291. 

  291. #define	DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
    292. 

  292. #define	DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map	Register */
    293. 

  293. #define	DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
    294. 

  294. #define	DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
    295. 

  295. 

  296. #define	DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
    297. 

  297. #define	DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register */
    298. 

  298. #define	DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register */
    299. 

  299. #define	DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register */
    300. 

  300. #define	DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register */
    301. 

  301. #define	DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register */
    302. 

  302. #define	DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
    303. 

  303. #define	DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
    304. 

  304. #define	DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register */
    305. 

  305. #define	DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
    306. 

  306. #define	DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map	Register */
    307. 

  307. #define	DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
    308. 

  308. #define	DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
    309. 

  309. 

  310. #define	MDMA_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA0 Stream 0 Destination	Next Descriptor	Pointer	Register */
    311. 

  311. #define	MDMA_D0_START_ADDR		0xFFC00E04	/* MemDMA0 Stream 0 Destination	Start Address Register */
    312. 

  312. #define	MDMA_D0_CONFIG			0xFFC00E08	/* MemDMA0 Stream 0 Destination	Configuration Register */
    313. 

  313. #define	MDMA_D0_X_COUNT		0xFFC00E10	/* MemDMA0 Stream 0 Destination	X Count	Register */
    314. 

  314. #define	MDMA_D0_X_MODIFY		0xFFC00E14	/* MemDMA0 Stream 0 Destination	X Modify Register */
    315. 

  315. #define	MDMA_D0_Y_COUNT		0xFFC00E18	/* MemDMA0 Stream 0 Destination	Y Count	Register */
    316. 

  316. #define	MDMA_D0_Y_MODIFY		0xFFC00E1C	/* MemDMA0 Stream 0 Destination	Y Modify Register */
    317. 

  317. #define	MDMA_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA0 Stream 0 Destination	Current	Descriptor Pointer Register */
    318. 

  318. #define	MDMA_D0_CURR_ADDR		0xFFC00E24	/* MemDMA0 Stream 0 Destination	Current	Address	Register */
    319. 

  319. #define	MDMA_D0_IRQ_STATUS		0xFFC00E28	/* MemDMA0 Stream 0 Destination	Interrupt/Status Register */
    320. 

  320. #define	MDMA_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA0 Stream 0 Destination	Peripheral Map Register */
    321. 

  321. #define	MDMA_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA0 Stream 0 Destination	Current	X Count	Register */
    322. 

  322. #define	MDMA_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA0 Stream 0 Destination	Current	Y Count	Register */
    323. 

  323. 

  324. #define	MDMA_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA0 Stream 0 Source Next	Descriptor Pointer Register */
    325. 

  325. #define	MDMA_S0_START_ADDR		0xFFC00E44	/* MemDMA0 Stream 0 Source Start Address Register */
    326. 

  326. #define	MDMA_S0_CONFIG			0xFFC00E48	/* MemDMA0 Stream 0 Source Configuration Register */
    327. 

  327. #define	MDMA_S0_X_COUNT		0xFFC00E50	/* MemDMA0 Stream 0 Source X Count Register */
    328. 

  328. #define	MDMA_S0_X_MODIFY		0xFFC00E54	/* MemDMA0 Stream 0 Source X Modify Register */
    329. 

  329. #define	MDMA_S0_Y_COUNT		0xFFC00E58	/* MemDMA0 Stream 0 Source Y Count Register */
    330. 

  330. #define	MDMA_S0_Y_MODIFY		0xFFC00E5C	/* MemDMA0 Stream 0 Source Y Modify Register */
    331. 

  331. #define	MDMA_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
    332. 

  332. #define	MDMA_S0_CURR_ADDR		0xFFC00E64	/* MemDMA0 Stream 0 Source Current Address Register */
    333. 

  333. #define	MDMA_S0_IRQ_STATUS		0xFFC00E68	/* MemDMA0 Stream 0 Source Interrupt/Status Register */
    334. 

  334. #define	MDMA_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA0 Stream 0 Source Peripheral Map Register */
    335. 

  335. #define	MDMA_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA0 Stream 0 Source Current X Count Register */
    336. 

  336. #define	MDMA_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA0 Stream 0 Source Current Y Count Register */
    337. 

  337. 

  338. #define	MDMA_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA0 Stream 1 Destination	Next Descriptor	Pointer	Register */
    339. 

  339. #define	MDMA_D1_START_ADDR		0xFFC00E84	/* MemDMA0 Stream 1 Destination	Start Address Register */
    340. 

  340. #define	MDMA_D1_CONFIG			0xFFC00E88	/* MemDMA0 Stream 1 Destination	Configuration Register */
    341. 

  341. #define	MDMA_D1_X_COUNT		0xFFC00E90	/* MemDMA0 Stream 1 Destination	X Count	Register */
    342. 

  342. #define	MDMA_D1_X_MODIFY		0xFFC00E94	/* MemDMA0 Stream 1 Destination	X Modify Register */
    343. 

  343. #define	MDMA_D1_Y_COUNT		0xFFC00E98	/* MemDMA0 Stream 1 Destination	Y Count	Register */
    344. 

  344. #define	MDMA_D1_Y_MODIFY		0xFFC00E9C	/* MemDMA0 Stream 1 Destination	Y Modify Register */
    345. 

  345. #define	MDMA_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA0 Stream 1 Destination	Current	Descriptor Pointer Register */
    346. 

  346. #define	MDMA_D1_CURR_ADDR		0xFFC00EA4	/* MemDMA0 Stream 1 Destination	Current	Address	Register */
    347. 

  347. #define	MDMA_D1_IRQ_STATUS		0xFFC00EA8	/* MemDMA0 Stream 1 Destination	Interrupt/Status Register */
    348. 

  348. #define	MDMA_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA0 Stream 1 Destination	Peripheral Map Register */
    349. 

  349. #define	MDMA_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA0 Stream 1 Destination	Current	X Count	Register */
    350. 

  350. #define	MDMA_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA0 Stream 1 Destination	Current	Y Count	Register */
    351. 

  351. 

  352. #define	MDMA_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA0 Stream 1 Source Next	Descriptor Pointer Register */
    353. 

  353. #define	MDMA_S1_START_ADDR		0xFFC00EC4	/* MemDMA0 Stream 1 Source Start Address Register */
    354. 

  354. #define	MDMA_S1_CONFIG			0xFFC00EC8	/* MemDMA0 Stream 1 Source Configuration Register */
    355. 

  355. #define	MDMA_S1_X_COUNT		0xFFC00ED0	/* MemDMA0 Stream 1 Source X Count Register */
    356. 

  356. #define	MDMA_S1_X_MODIFY		0xFFC00ED4	/* MemDMA0 Stream 1 Source X Modify Register */
    357. 

  357. #define	MDMA_S1_Y_COUNT		0xFFC00ED8	/* MemDMA0 Stream 1 Source Y Count Register */
    358. 

  358. #define	MDMA_S1_Y_MODIFY		0xFFC00EDC	/* MemDMA0 Stream 1 Source Y Modify Register */
    359. 

  359. #define	MDMA_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
    360. 

  360. #define	MDMA_S1_CURR_ADDR		0xFFC00EE4	/* MemDMA0 Stream 1 Source Current Address Register */
    361. 

  361. #define	MDMA_S1_IRQ_STATUS		0xFFC00EE8	/* MemDMA0 Stream 1 Source Interrupt/Status Register */
    362. 

  362. #define	MDMA_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA0 Stream 1 Source Peripheral Map Register */
    363. 

  363. #define	MDMA_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA0 Stream 1 Source Current X Count Register */
    364. 

  364. #define	MDMA_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA0 Stream 1 Source Current Y Count Register */
    365. 

  365. 

  366. 

  367. /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
    368. 

  368. #define	PPI_CONTROL			0xFFC01000	/* PPI Control Register */
    369. 

  369. #define	PPI_STATUS			0xFFC01004	/* PPI Status Register */
    370. 

  370. #define	PPI_COUNT			0xFFC01008	/* PPI Transfer	Count Register */
    371. 

  371. #define	PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register */
    372. 

  372. #define	PPI_FRAME			0xFFC01010	/* PPI Frame Length Register */
    373. 

  373. 

  374. 

  375. /* Two-Wire Interface 0	(0xFFC01400 - 0xFFC014FF)			 */
    376. 

  376. #define	TWI0_CLKDIV			0xFFC01400	/* Serial Clock	Divider	Register */
    377. 

  377. #define	TWI0_CONTROL		0xFFC01404	/* TWI0	Master Internal	Time Reference Register */
    378. 

  378. #define	TWI0_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register */
    379. 

  379. #define	TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register */
    380. 

  380. #define	TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register */
    381. 

  381. #define	TWI0_MASTER_CTL	0xFFC01414	/* Master Mode Control Register */
    382. 

  382. #define	TWI0_MASTER_STAT	0xFFC01418	/* Master Mode Status Register */
    383. 

  383. #define	TWI0_MASTER_ADDR	0xFFC0141C	/* Master Mode Address Register */
    384. 

  384. #define	TWI0_INT_STAT		0xFFC01420	/* TWI0	Master Interrupt Register */
    385. 

  385. #define	TWI0_INT_MASK		0xFFC01424	/* TWI0	Master Interrupt Mask Register */
    386. 

  386. #define	TWI0_FIFO_CTL		0xFFC01428	/* FIFO	Control	Register */
    387. 

  387. #define	TWI0_FIFO_STAT		0xFFC0142C	/* FIFO	Status Register */
    388. 

  388. #define	TWI0_XMT_DATA8		0xFFC01480	/* FIFO	Transmit Data Single Byte Register */
    389. 

  389. #define	TWI0_XMT_DATA16		0xFFC01484	/* FIFO	Transmit Data Double Byte Register */
    390. 

  390. #define	TWI0_RCV_DATA8		0xFFC01488	/* FIFO	Receive	Data Single Byte Register */
    391. 

  391. #define	TWI0_RCV_DATA16		0xFFC0148C	/* FIFO	Receive	Data Double Byte Register */
    392. 

  392. 

  393. #define TWI0_REGBASE		TWI0_CLKDIV
    394. 

  394. 

  395. /* the following are for backwards compatibility */
    396. 

  396. #define	TWI0_PRESCALE	 TWI0_CONTROL
    397. 

  397. #define	TWI0_INT_SRC	 TWI0_INT_STAT
    398. 

  398. #define	TWI0_INT_ENABLE	 TWI0_INT_MASK
    399. 

  399. 

  400. 

  401. /* General-Purpose Ports  (0xFFC01500 -	0xFFC015FF)	 */
    402. 

  402. 

  403. /* GPIO	Port C Register	Names */
    404. 

  404. #define PORTCIO_FER			0xFFC01500	/* GPIO	Pin Port C Configuration Register */
    405. 

  405. #define PORTCIO				0xFFC01510	/* GPIO	Pin Port C Data	Register */
    406. 

  406. #define PORTCIO_CLEAR			0xFFC01520	/* Clear GPIO Pin Port C Register */
    407. 

  407. #define PORTCIO_SET			0xFFC01530	/* Set GPIO Pin	Port C Register */
    408. 

  408. #define PORTCIO_TOGGLE			0xFFC01540	/* Toggle GPIO Pin Port	C Register */
    409. 

  409. #define PORTCIO_DIR			0xFFC01550	/* GPIO	Pin Port C Direction Register */
    410. 

  410. #define PORTCIO_INEN			0xFFC01560	/* GPIO	Pin Port C Input Enable	Register */
    411. 

  411. 

  412. /* GPIO	Port D Register	Names */
    413. 

  413. #define PORTDIO_FER			0xFFC01504	/* GPIO	Pin Port D Configuration Register */
    414. 

  414. #define PORTDIO				0xFFC01514	/* GPIO	Pin Port D Data	Register */
    415. 

  415. #define PORTDIO_CLEAR			0xFFC01524	/* Clear GPIO Pin Port D Register */
    416. 

  416. #define PORTDIO_SET			0xFFC01534	/* Set GPIO Pin	Port D Register */
    417. 

  417. #define PORTDIO_TOGGLE			0xFFC01544	/* Toggle GPIO Pin Port	D Register */
    418. 

  418. #define PORTDIO_DIR			0xFFC01554	/* GPIO	Pin Port D Direction Register */
    419. 

  419. #define PORTDIO_INEN			0xFFC01564	/* GPIO	Pin Port D Input Enable	Register */
    420. 

  420. 

  421. /* GPIO	Port E Register	Names */
    422. 

  422. #define PORTEIO_FER			0xFFC01508	/* GPIO	Pin Port E Configuration Register */
    423. 

  423. #define PORTEIO				0xFFC01518	/* GPIO	Pin Port E Data	Register */
    424. 

  424. #define PORTEIO_CLEAR			0xFFC01528	/* Clear GPIO Pin Port E Register */
    425. 

  425. #define PORTEIO_SET			0xFFC01538	/* Set GPIO Pin	Port E Register */
    426. 

  426. #define PORTEIO_TOGGLE			0xFFC01548	/* Toggle GPIO Pin Port	E Register */
    427. 

  427. #define PORTEIO_DIR			0xFFC01558	/* GPIO	Pin Port E Direction Register */
    428. 

  428. #define PORTEIO_INEN			0xFFC01568	/* GPIO	Pin Port E Input Enable	Register */
    429. 

  429. 

  430. /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
    431. 

  431. 

  432. #define	DMAC1_TC_PER			0xFFC01B0C	/* DMA Controller 1 Traffic Control Periods Register */
    433. 

  433. #define	DMAC1_TC_CNT			0xFFC01B10	/* DMA Controller 1 Traffic Control Current Counts Register */
    434. 

  434. 

  435. 

  436. 

  437. /* DMA Controller 1 (0xFFC01C00	- 0xFFC01FFF)							 */
    438. 

  438. #define	DMA8_NEXT_DESC_PTR		0xFFC01C00	/* DMA Channel 8 Next Descriptor Pointer Register */
    439. 

  439. #define	DMA8_START_ADDR			0xFFC01C04	/* DMA Channel 8 Start Address Register */
    440. 

  440. #define	DMA8_CONFIG				0xFFC01C08	/* DMA Channel 8 Configuration Register */
    441. 

  441. #define	DMA8_X_COUNT			0xFFC01C10	/* DMA Channel 8 X Count Register */
    442. 

  442. #define	DMA8_X_MODIFY			0xFFC01C14	/* DMA Channel 8 X Modify Register */
    443. 

  443. #define	DMA8_Y_COUNT			0xFFC01C18	/* DMA Channel 8 Y Count Register */
    444. 

  444. #define	DMA8_Y_MODIFY			0xFFC01C1C	/* DMA Channel 8 Y Modify Register */
    445. 

  445. #define	DMA8_CURR_DESC_PTR		0xFFC01C20	/* DMA Channel 8 Current Descriptor Pointer Register */
    446.