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waterDataDiscreteRateMining
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monitoringDataProcessing
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connectionSignalSlot.h

connectionSignalSlot.h 1.9 KB
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  1. 

  2. /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2000-2001	Lineo Inc. <www.lineo.com>
    5. 

  5.  * Copyright (c) 2000-2001	Lineo Canada Corp. <www.lineo.ca>
    6. 

  6.  * Copyright (C) 1999		Vladimir Gurevich <vgurevic@cisco.com>
    7. 

  7.  * 				Bare & Hare Software, Inc.
    8. 

  8.  * Based on include/asm-m68knommu/MC68332.h
    9. 

  9.  * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
    10. 

  10.  *                     The Silver Hammer Group, Ltd.
    11. 

  11.  *
    12. 

  12.  * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
    13. 

  13.  * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
    14. 

  14.  */
    15. 

  15. 

  16. #ifndef _MC68VZ328_H_
    17. 

  17. #define _MC68VZ328_H_
    18. 

  18. 

  19. #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
    20. 

  20. #define WORD_REF(addr) (*((volatile unsigned short*)addr))
    21. 

  21. #define LONG_REF(addr) (*((volatile unsigned long*)addr))
    22. 

  22. 

  23. #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
    24. 

  24. #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
    25. 

  25. 

  26. /********** 
    27. 

  27.  *
    28. 

  28.  * 0xFFFFF0xx -- System Control
    29. 

  29.  *
    30. 

  30.  **********/
    31. 

  31.  
    32. 

  32. /*
    33. 

  33.  * System Control Register (SCR)
    34. 

  34.  */
    35. 

  35. #define SCR_ADDR	0xfffff000
    36. 

  36. #define SCR		BYTE_REF(SCR_ADDR)
    37. 

  37. 

  38. #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
    39. 

  39. #define SCR_DMAP	0x04	/* Double Map */
    40. 

  40. #define SCR_SO		0x08	/* Supervisor Only */
    41. 

  41. #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
    42. 

  42. #define SCR_PRV		0x20	/* Privilege Violation */
    43. 

  43. #define SCR_WPV		0x40	/* Write Protect Violation */
    44. 

  44. #define SCR_BETO	0x80	/* Bus-Error TimeOut */
    45. 

  45. 

  46. /*
    47. 

  47.  * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
    48. 

  48.  */
    49. 

  49. #define MRR_ADDR 0xfffff004
    50. 

  50. #define MRR	 LONG_REF(MRR_ADDR)
    51. 

  51. 

  52. /********** 
    53. 

  53.  *
    54. 

  54.  * 0xFFFFF1xx -- Chip-Select logic
    55. 

  55.  *
    56. 

  56.  **********/
    57. 

  57.  
    58. 

  58. /*
    59. 

  59.  * Chip Select Group Base Registers 
    60. 

  60.  */
    61. 

  61. #define CSGBA_ADDR	0xfffff100
    62. 

  62. #define CSGBB_ADDR	0xfffff102
    63. 

  63. 

  64. #define CSGBC_ADDR	0xfffff104
    65. 

  65. #define CSGBD_ADDR	0xfffff106
    66. 

  66. 

  67. #define CSGBA		WORD_REF(CSGBA_ADDR)
    68. 

  68. #define CSGBB		WORD_REF(CSGBB_ADDR)
    69. 

  69. #define CSGBC		WORD_REF(CSGBC_ADDR)
    70.