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aiot
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waterDataPreprocessing
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dataProcessing
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basicAlgorithmEncapsulation.h

basicAlgorithmEncapsulation.h 12 KB
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  1. /*
    2. 

  2.  * Copyright 2007-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF54X_H
    8. 

  8. #define _DEF_BF54X_H
    9. 

  9. 

  10. 

  11. /* ************************************************************** */
    12. 

  12. /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
    13. 

  13. /* ************************************************************** */
    14. 

  14. 

  15. /* PLL Registers */
    16. 

  16. 

  17. #define                          PLL_CTL  0xffc00000   /* PLL Control Register */
    18. 

  18. #define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
    19. 

  19. #define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
    20. 

  20. #define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
    21. 

  21. #define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
    22. 

  22. 

  23. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
    24. 

  24. 

  25. #define                           CHIPID  0xffc00014
    26. 

  26. /* CHIPID Masks */
    27. 

  27. #define                   CHIPID_VERSION  0xF0000000
    28. 

  28. #define                    CHIPID_FAMILY  0x0FFFF000
    29. 

  29. #define               CHIPID_MANUFACTURE  0x00000FFE
    30. 

  30. 

  31. /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
    32. 

  32. 

  33. #define                            SWRST  0xffc00100   /* Software Reset Register */
    34. 

  34. #define                            SYSCR  0xffc00104   /* System Configuration register */
    35. 

  35. 

  36. /* SIC Registers */
    37. 

  37. 

  38. #define                        SIC_RVECT  0xffc00108
    39. 

  39. #define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
    40. 

  40. #define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
    41. 

  41. #define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
    42. 

  42. #define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
    43. 

  43. #define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
    44. 

  44. #define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
    45. 

  45. #define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
    46. 

  46. #define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
    47. 

  47. #define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
    48. 

  48. #define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
    49. 

  49. #define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
    50. 

  50. #define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
    51. 

  51. #define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
    52. 

  52. #define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
    53. 

  53. #define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
    54. 

  54. #define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
    55. 

  55. #define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
    56. 

  56. #define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
    57. 

  57. #define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
    58. 

  58. #define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
    59. 

  59. #define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
    60. 

  60. 

  61. /* Watchdog Timer Registers */
    62. 

  62. 

  63. #define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
    64. 

  64. #define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
    65. 

  65. #define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
    66. 

  66. 

  67. /* RTC Registers */
    68. 

  68. 

  69. #define                         RTC_STAT  0xffc00300   /* RTC Status Register */
    70. 

  70. #define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
    71. 

  71. #define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
    72. 

  72. #define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
    73. 

  73. #define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
    74. 

  74. #define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
    75. 

  75. 

  76. /* UART0 Registers */
    77. 

  77. 

  78. #define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
    79. 

  79. #define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
    80. 

  80. #define                       UART0_GCTL  0xffc00408   /* Global Control Register */
    81. 

  81. #define                        UART0_LCR  0xffc0040c   /* Line Control Register */
    82. 

  82. #define                        UART0_MCR  0xffc00410   /* Modem Control Register */
    83. 

  83. #define                        UART0_LSR  0xffc00414   /* Line Status Register */
    84. 

  84. #define                        UART0_MSR  0xffc00418   /* Modem Status Register */
    85. 

  85. #define                        UART0_SCR  0xffc0041c   /* Scratch Register */
    86. 

  86. #define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
    87. 

  87. #define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
    88. 

  88. #define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
    89. 

  89. #define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
    90. 

  90. 

  91. /* SPI0 Registers */
    92. 

  92. 

  93. #define                     SPI0_REGBASE  0xffc00500
    94. 

  94. #define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
    95. 

  95. #define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
    96. 

  96. #define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
    97. 

  97. #define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
    98. 

  98. #define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
    99. 

  99. #define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
    100. 

  100. #define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
    101. 

  101. 

  102. /* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
    103. 

  103. 

  104. /* Two Wire Interface Registers (TWI0) */
    105. 

  105. 

  106. #define                     TWI0_REGBASE  0xffc00700
    107. 

  107. #define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
    108. 

  108. #define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
    109. 

  109. #define                   TWI0_SLAVE_CTL  0xffc00708   /* TWI Slave Mode Control Register */
    110. 

  110. #define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
    111. 

  111. #define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
    112. 

  112. #define                  TWI0_MASTER_CTL  0xffc00714   /* TWI Master Mode Control Register */
    113. 

  113. #define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
    114. 

  114. #define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
    115. 

  115. #define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
    116. 

  116. #define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
    117. 

  117. #define                    TWI0_FIFO_CTL  0xffc00728   /* TWI FIFO Control Register */
    118. 

  118. #define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
    119. 

  119. #define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
    120. 

  120. #define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
    121. 

  121. #define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
    122. 

  122. #define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
    123. 

  123. 

  124. /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
    125. 

  125. 

  126. /* SPORT1 Registers */
    127. 

  127. 

  128. #define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
    129. 

  129. #define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
    130. 

  130. #define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
    131. 

  131. #define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
    132. 

  132. #define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
    133. 

  133. #define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
    134. 

  134. #define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
    135. 

  135. #define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
    136. 

  136. #define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
    137. 

  137. #define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
    138. 

  138. #define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
    139. 

  139. #define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
    140. 

  140. #define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
    141. 

  141. #define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
    142. 

  142. #define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
    143. 

  143. #define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
    144. 

  144. #define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
    145. 

  145. #define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
    146. 

  146. #define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
    147. 

  147. #define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
    148. 

  148. #define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
    149. 

  149. #define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
    150. 

  150. 

  151. /* Asynchronous Memory Control Registers */
    152. 

  152. 

  153. #define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
    154. 

  154. #define                    EBIU_AMBCTL0   0xffc00a04   /* Asynchronous Memory Bank Control Register */
    155. 

  155. #define                    EBIU_AMBCTL1   0xffc00a08   /* Asynchronous Memory Bank Control Register */
    156. 

  156. #define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
    157. 

  157. #define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
    158. 

  158. #define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
    159. 

  159. #define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
    160. 

  160. 

  161. /* DDR Memory Control Registers */
    162. 

  162. 

  163. #define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
    164. 

  164. #define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
    165. 

  165. #define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
    166. 

  166. #define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
    167. 

  167. #define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
    168. 

  168. #define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
    169. 

  169. #define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
    170. 

  170. #define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
    171. 

  171. 

  172. /* DDR BankRead and Write Count Registers */
    173. 

  173. 

  174. #define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
    175. 

  175. #define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
    176. 

  176. #define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
    177. 

  177. #define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
    178. 

  178. #define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
    179. 

  179. #define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
    180. 

  180. #define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
    181.