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commandProcessing.h

commandProcessing.h 102 KB
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  1. /*
    2. 

  2.  * Copyright 2011 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF60X_H
    8. 

  8. #define _DEF_BF60X_H
    9. 

  9. 

  10. 

  11. /* ************************************************************** */
    12. 

  12. /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
    13. 

  13. /* ************************************************************** */
    14. 

  14. 

  15. 

  16. /* =========================
    17. 

  17.         CNT Registers
    18. 

  18.    ========================= */
    19. 

  19. 

  20. /* =========================
    21. 

  21.         CNT0
    22. 

  22.    ========================= */
    23. 

  23. #define CNT_CONFIG                 0xFFC00400         /* CNT0 Configuration Register */
    24. 

  24. #define CNT_IMASK                  0xFFC00404         /* CNT0 Interrupt Mask Register */
    25. 

  25. #define CNT_STATUS                 0xFFC00408         /* CNT0 Status Register */
    26. 

  26. #define CNT_COMMAND                0xFFC0040C         /* CNT0 Command Register */
    27. 

  27. #define CNT_DEBOUNCE               0xFFC00410         /* CNT0 Debounce Register */
    28. 

  28. #define CNT_COUNTER                0xFFC00414         /* CNT0 Counter Register */
    29. 

  29. #define CNT_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
    30. 

  30. #define CNT_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
    31. 

  31. 

  32. 

  33. /* =========================
    34. 

  34.         RSI Registers
    35. 

  35.    ========================= */
    36. 

  36. 

  37. #define RSI_CLK_CONTROL            0xFFC00604         /* RSI0 Clock Control Register */
    38. 

  38. #define RSI_ARGUMENT               0xFFC00608         /* RSI0 Argument Register */
    39. 

  39. #define RSI_COMMAND                0xFFC0060C         /* RSI0 Command Register */
    40. 

  40. #define RSI_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
    41. 

  41. #define RSI_RESPONSE0              0xFFC00614         /* RSI0 Response 0 Register */
    42. 

  42. #define RSI_RESPONSE1              0xFFC00618         /* RSI0 Response 1 Register */
    43. 

  43. #define RSI_RESPONSE2              0xFFC0061C         /* RSI0 Response 2 Register */
    44. 

  44. #define RSI_RESPONSE3              0xFFC00620         /* RSI0 Response 3 Register */
    45. 

  45. #define RSI_DATA_TIMER             0xFFC00624         /* RSI0 Data Timer Register */
    46. 

  46. #define RSI_DATA_LGTH              0xFFC00628         /* RSI0 Data Length Register */
    47. 

  47. #define RSI_DATA_CONTROL           0xFFC0062C         /* RSI0 Data Control Register */
    48. 

  48. #define RSI_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
    49. 

  49. #define RSI_STATUS                 0xFFC00634         /* RSI0 Status Register */
    50. 

  50. #define RSI_STATUSCL               0xFFC00638         /* RSI0 Status Clear Register */
    51. 

  51. #define RSI_MASK0                  0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
    52. 

  52. #define RSI_MASK1                  0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
    53. 

  53. #define RSI_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
    54. 

  54. #define RSI_CEATA_CONTROL          0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
    55. 

  55. #define RSI_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
    56. 

  56. #define RSI_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
    57. 

  57. #define RSI_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
    58. 

  58. #define RSI_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
    59. 

  59. #define RSI_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
    60. 

  60. #define RSI_ESTAT                  0xFFC006C0         /* RSI0 Exception Status Register */
    61. 

  61. #define RSI_EMASK                  0xFFC006C4         /* RSI0 Exception Mask Register */
    62. 

  62. #define RSI_CONFIG                 0xFFC006C8         /* RSI0 Configuration Register */
    63. 

  63. #define RSI_RD_WAIT_EN             0xFFC006CC         /* RSI0 Read Wait Enable Register */
    64. 

  64. #define RSI_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
    65. 

  65. #define RSI_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
    66. 

  66. #define RSI_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
    67. 

  67. #define RSI_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
    68. 

  68. 

  69. /* =========================
    70. 

  70.         CAN Registers
    71. 

  71.    ========================= */
    72. 

  72. 

  73. /* =========================
    74. 

  74.         CAN0
    75. 

  75.    ========================= */
    76. 

  76. #define CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration Register 1 */
    77. 

  77. #define CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction Register 1 */
    78. 

  78. #define CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set Register 1 */
    79. 

  79. #define CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset Register 1 */
    80. 

  80. #define CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge Register 1 */
    81. 

  81. #define CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge Register 1 */
    82. 

  82. #define CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending Register 1 */
    83. 

  83. #define CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost Register 1 */
    84. 

  84. #define CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
    85. 

  85. #define CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
    86. 

  86. #define CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask Register 1 */
    87. 

  87. #define CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling Register 1 */
    88. 

  88. #define CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
    89. 

  89. #define CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration Register 2 */
    90. 

  90. #define CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction Register 2 */
    91. 

  91. #define CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set Register 2 */
    92. 

  92. #define CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset Register 2 */
    93. 

  93. #define CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge Register 2 */
    94. 

  94. #define CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge Register 2 */
    95. 

  95. #define CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending Register 2 */
    96. 

  96. #define CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost Register 2 */
    97. 

  97. #define CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
    98. 

  98. #define CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
    99. 

  99. #define CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask Register 2 */
    100. 

  100. #define CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling Register 2 */
    101. 

  101. #define CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
    102. 

  102. #define CAN0_CLOCK                    0xFFC00A80         /* CAN0 Clock Register */
    103. 

  103. #define CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
    104. 

  104. #define CAN0_DEBUG                    0xFFC00A88         /* CAN0 Debug Register */
    105. 

  105. #define CAN0_STATUS                   0xFFC00A8C         /* CAN0 Status Register */
    106. 

  106. #define CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
    107. 

  107. #define CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status */
    108. 

  108. #define CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask */
    109. 

  109. #define CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag */
    110. 

  110. #define CAN0_CONTROL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
    111. 

  111. #define CAN0_INTR                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
    112. 

  112. #define CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
    113. 

  113. #define CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
    114. 

  114. #define CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
    115. 

  115. #define CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
    116. 

  116. #define CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
    117. 

  117. #define CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
    118. 

  118. #define CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask Register (L) */
    119. 

  119. #define CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask Register (L) */
    120. 

  120. #define CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask Register (L) */
    121. 

  121. #define CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask Register (L) */
    122. 

  122. #define CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask Register (L) */
    123. 

  123. #define CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask Register (L) */
    124. 

  124. #define CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask Register (L) */
    125. 

  125. #define CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask Register (L) */
    126. 

  126. #define CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask Register (L) */
    127. 

  127. #define CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask Register (L) */
    128. 

  128. #define CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask Register (L) */
    129. 

  129. #define CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask Register (L) */
    130. 

  130. #define CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask Register (L) */
    131. 

  131. #define CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask Register (L) */
    132. 

  132. #define CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask Register (L) */
    133. 

  133. #define CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask Register (L) */
    134. 

  134. #define CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask Register (L) */
    135. 

  135. #define CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask Register (L) */
    136. 

  136. #define CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask Register (L) */
    137. 

  137. #define CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask Register (L) */
    138. 

  138. #define CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask Register (L) */
    139. 

  139. #define CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask Register (L) */
    140. 

  140. #define CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask Register (L) */
    141. 

  141. #define CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask Register (L) */
    142. 

  142. #define CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask Register (L) */
    143. 

  143. #define CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask Register (L) */
    144. 

  144. #define CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask Register (L) */
    145. 

  145. #define CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask Register (L) */
    146. 

  146. #define CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask Register (L) */
    147. 

  147. #define CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask Register (L) */
    148. 

  148. #define CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask Register (L) */
    149. 

  149. #define CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask Register (L) */
    150. 

  150. #define CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask Register (H) */
    151. 

  151. #define CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask Register (H) */
    152. 

  152. #define CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask Register (H) */
    153. 

  153. #define CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask Register (H) */
    154. 

  154. #define CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask Register (H) */
    155. 

  155. #define CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask Register (H) */
    156. 

  156. #define CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask Register (H) */
    157. 

  157. #define CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask Register (H) */
    158. 

  158. #define CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask Register (H) */
    159. 

  159. #define CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask Register (H) */
    160. 

  160. #define CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask Register (H) */
    161. 

  161. #define CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask Register (H) */
    162. 

  162. #define CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask Register (H) */
    163. 

  163. #define CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask Register (H) */
    164. 

  164. #define CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask Register (H) */
    165. 

  165. #define CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask Register (H) */
    166. 

  166. #define CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask Register (H) */
    167. 

  167. #define CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask Register (H) */
    168. 

  168. #define CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask Register (H) */
    169. 

  169. #define CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask Register (H) */
    170. 

  170. #define CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask Register (H) */
    171. 

  171. #define CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask Register (H) */
    172. 

  172. #define CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask Register (H) */
    173. 

  173. #define CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask Register (H) */
    174. 

  174. #define CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask Register (H) */
    175. 

  175. #define CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask Register (H) */
    176. 

  176. #define CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask Register (H) */
    177. 

  177. #define CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask Register (H) */
    178. 

  178. #define CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask Register (H) */
    179. 

  179. #define CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask Register (H) */
    180. 

  180. #define CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask Register (H) */
    181. 

  181. #define CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask Register (H) */
    182. 

  182. #define CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
    183. 

  183. #define CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
    184. 

  184. #define CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
    185. 

  185. #define CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
    186. 

  186. #define CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
    187. 

  187. #define CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
    188. 

  188. #define CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
    189. 

  189. #define CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
    190. 

  190. #define CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
    191. 

  191. #define CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
    192. 

  192. #define CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
    193. 

  193. #define CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
    194. 

  194. #define CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
    195. 

  195. #define CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
    196. 

  196. #define CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
    197. 

  197. #define CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
    198. 

  198. #define CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
    199. 

  199. #define CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
    200. 

  200. #define CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
    201. 

  201. #define CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
    202. 

  202. #define CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
    203. 

  203. #define CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
    204. 

  204. #define CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
    205. 

  205. #define CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
    206. 

  206. #define CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
    207. 

  207. #define CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
    208. 

  208. #define CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
    209. 

  209. #define CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
    210. 

  210. #define CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
    211. 

  211. #define CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
    212. 

  212. #define CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
    213. 

  213. #define CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
    214. 

  214. #define CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
    215. 

  215. #define CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
    216. 

  216. #define CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
    217. 

  217. #define CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
    218. 

  218. #define CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
    219. 

  219. #define CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
    220. 

  220. #define CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
    221. 

  221. #define CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
    222. 

  222. #define CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
    223. 

  223. #define CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
    224. 

  224. #define CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
    225. 

  225. #define CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
    226. 

  226. #define CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
    227. 

  227. #define CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
    228. 

  228. #define CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
    229. 

  229. #define CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
    230. 

  230. #define CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
    231. 

  231. #define CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
    232. 

  232. #define CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
    233. 

  233. #define CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
    234. 

  234. #define CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
    235. 

  235. #define CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
    236. 

  236. #define CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
    237. 

  237. #define CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
    238. 

  238. #define CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
    239. 

  239. #define CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
    240. 

  240. #define CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
    241. 

  241. #define CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
    242. 

  242. #define CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
    243. 

  243. #define CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
    244. 

  244. #define CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
    245. 

  245. #define CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
    246. 

  246. #define CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
    247. 

  247. #define CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
    248. 

  248. #define CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
    249. 

  249. #define CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
    250. 

  250. #define CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
    251. 

  251. #define CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
    252. 

  252. #define CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
    253. 

  253. #define CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
    254. 

  254. #define CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
    255. 

  255. #define CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
    256. 

  256. #define CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
    257. 

  257. #define CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
    258. 

  258. #define CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
    259. 

  259. #define CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
    260. 

  260. #define CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
    261. 

  261. #define CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
    262. 

  262. #define CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
    263. 

  263. #define CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
    264. 

  264. #define CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
    265. 

  265. #define CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
    266. 

  266. #define CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
    267. 

  267. #define CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
    268. 

  268. #define CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
    269. 

  269. #define CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
    270. 

  270. #define CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
    271. 

  271. #define CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
    272. 

  272. #define CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
    273. 

  273. #define CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
    274. 

  274. #define CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
    275. 

  275. #define CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
    276. 

  276. #define CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
    277. 

  277. #define CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
    278. 

  278. #define CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
    279. 

  279. #define CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
    280. 

  280. #define CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
    281. 

  281. #define CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
    282. 

  282. #define CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
    283. 

  283. #define CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
    284. 

  284. #define CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
    285. 

  285. #define CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
    286. 

  286. #define CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
    287. 

  287. #define CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
    288. 

  288. #define CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
    289. 

  289. #define CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
    290. 

  290. #define CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
    291. 

  291. #define CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
    292. 

  292. #define CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
    293. 

  293. #define CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
    294. 

  294. #define CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
    295. 

  295. #define CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
    296. 

  296. #define CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
    297. 

  297. #define CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
    298. 

  298. #define CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
    299. 

  299. #define CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
    300. 

  300. #define CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
    301. 

  301. #define CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
    302. 

  302. #define CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
    303. 

  303. #define CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
    304. 

  304. #define CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
    305. 

  305. #define CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
    306. 

  306. #define CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
    307. 

  307. #define CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
    308. 

  308. #define CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
    309. 

  309. #define CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
    310. 

  310. #define CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Word 4 Register */
    311. 

  311. #define CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Word 4 Register */
    312. 

  312. #define CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Word 4 Register */
    313. 

  313. #define CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Word 4 Register */
    314. 

  314. #define CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Word 4 Register */
    315. 

  315. #define CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Word 4 Register */
    316. 

  316. #define CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Word 4 Register */
    317. 

  317. #define CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Word 4 Register */
    318. 

  318. #define CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Word 4 Register */
    319. 

  319. #define CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Word 4 Register */
    320. 

  320. #define CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Word 4 Register */
    321. 

  321. #define CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Word 4 Register */
    322. 

  322. #define CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Word 4 Register */
    323. 

  323. #define CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Word 4 Register */
    324. 

  324. #define CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Word 4 Register */
    325. 

  325. #define CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Word 4 Register */
    326. 

  326. #define CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Word 4 Register */
    327. 

  327. #define CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Word 4 Register */
    328. 

  328. #define CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Word 4 Register */
    329. 

  329. #define CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Word 4 Register */
    330. 

  330. #define CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Word 4 Register */
    331. 

  331. #define CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Word 4 Register */
    332. 

  332. #define CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Word 4 Register */
    333. 

  333. #define CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Word 4 Register */
    334. 

  334. #define CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Word 4 Register */
    335. 

  335. #define CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Word 4 Register */
    336. 

  336. #define CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Word 4 Register */
    337. 

  337. #define CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Word 4 Register */
    338. 

  338. #define CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Word 4 Register */
    339. 

  339. #define CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Word 4 Register */
    340. 

  340. #define CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Word 4 Register */
    341. 

  341. #define CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Word 4 Register */
    342. 

  342. #define CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Word 5 Register */
    343. 

  343. #define CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Word 5 Register */
    344. 

  344. #define CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Word 5 Register */
    345. 

  345. #define CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Word 5 Register */
    346. 

  346. #define CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Word 5 Register */
    347. 

  347. #define CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Word 5 Register */
    348. 

  348. #define CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Word 5 Register */
    349. 

  349. #define CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Word 5 Register */
    350. 

  350. #define CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Word 5 Register */
    351. 

  351. #define CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Word 5 Register */
    352. 

  352. #define CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Word 5 Register */
    353. 

  353. #define CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Word 5 Register */
    354. 

  354. #define CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Word 5 Register */
    355. 

  355. #define CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Word 5 Register */
    356. 

  356. #define CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Word 5 Register */
    357. 

  357. #define CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Word 5 Register */
    358. 

  358. #define CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Word 5 Register */
    359. 

  359. #define CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Word 5 Register */
    360. 

  360. #define CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Word 5 Register */
    361. 

  361. #define CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Word 5 Register */
    362. 

  362. #define CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Word 5 Register */
    363. 

  363. #define CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Word 5 Register */
    364. 

  364. #define CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Word 5 Register */
    365. 

  365. #define CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Word 5 Register */
    366. 

  366. #define CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Word 5 Register */
    367. 

  367. #define CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Word 5 Register */
    368. 

  368. #define CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Word 5 Register */
    369. 

  369. #define CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Word 5 Register */
    370. 

  370. #define CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Word 5 Register */
    371. 

  371. #define CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Word 5 Register */
    372. 

  372. #define CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Word 5 Register */
    373. 

  373. #define CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Word 5 Register */
    374. 

  374. #define CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox Word 6 Register */
    375. 

  375. #define CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox Word 6 Register */
    376. 

  376. #define CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox Word 6 Register */
    377. 

  377. #define CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox Word 6 Register */
    378. 

  378. #define CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox Word 6 Register */
    379. 

  379. #define CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox Word 6 Register */
    380. 

  380. #define CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox Word 6 Register */
    381. 

  381. #define CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox Word 6 Register */
    382. 

  382. #define CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox Word 6 Register */
    383. 

  383. #define CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox Word 6 Register */
    384. 

  384. #define CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox Word 6 Register */
    385. 

  385. #define CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox Word 6 Register */
    386. 

  386. #define CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox Word 6 Register */
    387. 

  387. #define CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox Word 6 Register */
    388. 

  388. #define CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox Word 6 Register */
    389. 

  389. #define CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox Word 6 Register */
    390. 

  390. #define CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox Word 6 Register */
    391. 

  391. #define CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox Word 6 Register */
    392. 

  392. #define CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox Word 6 Register */
    393. 

  393. #define CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox Word 6 Register */
    394. 

  394. #define CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox Word 6 Register */
    395. 

  395. #define CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox Word 6 Register */
    396. 

  396. #define CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox Word 6 Register */
    397. 

  397. #define CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox Word 6 Register */
    398. 

  398. #define CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox Word 6 Register */
    399. 

  399. #define CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox Word 6 Register */
    400. 

  400. #define CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox Word 6 Register */
    401. 

  401. #define CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox Word 6 Register */
    402. 

  402. #define CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox Word 6 Register */
    403. 

  403. #define CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox Word 6 Register */
    404. 

  404. #define CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox Word 6 Register */
    405. 

  405. #define CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox Word 6 Register */
    406. 

  406. #define CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox Word 7 Register */
    407. 

  407. #define CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox Word 7 Register */
    408. 

  408. #define CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox Word 7 Register */
    409. 

  409. #define CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox Word 7 Register */
    410. 

  410. #define CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox Word 7 Register */
    411. 

  411. #define CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox Word 7 Register */
    412. 

  412. #define CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox Word 7 Register */
    413. 

  413. #define CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox Word 7 Register */
    414. 

  414. #define CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox Word 7 Register */
    415. 

  415. #define CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox Word 7 Register */
    416. 

  416. #define CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox Word 7 Register */
    417. 

  417. #define CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox Word 7 Register */
    418. 

  418. #define CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox Word 7 Register */
    419. 

  419. #define CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox Word 7 Register */
    420. 

  420. #define CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox Word 7 Register */
    421. 

  421. #define CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox Word 7 Register */
    422. 

  422. #define CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox Word 7 Register */
    423. 

  423. #define CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox Word 7 Register */
    424. 

  424. #define CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox Word 7 Register */
    425. 

  425. #define CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox Word 7 Register */
    426. 

  426. #define CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox Word 7 Register */
    427. 

  427. #define CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox Word 7 Register */
    428. 

  428. #define CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox Word 7 Register */
    429. 

  429. #define CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox Word 7 Register */
    430. 

  430. #define CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox Word 7 Register */
    431. 

  431. #define CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox Word 7 Register */
    432. 

  432. #define CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox Word 7 Register */
    433. 

  433. #define CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox Word 7 Register */
    434. 

  434. #define CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox Word 7 Register */
    435. 

  435. #define CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox Word 7 Register */
    436. 

  436. #define CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox Word 7 Register */
    437. 

  437. #define CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox Word 7 Register */
    438. 

  438. 

  439. /* =========================
    440. 

  440. 	LINK PORT Registers
    441. 

  441.    ========================= */
    442. 

  442. #define LP0_CTL                     0xFFC01000         /* LP0 Control Register */
    443. 

  443. #define LP0_STAT                    0xFFC01004         /* LP0 Status Register */
    444. 

  444. #define LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
    445. 

  445. #define LP0_CNT                     0xFFC0100C         /* LP0 Current Count Value of Clock Divider */
    446. 

  446. #define LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
    447. 

  447. #define LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
    448. 

  448. #define LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
    449. 

  449. #define LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
    450. 

  450. #define LP1_CTL                     0xFFC01100         /* LP1 Control Register */
    451. 

  451. #define LP1_STAT                    0xFFC01104         /* LP1 Status Register */
    452. 

  452. #define LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
    453. 

  453. #define LP1_CNT                     0xFFC0110C         /* LP1 Current Count Value of Clock Divider */
    454. 

  454. #define LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
    455. 

  455. #define LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
    456. 

  456. #define LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
    457. 

  457. #define LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
    458. 

  458. #define LP2_CTL                     0xFFC01200         /* LP2 Control Register */
    459. 

  459. #define LP2_STAT                    0xFFC01204         /* LP2 Status Register */
    460. 

  460. #define LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
    461. 

  461. #define LP2_CNT                     0xFFC0120C         /* LP2 Current Count Value of Clock Divider */
    462. 

  462. #define LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
    463. 

  463. #define LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
    464. 

  464. #define LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
    465. 

  465. #define LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
    466. 

  466. #define LP3_CTL                     0xFFC01300         /* LP3 Control Register */
    467. 

  467. #define LP3_STAT                    0xFFC01304         /* LP3 Status Register */
    468. 

  468. #define LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
    469. 

  469. #define LP3_CNT                     0xFFC0130C         /* LP3 Current Count Value of Clock Divider */
    470. 

  470. #define LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
    471. 

  471. #define LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
    472. 

  472. #define LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
    473. 

  473. #define LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
    474. 

  474. 

  475. /* =========================
    476. 

  476.         TIMER Registers
    477. 

  477.    ========================= */
    478. 

  478. #define TIMER_REVID                0xFFC01400         /* GPTIMER Timer IP Version ID */
    479. 

  479. #define TIMER_RUN                  0xFFC01404         /* GPTIMER Timer Run Register */
    480. 

  480. #define TIMER_RUN_SET              0xFFC01408         /* GPTIMER Run Register Alias to Set */
    481. 

  481. #define TIMER_RUN_CLR              0xFFC0140C         /* GPTIMER Run Register Alias to Clear */
    482. 

  482. #define TIMER_STOP_CFG             0xFFC01410         /* GPTIMER Stop Config Register */
    483. 

  483. #define TIMER_STOP_CFG_SET         0xFFC01414         /* GPTIMER Stop Config Alias to Set */
    484. 

  484. #define TIMER_STOP_CFG_CLR         0xFFC01418         /* GPTIMER Stop Config Alias to Clear */
    485. 

  485. #define TIMER_DATA_IMSK            0xFFC0141C         /* GPTIMER Data Interrupt Mask register */
    486. 

  486. #define TIMER_STAT_IMSK            0xFFC01420         /* GPTIMER Status Interrupt Mask register */
    487. 

  487. #define TIMER_TRG_MSK              0xFFC01424         /* GPTIMER Output Trigger Mask register */
    488. 

  488. #define TIMER_TRG_IE               0xFFC01428         /* GPTIMER Slave Trigger Enable register */
    489. 

  489. #define TIMER_DATA_ILAT            0xFFC0142C         /* GPTIMER Data Interrupt Register */
    490. 

  490. #define TIMER_STAT_ILAT            0xFFC01430         /* GPTIMER Status (Error) Interrupt Register */
    491. 

  491. #define TIMER_ERR_TYPE             0xFFC01434         /* GPTIMER Register Indicating Type of Error */
    492. 

  492. #define TIMER_BCAST_PER            0xFFC01438         /* GPTIMER Broadcast Period */
    493. 

  493. #define TIMER_BCAST_WID            0xFFC0143C         /* GPTIMER Broadcast Width */
    494. 

  494. #define TIMER_BCAST_DLY            0xFFC01440         /* GPTIMER Broadcast Delay */
    495. 

  495. 

  496. /* =========================
    497. 

  497. 	TIMER0~7
    498. 

  498.    ========================= */
    499. 

  499. #define TIMER0_CONFIG             0xFFC01460         /* TIMER0 Per Timer Config Register */
    500. 

  500. #define TIMER0_COUNTER            0xFFC01464         /* TIMER0 Per Timer Counter Register */
    501. 

  501. #define TIMER0_PERIOD             0xFFC01468         /* TIMER0 Per Timer Period Register */
    502. 

  502. #define TIMER0_WIDTH              0xFFC0146C         /* TIMER0 Per Timer Width Register */
    503. 

  503. #define TIMER0_DELAY              0xFFC01470         /* TIMER0 Per Timer Delay Register */
    504. 

  504. 

  505. #define TIMER1_CONFIG             0xFFC01480         /* TIMER1 Per Timer Config Register */
    506. 

  506. #define TIMER1_COUNTER            0xFFC01484         /* TIMER1 Per Timer Counter Register */
    507. 

  507. #define TIMER1_PERIOD             0xFFC01488         /* TIMER1 Per Timer Period Register */
    508. 

  508. #define TIMER1_WIDTH              0xFFC0148C         /* TIMER1 Per Timer Width Register */
    509. 

  509. #define TIMER1_DELAY              0xFFC01490         /* TIMER1 Per Timer Delay Register */
    510. 

  510. 

  511. #define TIMER2_CONFIG             0xFFC014A0         /* TIMER2 Per Timer Config Register */
    512. 

  512. #define TIMER2_COUNTER            0xFFC014A4         /* TIMER2 Per Timer Counter Register */
    513. 

  513. #define TIMER2_PERIOD             0xFFC014A8         /* TIMER2 Per Timer Period Register */
    514. 

  514. #define TIMER2_WIDTH              0xFFC014AC         /* TIMER2 Per Timer Width Register */
    515. 

  515. #define TIMER2_DELAY              0xFFC014B0         /* TIMER2 Per Timer Delay Register */
    516. 

  516. 

  517. #define TIMER3_CONFIG             0xFFC014C0         /* TIMER3 Per Timer Config Register */
    518. 

  518. #define TIMER3_COUNTER            0xFFC014C4         /* TIMER3 Per Timer Counter Register */
    519. 

  519. #define TIMER3_PERIOD             0xFFC014C8         /* TIMER3 Per Timer Period Register */
    520. 

  520. #define TIMER3_WIDTH              0xFFC014CC         /* TIMER3 Per Timer Width Register */
    521. 

  521. #define TIMER3_DELAY              0xFFC014D0         /* TIMER3 Per Timer Delay Register */
    522. 

  522. 

  523. #define TIMER4_CONFIG             0xFFC014E0         /* TIMER4 Per Timer Config Register */
    524. 

  524. #define TIMER4_COUNTER            0xFFC014E4         /* TIMER4 Per Timer Counter Register */
    525. 

  525. #define TIMER4_PERIOD             0xFFC014E8         /* TIMER4 Per Timer Period Register */
    526. 

  526. #define TIMER4_WIDTH              0xFFC014EC         /* TIMER4 Per Timer Width Register */
    527. 

  527. #define TIMER4_DELAY              0xFFC014F0         /* TIMER4 Per Timer Delay Register */
    528. 

  528. 

  529. #define TIMER5_CONFIG             0xFFC01500         /* TIMER5 Per Timer Config Register */
    530. 

  530. #define TIMER5_COUNTER            0xFFC01504         /* TIMER5 Per Timer Counter Register */
    531. 

  531. #define TIMER5_PERIOD             0xFFC01508         /* TIMER5 Per Timer Period Register */
    532. 

  532. #define TIMER5_WIDTH              0xFFC0150C         /* TIMER5 Per Timer Width Register */
    533. 

  533. #define TIMER5_DELAY              0xFFC01510         /* TIMER5 Per Timer Delay Register */
    534. 

  534. 

  535. #define TIMER6_CONFIG             0xFFC01520         /* TIMER6 Per Timer Config Register */
    536. 

  536. #define TIMER6_COUNTER            0xFFC01524         /* TIMER6 Per Timer Counter Register */
    537. 

  537. #define TIMER6_PERIOD             0xFFC01528         /* TIMER6 Per Timer Period Register */
    538. 

  538. #define TIMER6_WIDTH              0xFFC0152C         /* TIMER6 Per Timer Width Register */
    539. 

  539. #define TIMER6_DELAY              0xFFC01530         /* TIMER6 Per Timer Delay Register */
    540. 

  540. 

  541. #define TIMER7_CONFIG             0xFFC01540         /* TIMER7 Per Timer Config Register */
    542. 

  542. #define TIMER7_COUNTER            0xFFC01544         /* TIMER7 Per Timer Counter Register */
    543. 

  543. #define TIMER7_PERIOD             0xFFC01548         /* TIMER7 Per Timer Period Register */
    544. 

  544. #define TIMER7_WIDTH              0xFFC0154C         /* TIMER7 Per Timer Width Register */
    545. 

  545. #define TIMER7_DELAY              0xFFC01550         /* TIMER7 Per Timer Delay Register */
    546. 

  546. 

  547. /* =========================
    548. 

  548. 	CRC Registers
    549. 

  549.    ========================= */
    550. 

  550. 

  551. /* =========================
    552. 

  552. 	CRC0
    553. 

  553.    ========================= */
    554. 

  554. #define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
    555. 

  555. #define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
    556. 

  556. #define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
    557. 

  557. #define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 DATA Compare Register */
    558. 

  558. #define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
    559. 

  559. #define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 DATA FIFO Register */
    560. 

  560. #define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
    561. 

  561. #define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
    562. 

  562. #define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
    563. 

  563. #define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
    564. 

  564. #define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
    565. 

  565. #define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 DATA Count Capture Register */
    566. 

  566. #define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 Final CRC Result Register */
    567. 

  567. #define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 Current CRC Result Register */
    568. 

  568. #define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
    569. 

  569. 

  570. /* =========================
    571. 

  571. 	CRC1
    572. 

  572.    ========================= */
    573. 

  573. #define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
    574. 

  574. #define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
    575. 

  575. #define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
    576. 

  576. #define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 DATA Compare Register */
    577. 

  577. #define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
    578. 

  578. #define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 DATA FIFO Register */
    579. 

  579. #define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
    580. 

  580. #define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
    581. 

  581. #define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
    582. 

  582. #define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
    583. 

  583. #define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
    584. 

  584. #define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 DATA Count Capture Register */
    585. 

  585. #define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 Final CRC Result Register */
    586. 

  586. #define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 Current CRC Result Register */
    587. 

  587. #define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
    588. 

  588. 

  589. /* =========================
    590. 

  590.         TWI Registers
    591. 

  591.    ========================= */
    592. 

  592. 

  593. /* =========================
    594. 

  594.         TWI0
    595. 

  595.    ========================= */
    596. 

  596. #define TWI0_CLKDIV                    0xFFC01E00         /* TWI0 SCL Clock Divider */
    597. 

  597. #define TWI0_CONTROL                   0xFFC01E04         /* TWI0 Control Register */
    598. 

  598. #define TWI0_SLAVE_CTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
    599. 

  599. #define TWI0_SLAVE_STAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
    600. 

  600. #define TWI0_SLAVE_ADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
    601. 

  601. #define TWI0_MASTER_CTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
    602. 

  602. #define TWI0_MASTER_STAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
    603. 

  603. #define TWI0_MASTER_ADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
    604. 

  604. #define TWI0_INT_STAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
    605. 

  605. #define TWI0_INT_MASK                  0xFFC01E24         /* TWI0 Interrupt Mask Register */
    606. 

  606. #define TWI0_FIFO_CTL                  0xFFC01E28         /* TWI0 FIFO Control Register */
    607. 

  607. #define TWI0_FIFO_STAT                 0xFFC01E2C         /* TWI0 FIFO Status Register */
    608. 

  608. #define TWI0_XMT_DATA8                 0xFFC01E80         /* TWI0 FIFO Transmit Data Single-Byte Register */
    609. 

  609. #define TWI0_XMT_DATA16                0xFFC01E84         /* TWI0 FIFO Transmit Data Double-Byte Register */
    610. 

  610. #define TWI0_RCV_DATA8                 0xFFC01E88         /* TWI0 FIFO Transmit Data Single-Byte Register */
    611. 

  611. #define TWI0_RCV_DATA16                0xFFC01E8C         /* TWI0 FIFO Transmit Data Double-Byte Register */
    612. 

  612. 

  613. /* =========================
    614. 

  614.         TWI1
    615. 

  615.    ========================= */
    616. 

  616. #define TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider */
    617. 

  617. #define TWI1_CONTROL                    0xFFC01F04         /* TWI1 Control Register */
    618. 

  618. #define TWI1_SLAVE_CTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
    619. 

  619. #define TWI1_SLAVE_STAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
    620. 

  620. #define TWI1_SLAVE_ADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
    621. 

  621. #define TWI1_MASTER_CTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
    622. 

  622. #define TWI1_MASTER_STAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
    623. 

  623. #define TWI1_MASTER_ADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
    624. 

  624. #define TWI1_INT_STAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
    625. 

  625. #define TWI1_INT_MASK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
    626. 

  626. #define TWI1_FIFO_CTL                0xFFC01F28         /* TWI1 FIFO Control Register */
    627. 

  627. #define TWI1_FIFO_STAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
    628. 

  628. #define TWI1_XMT_DATA8                0xFFC01F80         /* TWI1 FIFO Transmit Data Single-Byte Register */
    629. 

  629. #define TWI1_XMT_DATA16               0xFFC01F84         /* TWI1 FIFO Transmit Data Double-Byte Register */
    630. 

  630. #define TWI1_RCV_DATA8                0xFFC01F88         /* TWI1 FIFO Transmit Data Single-Byte Register */
    631. 

  631. #define TWI1_RCV_DATA16               0xFFC01F8C         /* TWI1 FIFO Transmit Data Double-Byte Register */
    632. 

  632. 

  633. 

  634. /* =========================
    635. 

  635.         UART Registers
    636. 

  636.    ========================= */
    637. 

  637. 

  638. /* =========================
    639. 

  639.         UART0
    640. 

  640.    ========================= */
    641. 

  641. #define UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
    642. 

  642. #define UART0_CTL                   0xFFC02004         /* UART0 Control Register */
    643. 

  643. #define UART0_STAT                  0xFFC02008         /* UART0 Status Register */
    644. 

  644. #define UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
    645. 

  645. #define UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
    646. 

  646. #define UART0_IER                   0xFFC02014         /* UART0 Interrupt Mask Register */
    647. 

  647. #define UART0_IER_SET               0xFFC02018         /* UART0 Interrupt Mask Set Register */
    648. 

  648. #define UART0_IER_CLR               0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
    649. 

  649. #define UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
    650. 

  650. #define UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
    651. 

  651. #define UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
    652. 

  652. #define UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
    653. 

  653. #define UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
    654. 

  654. #define UART0_TXDIV                 0xFFC02034         /* UART0 Transmit Clock Devider Register */
    655. 

  655. #define UART0_RXDIV                 0xFFC02038         /* UART0 Receive Clock Devider Register */
    656. 

  656. 

  657. /* =========================
    658. 

  658.         UART1
    659. 

  659.    ========================= */
    660. 

  660. #define UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
    661. 

  661. #define UART1_CTL                   0xFFC02404         /* UART1 Control Register */
    662. 

  662. #define UART1_STAT                  0xFFC02408         /* UART1 Status Register */
    663. 

  663. #define UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
    664. 

  664. #define UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
    665. 

  665. #define UART1_IER                   0xFFC02414         /* UART1 Interrupt Mask Register */
    666. 

  666. #define UART1_IER_SET               0xFFC02418         /* UART1 Interrupt Mask Set Register */
    667. 

  667. #define UART1_IER_CLR               0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
    668. 

  668. #define UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
    669. 

  669. #define UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
    670. 

  670. #define UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
    671. 

  671. #define UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
    672. 

  672. #define UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
    673. 

  673. #define UART1_TXDIV                 0xFFC02434         /* UART1 Transmit Clock Devider Register */
    674. 

  674. #define UART1_RXDIV                 0xFFC02438         /* UART1 Receive Clock Devider Register */
    675. 

  675. 

  676. 

  677. /* =========================
    678. 

  678.         PORT Registers
    679. 

  679.    ========================= */
    680. 

  680. 

  681. /* =========================
    682. 

  682.         PORTA
    683. 

  683.    ========================= */
    684. 

  684. #define PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
    685. 

  685. #define PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
    686. 

  686. #define PORTA_FER_CLEAR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
    687. 

  687. #define PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
    688. 

  688. #define PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
    689. 

  689. #define PORTA_DATA_CLEAR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
    690. 

  690. #define PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
    691. 

  691. #define PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
    692. 

  692. #define PORTA_DIR_CLEAR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
    693. 

  693. #define PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
    694. 

  694. #define PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
    695. 

  695. #define PORTA_INEN_CLEAR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
    696. 

  696. #define PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
    697. 

  697. #define PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
    698. 

  698. #define PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Programming Inversion Register */
    699. 

  699. #define PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Programming Inversion Set Register */
    700. 

  700. #define PORTA_POL_CLEAR               0xFFC03040         /* PORTA Port x GPIO Programming Inversion Clear Register */
    701. 

  701. #define PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
    702. 

  702. #define PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
    703. 

  703. 

  704. /* =========================
    705. 

  705.         PORTB
    706. 

  706.    ========================= */
    707. 

  707. #define PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
    708. 

  708. #define PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
    709. 

  709. #define PORTB_FER_CLEAR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
    710. 

  710. #define PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
    711. 

  711. #define PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
    712. 

  712. #define PORTB_DATA_CLEAR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
    713. 

  713. #define PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
    714. 

  714. #define PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
    715. 

  715. #define PORTB_DIR_CLEAR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
    716. 

  716. #define PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
    717. 

  717. #define PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
    718. 

  718. #define PORTB_INEN_CLEAR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
    719. 

  719. #define PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
    720. 

  720. #define PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
    721. 

  721. #define PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Programming Inversion Register */
    722. 

  722. #define PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Programming Inversion Set Register */
    723. 

  723. #define PORTB_POL_CLEAR               0xFFC030C0         /* PORTB Port x GPIO Programming Inversion Clear Register */
    724. 

  724. #define PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
    725. 

  725. #define PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
    726. 

  726. 

  727. /* =========================
    728. 

  728.         PORTC
    729. 

  729.    ========================= */
    730. 

  730. #define PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
    731. 

  731. #define PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
    732. 

  732. #define PORTC_FER_CLEAR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
    733. 

  733. #define PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
    734. 

  734. #define PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
    735. 

  735. #define PORTC_DATA_CLEAR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
    736. 

  736. #define PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
    737. 

  737. #define PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
    738. 

  738. #define PORTC_DIR_CLEAR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
    739. 

  739. #define PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
    740. 

  740. #define PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
    741. 

  741. #define PORTC_INEN_CLEAR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
    742. 

  742. #define PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
    743. 

  743. #define PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
    744. 

  744. #define PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Programming Inversion Register */
    745. 

  745. #define PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Programming Inversion Set Register */
    746. 

  746. #define PORTC_POL_CLEAR               0xFFC03140         /* PORTC Port x GPIO Programming Inversion Clear Register */
    747. 

  747. #define PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
    748. 

  748. #define PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
    749. 

  749. 

  750. /* =========================
    751. 

  751.         PORTD
    752. 

  752.    ========================= */
    753. 

  753. #define PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
    754. 

  754. #define PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
    755. 

  755. #define PORTD_FER_CLEAR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
    756. 

  756. #define PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
    757. 

  757. #define PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
    758. 

  758. #define PORTD_DATA_CLEAR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
    759. 

  759. #define PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
    760. 

  760. #define PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
    761. 

  761. #define PORTD_DIR_CLEAR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
    762. 

  762. #define PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
    763. 

  763. #define PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
    764. 

  764. #define PORTD_INEN_CLEAR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
    765. 

  765. #define PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
    766. 

  766. #define PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
    767. 

  767. #define PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Programming Inversion Register */
    768. 

  768. #define PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Programming Inversion Set Register */
    769. 

  769. #define PORTD_POL_CLEAR               0xFFC031C0         /* PORTD Port x GPIO Programming Inversion Clear Register */
    770. 

  770. #define PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
    771. 

  771. #define PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
    772. 

  772. 

  773. /* =========================
    774. 

  774.         PORTE
    775. 

  775.    ========================= */
    776. 

  776. #define PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
    777. 

  777. #define PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
    778. 

  778. #define PORTE_FER_CLEAR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
    779. 

  779. #define PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
    780. 

  780. #define PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
    781. 

  781. #define PORTE_DATA_CLEAR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
    782. 

  782. #define PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
    783. 

  783. #define PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
    784. 

  784. #define PORTE_DIR_CLEAR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
    785. 

  785. #define PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
    786. 

  786. #define PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
    787. 

  787. #define PORTE_INEN_CLEAR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
    788. 

  788. #define PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
    789. 

  789. #define PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
    790. 

  790. #define PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Programming Inversion Register */
    791. 

  791. #define PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Programming Inversion Set Register */
    792. 

  792. #define PORTE_POL_CLEAR               0xFFC03240         /* PORTE Port x GPIO Programming Inversion Clear Register */
    793. 

  793. #define PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
    794. 

  794. #define PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
    795. 

  795. 

  796. /* =========================
    797. 

  797.         PORTF
    798. 

  798.    ========================= */
    799. 

  799. #define PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
    800. 

  800. #define PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
    801. 

  801. #define PORTF_FER_CLEAR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
    802. 

  802. #define PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
    803. 

  803. #define PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
    804. 

  804. #define PORTF_DATA_CLEAR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
    805. 

  805. #define PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
    806. 

  806. #define PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
    807. 

  807. #define PORTF_DIR_CLEAR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
    808. 

  808. #define PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
    809. 

  809. #define PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
    810. 

  810. #define PORTF_INEN_CLEAR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
    811. 

  811. #define PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
    812. 

  812. #define PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
    813. 

  813. #define PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Programming Inversion Register */
    814. 

  814. #define PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Programming Inversion Set Register */
    815. 

  815. #define PORTF_POL_CLEAR               0xFFC032C0         /* PORTF Port x GPIO Programming Inversion Clear Register */
    816. 

  816. #define PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
    817. 

  817. #define PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
    818. 

  818. 

  819. /* =========================
    820. 

  820.         PORTG
    821. 

  821.    ========================= */
    822. 

  822. #define PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
    823. 

  823. #define PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
    824. 

  824. #define PORTG_FER_CLEAR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
    825. 

  825. #define PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
    826. 

  826. #define PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
    827. 

  827. #define PORTG_DATA_CLEAR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
    828. 

  828. #define PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
    829. 

  829. #define PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
    830. 

  830. #define PORTG_DIR_CLEAR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
    831. 

  831. #define PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
    832. 

  832. #define PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
    833. 

  833. #define PORTG_INEN_CLEAR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
    834. 

  834. #define PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
    835. 

  835. #define PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
    836. 

  836. #define PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Programming Inversion Register */
    837. 

  837. #define PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Programming Inversion Set Register */
    838. 

  838. #define PORTG_POL_CLEAR               0xFFC03340         /* PORTG Port x GPIO Programming Inversion Clear Register */
    839. 

  839. #define PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
    840. 

  840. #define PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
    841. 

  841. 

  842. 

  843. /* =========================
    844. 

  844.         PINT Registers
    845. 

  845.    ========================= */
    846. 

  846. 

  847. /* =========================
    848. 

  848.         PINT0
    849. 

  849.    ========================= */
    850. 

  850. #define PINT0_MASK_SET              0xFFC04000         /* PINT0 Pint Mask Set Register */
    851. 

  851. #define PINT0_MASK_CLEAR            0xFFC04004         /* PINT0 Pint Mask Clear Register */
    852. 

  852. #define PINT0_REQUEST               0xFFC04008         /* PINT0 Pint Request Register */
    853. 

  853. #define PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
    854. 

  854. #define PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
    855. 

  855. #define PINT0_EDGE_CLEAR            0xFFC04014         /* PINT0 Pint Edge Clear Register */
    856. 

  856. #define PINT0_INVERT_SET            0xFFC04018         /* PINT0 Pint Invert Set Register */
    857. 

  857. #define PINT0_INVERT_CLEAR          0xFFC0401C         /* PINT0 Pint Invert Clear Register */
    858. 

  858. #define PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
    859. 

  859. #define PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
    860. 

  860. 

  861. /* =========================
    862. 

  862.         PINT1
    863. 

  863.    ========================= */
    864. 

  864. #define PINT1_MASK_SET              0xFFC04100         /* PINT1 Pint Mask Set Register */
    865. 

  865. #define PINT1_MASK_CLEAR            0xFFC04104         /* PINT1 Pint Mask Clear Register */
    866. 

  866. #define PINT1_REQUEST               0xFFC04108         /* PINT1 Pint Request Register */
    867. 

  867. #define PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
    868. 

  868. #define PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
    869. 

  869. #define PINT1_EDGE_CLEAR            0xFFC04114         /* PINT1 Pint Edge Clear Register */
    870. 

  870. #define PINT1_INVERT_SET            0xFFC04118         /* PINT1 Pint Invert Set Register */
    871. 

  871. #define PINT1_INVERT_CLEAR          0xFFC0411C         /* PINT1 Pint Invert Clear Register */
    872. 

  872. #define PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
    873. 

  873. #define PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
    874. 

  874. 

  875. /* =========================
    876. 

  876.         PINT2
    877. 

  877.    ========================= */
    878. 

  878. #define PINT2_MASK_SET              0xFFC04200         /* PINT2 Pint Mask Set Register */
    879. 

  879. #define PINT2_MASK_CLEAR            0xFFC04204         /* PINT2 Pint Mask Clear Register */
    880. 

  880. #define PINT2_REQUEST               0xFFC04208         /* PINT2 Pint Request Register */
    881. 

  881. #define PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
    882. 

  882. #define PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
    883. 

  883. #define PINT2_EDGE_CLEAR            0xFFC04214         /* PINT2 Pint Edge Clear Register */
    884. 

  884. #define PINT2_INVERT_SET            0xFFC04218         /* PINT2 Pint Invert Set Register */
    885. 

  885. #define PINT2_INVERT_CLEAR          0xFFC0421C         /* PINT2 Pint Invert Clear Register */
    886. 

  886. #define PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
    887. 

  887. #define PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
    888. 

  888. 

  889. /* =========================
    890. 

  890.         PINT3
    891. 

  891.    ========================= */
    892. 

  892. #define PINT3_MASK_SET              0xFFC04300         /* PINT3 Pint Mask Set Register */
    893. 

  893. #define PINT3_MASK_CLEAR            0xFFC04304         /* PINT3 Pint Mask Clear Register */
    894. 

  894. #define PINT3_REQUEST               0xFFC04308         /* PINT3 Pint Request Register */
    895. 

  895. #define PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
    896. 

  896. #define PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
    897. 

  897. #define PINT3_EDGE_CLEAR            0xFFC04314         /* PINT3 Pint Edge Clear Register */
    898. 

  898. #define PINT3_INVERT_SET            0xFFC04318         /* PINT3 Pint Invert Set Register */
    899. 

  899. #define PINT3_INVERT_CLEAR          0xFFC0431C         /* PINT3 Pint Invert Clear Register */
    900. 

  900. #define PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
    901. 

  901. #define PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
    902. 

  902. 

  903. /* =========================
    904. 

  904.         PINT4
    905. 

  905.    ========================= */
    906. 

  906. #define PINT4_MASK_SET              0xFFC04400         /* PINT4 Pint Mask Set Register */
    907. 

  907. #define PINT4_MASK_CLEAR            0xFFC04404         /* PINT4 Pint Mask Clear Register */
    908. 

  908. #define PINT4_REQUEST               0xFFC04408         /* PINT4 Pint Request Register */
    909. 

  909. #define PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
    910. 

  910. #define PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
    911. 

  911. #define PINT4_EDGE_CLEAR            0xFFC04414         /* PINT4 Pint Edge Clear Register */
    912. 

  912. #define PINT4_INVERT_SET            0xFFC04418         /* PINT4 Pint Invert Set Register */
    913. 

  913. #define PINT4_INVERT_CLEAR          0xFFC0441C         /* PINT4 Pint Invert Clear Register */
    914. 

  914. #define PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
    915. 

  915. #define PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
    916. 

  916. 

  917. /* =========================
    918. 

  918.         PINT5
    919. 

  919.    ========================= */
    920. 

  920. #define PINT5_MASK_SET              0xFFC04500         /* PINT5 Pint Mask Set Register */
    921. 

  921. #define PINT5_MASK_CLEAR            0xFFC04504         /* PINT5 Pint Mask Clear Register */
    922. 

  922. #define PINT5_REQUEST               0xFFC04508         /* PINT5 Pint Request Register */
    923. 

  923. #define PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
    924. 

  924. #define PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
    925. 

  925. #define PINT5_EDGE_CLEAR            0xFFC04514         /* PINT5 Pint Edge Clear Register */
    926. 

  926. #define PINT5_INVERT_SET            0xFFC04518         /* PINT5 Pint Invert Set Register */
    927. 

  927. #define PINT5_INVERT_CLEAR          0xFFC0451C         /* PINT5 Pint Invert Clear Register */
    928. 

  928. #define PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
    929. 

  929. #define PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
    930. 

  930. 

  931. 

  932. /* =========================
    933. 

  933.         SMC Registers
    934. 

  934.    ========================= */
    935. 

  935. 

  936. /* =========================
    937. 

  937.         SMC0
    938. 

  938.    ========================= */
    939. 

  939. #define SMC_GCTL                   0xFFC16004         /* SMC0 SMC Control Register */
    940. 

  940. #define SMC_GSTAT                  0xFFC16008         /* SMC0 SMC Status Register */
    941. 

  941. #define SMC_B0CTL                  0xFFC1600C         /* SMC0 SMC Bank0 Control Register */
    942. 

  942. #define SMC_B0TIM                  0xFFC16010         /* SMC0 SMC Bank0 Timing Register */
    943. 

  943. #define SMC_B0ETIM                 0xFFC16014         /* SMC0 SMC Bank0 Extended Timing Register */
    944. 

  944. #define SMC_B1CTL                  0xFFC1601C         /* SMC0 SMC BANK1 Control Register */
    945. 

  945. #define SMC_B1TIM                  0xFFC16020         /* SMC0 SMC BANK1 Timing Register */
    946. 

  946. #define SMC_B1ETIM                 0xFFC16024         /* SMC0 SMC BANK1 Extended Timing Register */
    947. 

  947. #define SMC_B2CTL                  0xFFC1602C         /* SMC0 SMC BANK2 Control Register */
    948. 

  948. #define SMC_B2TIM                  0xFFC16030         /* SMC0 SMC BANK2 Timing Register */
    949. 

  949. #define SMC_B2ETIM                 0xFFC16034         /* SMC0 SMC BANK2 Extended Timing Register */
    950. 

  950. #define SMC_B3CTL                  0xFFC1603C         /* SMC0 SMC BANK3 Control Register */
    951. 

  951. #define SMC_B3TIM                  0xFFC16040         /* SMC0 SMC BANK3 Timing Register */
    952. 

  952. #define SMC_B3ETIM                 0xFFC16044         /* SMC0 SMC BANK3 Extended Timing Register */
    953. 

  953. 

  954. 

  955. /* =========================
    956. 

  956.         WDOG Registers
    957. 

  957.    ========================= */
    958. 

  958. 

  959. /* =========================
    960. 

  960.         WDOG0
    961. 

  961.    ========================= */
    962. 

  962. #define WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
    963. 

  963. #define WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
    964. 

  964. #define WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
    965. 

  965. #define WDOG_CTL		WDOG0_CTL
    966. 

  966. #define WDOG_CNT		WDOG0_CNT
    967. 

  967. #define WDOG_STAT		WDOG0_STAT
    968. 

  968. 

  969. /* =========================
    970. 

  970.         WDOG1
    971. 

  971.    ========================= */
    972. 

  972. #define WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
    973. 

  973. #define WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
    974. 

  974. #define WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
    975. 

  975. 

  976. 

  977. /* =========================
    978. 

  978.         SDU Registers
    979. 

  979.    ========================= */
    980. 

  980. 

  981. /* =========================
    982. 

  982.         SDU0
    983. 

  983.    ========================= */
    984. 

  984. #define SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
    985. 

  985. #define SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
    986. 

  986. #define SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
    987. 

  987. #define SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
    988. 

  988. #define SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
    989. 

  989. #define SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
    990. 

  990. #define SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
    991. 

  991. #define SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
    992. 

  992. #define SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
    993. 

  993. #define SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
    994. 

  994. #define SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
    995. 

  995. #define SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
    996. 

  996. 

  997. 

  998. /* =========================
    999. 

  999.         EMAC Registers
    1000. 

  1000.    ========================= */
    1001. 

  1001. /* =========================
    1002. 

  1002.         EMAC0
    1003. 

  1003.    ========================= */
    1004. 

  1004. #define EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
    1005. 

  1005. #define EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 Filter Register for filtering Received Frames */
    1006. 

  1006. #define EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Contains the Upper 32 bits of the hash table */
    1007. 

  1007. #define EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Contains the lower 32 bits of the hash table */
    1008. 

  1008. #define EMAC0_GMII_ADDR             0xFFC20010         /* EMAC0 Management Address Register */
    1009. 

  1009. #define EMAC0_GMII_DATA             0xFFC20014         /* EMAC0 Management Data Register */
    1010. 

  1010. #define EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 MAC FLow Control Register */
    1011. 

  1011. #define EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
    1012. 

  1012. #define EMAC0_VER                   0xFFC20020         /* EMAC0 EMAC Version Register */
    1013. 

  1013. #define EMAC0_DBG                   0xFFC20024         /* EMAC0 EMAC Debug Register */
    1014. 

  1014. #define EMAC0_RMTWKUP               0xFFC20028         /* EMAC0 Remote wake up frame register */
    1015. 

  1015. #define EMAC0_PMT_CTLSTAT           0xFFC2002C         /* EMAC0 PMT Control and Status Register */
    1016. 

  1016. #define EMAC0_ISTAT                 0xFFC20038         /* EMAC0 EMAC Interrupt Status Register */
    1017. 

  1017. #define EMAC0_IMSK                  0xFFC2003C         /* EMAC0 EMAC Interrupt Mask Register */
    1018. 

  1018. #define EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 EMAC Address0 High Register */
    1019. 

  1019. #define EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 EMAC Address0 Low Register */
    1020. 

  1020. #define EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
    1021. 

  1021. #define EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC RX Interrupt Register */
    1022. 

  1022. #define EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC TX Interrupt Register */
    1023. 

  1023. #define EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC RX Interrupt Mask Register */
    1024. 

  1024. #define EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
    1025. 

  1025. #define EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Num bytes transmitted exclusive of preamble */
    1026. 

  1026. #define EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Num frames transmitted exclusive of retired */
    1027. 

  1027. #define EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Number of good broadcast frames transmitted. */
    1028. 

  1028. #define EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Number of good multicast frames transmitted. */
    1029. 

  1029. #define EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Number of 64 byte length frames */
    1030. 

  1030. #define EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
    1031. 

  1031. #define EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
    1032. 

  1032. #define EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
    1033. 

  1033. #define EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
    1034. 

  1034. #define EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
    1035. 

  1035. #define EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Number of good and bad unicast frames transmitted */
    1036. 

  1036. #define EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Number of good and bad multicast frames transmitted */
    1037. 

  1037. #define EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Number of good and bad broadcast frames transmitted */
    1038. 

  1038. #define EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Number of frames aborted due to frame underflow error */
    1039. 

  1039. #define EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Number of transmitted frames after single collision */
    1040. 

  1040. #define EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Number of transmitted frames with more than one collision */
    1041. 

  1041. #define EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Number of transmitted frames after deferral */
    1042. 

  1042. #define EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Number of frames aborted due to late collision error */
    1043. 

  1043. #define EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Number of aborted frames due to excessive collisions */
    1044. 

  1044. #define EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Number of aborted frames due to carrier sense error */
    1045. 

  1045. #define EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Number of bytes transmitted in good frames only */
    1046. 

  1046. #define EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Number of good frames transmitted. */
    1047. 

  1047. #define EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Number of frames aborted due to excessive deferral */
    1048. 

  1048. #define EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Number of good PAUSE frames transmitted. */
    1049. 

  1049. #define EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Number of VLAN frames transmitted */
    1050. 

  1050. #define EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Number of good and bad frames received. */
    1051. 

  1051. #define EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Number of bytes received in good and bad frames */
    1052. 

  1052. #define EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Number of bytes received only in good frames */
    1053. 

  1053. #define EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Number of good broadcast frames received. */
    1054. 

  1054. #define EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Number of good multicast frames received */
    1055. 

  1055. #define EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Number of frames received with CRC error */
    1056. 

  1056. #define EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Number of frames with alignment error */
    1057. 

  1057. #define EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Number of frames received with runt error. */
    1058. 

  1058. #define EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Number of frames received with length greater than 1518 */
    1059. 

  1059. #define EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Number of frames received with length 64 */
    1060. 

  1060. #define EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Number of frames received with length greater than maxium */
    1061. 

  1061. #define EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Number of good and bad frames of lengh 64 bytes */
    1062. 

  1062. #define EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
    1063. 

  1063. #define EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
    1064. 

  1064. #define EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
    1065. 

  1065. #define EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Number of good and bad frames received between 512-1023 */
    1066. 

  1066. #define EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Number of frames received between 1024 and maxsize */
    1067. 

  1067. #define EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Number of good unicast frames received. */
    1068. 

  1068. #define EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Number of frames received with length error */
    1069. 

  1069. #define EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Number of frames with length not equal to valid frame size */
    1070. 

  1070. #define EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Number of good and valid PAUSE frames received. */
    1071. 

  1071. #define EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
    1072. 

  1072. #define EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Number of good and bad VLAN frames received. */
    1073. 

  1073. #define EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Frames received with error due to watchdog timeout */
    1074. 

  1074. #define EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC RX Interrupt Mask Register */
    1075. 

  1075. #define EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC RX Interrupt Register */
    1076. 

  1076. #define EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Number of good IPv4 datagrams */
    1077. 

  1077. #define EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Number of IPv4 datagrams with header errors */
    1078. 

  1078. #define EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Number of IPv4 datagrams without checksum */
    1079. 

  1079. #define EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Number of good IPv4 datagrams with fragmentation */
    1080. 

  1080. #define EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
    1081. 

  1081. #define EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
    1082. 

  1082. #define EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Number of IPv6 datagrams with header errors */
    1083. 

  1083. #define EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
    1084. 

  1084. #define EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Number of good IP datagrames with good UDP payload */
    1085. 

  1085. #define EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Number of good IP datagrams with UDP checksum errors */
    1086. 

  1086. #define EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Number of good IP datagrams with a good TCP payload */
    1087. 

  1087. #define EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Number of good IP datagrams with TCP checksum errors */
    1088. 

  1088. #define EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Number of good IP datagrams with a good ICMP payload */
    1089. 

  1089. #define EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
    1090. 

  1090. #define EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
    1091. 

  1091. #define EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Bytes received in IPv4 datagrams with header errors */
    1092. 

  1092. #define EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
    1093. 

  1093. #define EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Bytes received in fragmented IPv4 datagrams */
    1094. 

  1094. #define EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Bytes received in UDP segment with checksum disabled */
    1095. 

  1095. #define EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Bytes received in good IPv6  including tcp,udp or icmp load */
    1096. 

  1096. #define EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Number of bytes received in IPv6 with header errors */
    1097. 

  1097. #define EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
    1098. 

  1098. #define EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Number of bytes received in good UDP segments */
    1099. 

  1099. #define EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Number of bytes received in UDP segment with checksum err */
    1100. 

  1100. #define EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Number of bytes received in a good TCP segment */
    1101. 

  1101. #define EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Number of bytes received in TCP segment with checksum err */
    1102. 

  1102. #define EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Number of bytes received in a good ICMP segment */
    1103. 

  1103. #define EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Bytes received in an ICMP segment with checksum errors */
    1104. 

  1104. #define EMAC0_TM_CTL                0xFFC20700         /* EMAC0 EMAC Time Stamp Control Register */
    1105. 

  1105. #define EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 EMAC Time Stamp Sub Second Increment */
    1106. 

  1106. #define EMAC0_TM_SEC                0xFFC20708         /* EMAC0 EMAC Time Stamp Second Register */
    1107. 

  1107. #define EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 EMAC Time Stamp Nano Second Register */
    1108. 

  1108. #define EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 EMAC Time Stamp Seconds Update */
    1109. 

  1109. #define EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 EMAC Time Stamp Nano Seconds Update */
    1110. 

  1110. #define EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 EMAC Time Stamp Addend Register */
    1111. 

  1111. #define EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 EMAC Time Stamp Target Time Sec. */
    1112. 

  1112. #define EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
    1113. 

  1113. #define EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 EMAC Time Stamp High Second Register */
    1114. 

  1114. #define EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 EMAC Time Stamp Status Register */
    1115. 

  1115. #define EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 EMAC PPS Control Register */
    1116. 

  1116. #define EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
    1117. 

  1117. #define EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
    1118. 

  1118. #define EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 Bus Operating Modes for EMAC DMA */
    1119. 

  1119. #define EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 TX DMA Poll demand register */
    1120. 

  1120. #define EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 RX DMA Poll demand register */
    1121. 

  1121. #define EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 RX Descriptor List Address */
    1122. 

  1122. #define EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 TX Descriptor List Address */
    1123. 

  1123. #define EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
    1124. 

  1124. #define EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
    1125. 

  1125. #define EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
    1126. 

  1126. #define EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA missed frame and buffer overflow counter */
    1127. 

  1127. #define EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA RX Interrupt Watch Dog timer */
    1128. 

  1128. #define EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 AXI Bus Mode Register */
    1129. 

  1129. #define EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 AXI Status Register */
    1130. 

  1130. #define EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 TX current descriptor register */
    1131. 

  1131. #define EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 RX current descriptor register */
    1132. 

  1132. #define EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 TX current buffer pointer register */
    1133. 

  1133. #define EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 RX current buffer pointer register */
    1134. 

  1134. #define EMAC0_HWFEAT                0xFFC21058         /* EMAC0 Hardware Feature Register */
    1135. 

  1135. 

  1136. /* =========================
    1137. 

  1137.         EMAC1
    1138. 

  1138.    ========================= */
    1139. 

  1139. #define EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
    1140. 

  1140. #define EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 Filter Register for filtering Received Frames */
    1141. 

  1141. #define EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Contains the Upper 32 bits of the hash table */
    1142. 

  1142. #define EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Contains the lower 32 bits of the hash table */
    1143. 

  1143. #define EMAC1_GMII_ADDR             0xFFC22010         /* EMAC1 Management Address Register */
    1144. 

  1144. #define EMAC1_GMII_DATA             0xFFC22014         /* EMAC1 Management Data Register */
    1145. 

  1145. #define EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 MAC FLow Control Register */
    1146. 

  1146. #define EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
    1147. 

  1147. #define EMAC1_VER                   0xFFC22020         /* EMAC1 EMAC Version Register */
    1148. 

  1148. #define EMAC1_DBG                   0xFFC22024         /* EMAC1 EMAC Debug Register */
    1149. 

  1149. #define EMAC1_RMTWKUP               0xFFC22028         /* EMAC1 Remote wake up frame register */
    1150. 

  1150. #define EMAC1_PMT_CTLSTAT           0xFFC2202C         /* EMAC1 PMT Control and Status Register */
    1151. 

  1151. #define EMAC1_ISTAT                 0xFFC22038         /* EMAC1 EMAC Interrupt Status Register */
    1152. 

  1152. #define EMAC1_IMSK                  0xFFC2203C         /* EMAC1 EMAC Interrupt Mask Register */
    1153. 

  1153. #define EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 EMAC Address0 High Register */
    1154. 

  1154. #define EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 EMAC Address0 Low Register */
    1155. 

  1155. #define EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
    1156. 

  1156. #define EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC RX Interrupt Register */
    1157. 

  1157. #define EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC TX Interrupt Register */
    1158. 

  1158. #define EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC RX Interrupt Mask Register */
    1159. 

  1159. #define EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
    1160. 

  1160. #define EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Num bytes transmitted exclusive of preamble */
    1161. 

  1161. #define EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Num frames transmitted exclusive of retired */
    1162. 

  1162. #define EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Number of good broadcast frames transmitted. */
    1163. 

  1163. #define EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Number of good multicast frames transmitted. */
    1164. 

  1164. #define EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Number of 64 byte length frames */
    1165. 

  1165. #define EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
    1166. 

  1166. #define EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
    1167. 

  1167. #define EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
    1168. 

  1168. #define EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
    1169. 

  1169. #define EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
    1170. 

  1170. #define EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Number of good and bad unicast frames transmitted */
    1171. 

  1171. #define EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Number of good and bad multicast frames transmitted */
    1172. 

  1172. #define EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Number of good and bad broadcast frames transmitted */
    1173. 

  1173. #define EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Number of frames aborted due to frame underflow error */
    1174. 

  1174. #define EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Number of transmitted frames after single collision */
    1175. 

  1175. #define EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Number of transmitted frames with more than one collision */
    1176. 

  1176. #define EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Number of transmitted frames after deferral */
    1177. 

  1177. #define EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Number of frames aborted due to late collision error */
    1178. 

  1178. #define EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Number of aborted frames due to excessive collisions */
    1179. 

  1179. #define EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Number of aborted frames due to carrier sense error */
    1180. 

  1180. #define EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Number of bytes transmitted in good frames only */
    1181. 

  1181. #define EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Number of good frames transmitted. */
    1182. 

  1182. #define EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Number of frames aborted due to excessive deferral */
    1183. 

  1183. #define EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Number of good PAUSE frames transmitted. */
    1184. 

  1184. #define EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Number of VLAN frames transmitted */
    1185. 

  1185. #define EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Number of good and bad frames received. */
    1186. 

  1186. #define EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Number of bytes received in good and bad frames */
    1187. 

  1187. #define EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Number of bytes received only in good frames */
    1188. 

  1188. #define EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Number of good broadcast frames received. */
    1189. 

  1189. #define EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Number of good multicast frames received */
    1190. 

  1190. #define EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Number of frames received with CRC error */
    1191. 

  1191. #define EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Number of frames with alignment error */
    1192. 

  1192. #define EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Number of frames received with runt error. */
    1193. 

  1193. #define EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Number of frames received with length greater than 1518 */
    1194. 

  1194. #define EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Number of frames received with length 64 */
    1195. 

  1195. #define EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Number of frames received with length greater than maxium */
    1196. 

  1196. #define EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Number of good and bad frames of lengh 64 bytes */
    1197. 

  1197. #define EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
    1198. 

  1198. #define EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
    1199. 

  1199. #define EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
    1200. 

  1200. #define EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Number of good and bad frames received between 512-1023 */
    1201. 

  1201. #define EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Number of frames received between 1024 and maxsize */
    1202. 

  1202. #define EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Number of good unicast frames received. */
    1203. 

  1203. #define EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Number of frames received with length error */
    1204. 

  1204. #define EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Number of frames with length not equal to valid frame size */
    1205. 

  1205. #define EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Number of good and valid PAUSE frames received. */
    1206. 

  1206. #define EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
    1207. 

  1207. #define EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Number of good and bad VLAN frames received. */
    1208. 

  1208. #define EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Frames received with error due to watchdog timeout */
    1209. 

  1209. #define EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC RX Interrupt Mask Register */
    1210. 

  1210. #define EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC RX Interrupt Register */
    1211. 

  1211. #define EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Number of good IPv4 datagrams */
    1212. 

  1212. #define EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Number of IPv4 datagrams with header errors */
    1213. 

  1213. #define EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Number of IPv4 datagrams without checksum */
    1214. 

  1214. #define EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Number of good IPv4 datagrams with fragmentation */
    1215. 

  1215. #define EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
    1216. 

  1216. #define EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
    1217. 

  1217. #define EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Number of IPv6 datagrams with header errors */
    1218. 

  1218. #define EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
    1219. 

  1219. #define EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Number of good IP datagrames with good UDP payload */
    1220. 

  1220. #define EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Number of good IP datagrams with UDP checksum errors */
    1221. 

  1221. #define EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Number of good IP datagrams with a good TCP payload */
    1222. 

  1222. #define EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Number of good IP datagrams with TCP checksum errors */
    1223. 

  1223. #define EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Number of good IP datagrams with a good ICMP payload */
    1224. 

  1224. #define EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
    1225. 

  1225. #define EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
    1226. 

  1226. #define EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Bytes received in IPv4 datagrams with header errors */
    1227. 

  1227. #define EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
    1228. 

  1228. #define EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Bytes received in fragmented IPv4 datagrams */
    1229. 

  1229. #define EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Bytes received in UDP segment with checksum disabled */
    1230. 

  1230. #define EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Bytes received in good IPv6  including tcp,udp or icmp load */
    1231. 

  1231. #define EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Number of bytes received in IPv6 with header errors */
    1232. 

  1232. #define EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
    1233. 

  1233. #define EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Number of bytes received in good UDP segments */
    1234. 

  1234. #define EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Number of bytes received in UDP segment with checksum err */
    1235. 

  1235. #define EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Number of bytes received in a good TCP segment */
    1236. 

  1236. #define EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Number of bytes received in TCP segment with checksum err */
    1237. 

  1237. #define EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Number of bytes received in a good ICMP segment */
    1238. 

  1238. #define EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Bytes received in an ICMP segment with checksum errors */
    1239.