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aiot
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waterDataFluctuationCorrelation
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monitoringDataProcessing
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connectionSignalSlot.h

connectionSignalSlot.h 9.7 KB
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  1. #ifndef _ASM_M32R_M32R_MP_FPGA_
    2. 

  2. #define _ASM_M32R_M32R_MP_FPGA_
    3. 

  3. 

  4. /*
    5. 

  5.  * Renesas M32R-MP-FPGA
    6. 

  6.  *
    7. 

  7.  * Copyright (c) 2002  Hitoshi Yamamoto
    8. 

  8.  * Copyright (c) 2003, 2004  Renesas Technology Corp.
    9. 

  9.  */
    10. 

  10. 

  11. /*
    12. 

  12.  * ========================================================
    13. 

  13.  * M32R-MP-FPGA Memory Map
    14. 

  14.  * ========================================================
    15. 

  15.  * 0x00000000 : Block#0 : 64[MB]
    16. 

  16.  *              0x03E00000 : SFR
    17. 

  17.  *                           0x03E00000 : reserved
    18. 

  18.  *                           0x03EF0000 : FPGA
    19. 

  19.  *                           0x03EF1000 : reserved
    20. 

  20.  *                           0x03EF4000 : CKM
    21. 

  21.  *                           0x03EF4000 : BSELC
    22. 

  22.  *                           0x03EF5000 : reserved
    23. 

  23.  *                           0x03EFC000 : MFT
    24. 

  24.  *                           0x03EFD000 : SIO
    25. 

  25.  *                           0x03EFE000 : reserved
    26. 

  26.  *                           0x03EFF000 : ICU
    27. 

  27.  *              0x03F00000 : Internal SRAM 64[KB]
    28. 

  28.  *              0x03F10000 : reserved
    29. 

  29.  * --------------------------------------------------------
    30. 

  30.  * 0x04000000 : Block#1 : 64[MB]
    31. 

  31.  *              0x04000000 : Debug board SRAM 4[MB]
    32. 

  32.  *              0x04400000 : reserved
    33. 

  33.  * --------------------------------------------------------
    34. 

  34.  * 0x08000000 : Block#2 : 64[MB]
    35. 

  35.  * --------------------------------------------------------
    36. 

  36.  * 0x0C000000 : Block#3 : 64[MB]
    37. 

  37.  * --------------------------------------------------------
    38. 

  38.  * 0x10000000 : Block#4 : 64[MB]
    39. 

  39.  * --------------------------------------------------------
    40. 

  40.  * 0x14000000 : Block#5 : 64[MB]
    41. 

  41.  * --------------------------------------------------------
    42. 

  42.  * 0x18000000 : Block#6 : 64[MB]
    43. 

  43.  * --------------------------------------------------------
    44. 

  44.  * 0x1C000000 : Block#7 : 64[MB]
    45. 

  45.  * --------------------------------------------------------
    46. 

  46.  * 0xFE000000 : TLB
    47. 

  47.  *              0xFE000000 : ITLB
    48. 

  48.  *              0xFE000080 : reserved
    49. 

  49.  *              0xFE000800 : DTLB
    50. 

  50.  *              0xFE000880 : reserved
    51. 

  51.  * --------------------------------------------------------
    52. 

  52.  * 0xFF000000 : System area
    53. 

  53.  *              0xFFFF0000 : MMU
    54. 

  54.  *              0xFFFF0030 : reserved
    55. 

  55.  *              0xFFFF8000 : Debug function
    56. 

  56.  *              0xFFFFA000 : reserved
    57. 

  57.  *              0xFFFFC000 : CPU control
    58. 

  58.  * 0xFFFFFFFF
    59. 

  59.  * ========================================================
    60. 

  60.  */
    61. 

  61. 

  62. /*======================================================================*
    63. 

  63.  * Special Function Register
    64. 

  64.  *======================================================================*/
    65. 

  65. #define M32R_SFR_OFFSET  (0x00E00000)  /* 0x03E00000-0x03EFFFFF 1[MB] */
    66. 

  66. 

  67. /*
    68. 

  68.  * FPGA registers.
    69. 

  69.  */
    70. 

  70. #define M32R_FPGA_TOP  (0x000F0000+M32R_SFR_OFFSET)
    71. 

  71. 

  72. #define M32R_FPGA_NUM_OF_CPUS_PORTL  (0x00+M32R_FPGA_TOP)
    73. 

  73. #define M32R_FPGA_CPU_NAME0_PORTL    (0x10+M32R_FPGA_TOP)
    74. 

  74. #define M32R_FPGA_CPU_NAME1_PORTL    (0x14+M32R_FPGA_TOP)
    75. 

  75. #define M32R_FPGA_CPU_NAME2_PORTL    (0x18+M32R_FPGA_TOP)
    76. 

  76. #define M32R_FPGA_CPU_NAME3_PORTL    (0x1C+M32R_FPGA_TOP)
    77. 

  77. #define M32R_FPGA_MODEL_ID0_PORTL    (0x20+M32R_FPGA_TOP)
    78. 

  78. #define M32R_FPGA_MODEL_ID1_PORTL    (0x24+M32R_FPGA_TOP)
    79. 

  79. #define M32R_FPGA_MODEL_ID2_PORTL    (0x28+M32R_FPGA_TOP)
    80. 

  80. #define M32R_FPGA_MODEL_ID3_PORTL    (0x2C+M32R_FPGA_TOP)
    81. 

  81. #define M32R_FPGA_VERSION0_PORTL     (0x30+M32R_FPGA_TOP)
    82. 

  82. #define M32R_FPGA_VERSION1_PORTL     (0x34+M32R_FPGA_TOP)
    83. 

  83. 

  84. /*
    85. 

  85.  * Clock and Power Manager registers.
    86. 

  86.  */
    87. 

  87. #define M32R_CPM_OFFSET  (0x000F4000+M32R_SFR_OFFSET)
    88. 

  88. 

  89. #define M32R_CPM_CPUCLKCR_PORTL  (0x00+M32R_CPM_OFFSET)
    90. 

  90. #define M32R_CPM_CLKMOD_PORTL    (0x04+M32R_CPM_OFFSET)
    91. 

  91. #define M32R_CPM_PLLCR_PORTL     (0x08+M32R_CPM_OFFSET)
    92. 

  92. 

  93. /*
    94. 

  94.  * Block SELect Controller registers.
    95. 

  95.  */
    96. 

  96. #define M32R_BSELC_OFFSET  (0x000F5000+M32R_SFR_OFFSET)
    97. 

  97. 

  98. #define M32R_BSEL0_CR0_PORTL  (0x000+M32R_BSELC_OFFSET)
    99. 

  99. #define M32R_BSEL0_CR1_PORTL  (0x004+M32R_BSELC_OFFSET)
    100. 

  100. #define M32R_BSEL1_CR0_PORTL  (0x100+M32R_BSELC_OFFSET)
    101. 

  101. #define M32R_BSEL1_CR1_PORTL  (0x104+M32R_BSELC_OFFSET)
    102. 

  102. #define M32R_BSEL2_CR0_PORTL  (0x200+M32R_BSELC_OFFSET)
    103. 

  103. #define M32R_BSEL2_CR1_PORTL  (0x204+M32R_BSELC_OFFSET)
    104. 

  104. #define M32R_BSEL3_CR0_PORTL  (0x300+M32R_BSELC_OFFSET)
    105. 

  105. #define M32R_BSEL3_CR1_PORTL  (0x304+M32R_BSELC_OFFSET)
    106. 

  106. #define M32R_BSEL4_CR0_PORTL  (0x400+M32R_BSELC_OFFSET)
    107. 

  107. #define M32R_BSEL4_CR1_PORTL  (0x404+M32R_BSELC_OFFSET)
    108. 

  108. #define M32R_BSEL5_CR0_PORTL  (0x500+M32R_BSELC_OFFSET)
    109. 

  109. #define M32R_BSEL5_CR1_PORTL  (0x504+M32R_BSELC_OFFSET)
    110. 

  110. #define M32R_BSEL6_CR0_PORTL  (0x600+M32R_BSELC_OFFSET)
    111. 

  111. #define M32R_BSEL6_CR1_PORTL  (0x604+M32R_BSELC_OFFSET)
    112. 

  112. #define M32R_BSEL7_CR0_PORTL  (0x700+M32R_BSELC_OFFSET)
    113. 

  113. #define M32R_BSEL7_CR1_PORTL  (0x704+M32R_BSELC_OFFSET)
    114. 

  114. 

  115. /*
    116. 

  116.  * Multi Function Timer registers.
    117. 

  117.  */
    118. 

  118. #define M32R_MFT_OFFSET        (0x000FC000+M32R_SFR_OFFSET)
    119. 

  119. 

  120. #define M32R_MFTCR_PORTL       (0x000+M32R_MFT_OFFSET)  /* MFT control */
    121. 

  121. #define M32R_MFTRPR_PORTL      (0x004+M32R_MFT_OFFSET)  /* MFT real port */
    122. 

  122. 

  123. #define M32R_MFT0_OFFSET       (0x100+M32R_MFT_OFFSET)
    124. 

  124. #define M32R_MFT0MOD_PORTL     (0x00+M32R_MFT0_OFFSET)  /* MFT0 mode */
    125. 

  125. #define M32R_MFT0BOS_PORTL     (0x04+M32R_MFT0_OFFSET)  /* MFT0 b-port output status */
    126. 

  126. #define M32R_MFT0CUT_PORTL     (0x08+M32R_MFT0_OFFSET)  /* MFT0 count */
    127. 

  127. #define M32R_MFT0RLD_PORTL     (0x0C+M32R_MFT0_OFFSET)  /* MFT0 reload */
    128. 

  128. #define M32R_MFT0CMPRLD_PORTL  (0x10+M32R_MFT0_OFFSET)  /* MFT0 compare reload */
    129. 

  129. 

  130. #define M32R_MFT1_OFFSET       (0x200+M32R_MFT_OFFSET)
    131. 

  131. #define M32R_MFT1MOD_PORTL     (0x00+M32R_MFT1_OFFSET)  /* MFT1 mode */
    132. 

  132. #define M32R_MFT1BOS_PORTL     (0x04+M32R_MFT1_OFFSET)  /* MFT1 b-port output status */
    133. 

  133. #define M32R_MFT1CUT_PORTL     (0x08+M32R_MFT1_OFFSET)  /* MFT1 count */
    134. 

  134. #define M32R_MFT1RLD_PORTL     (0x0C+M32R_MFT1_OFFSET)  /* MFT1 reload */
    135. 

  135. #define M32R_MFT1CMPRLD_PORTL  (0x10+M32R_MFT1_OFFSET)  /* MFT1 compare reload */
    136. 

  136. 

  137. #define M32R_MFT2_OFFSET       (0x300+M32R_MFT_OFFSET)
    138. 

  138. #define M32R_MFT2MOD_PORTL     (0x00+M32R_MFT2_OFFSET)  /* MFT2 mode */
    139. 

  139. #define M32R_MFT2BOS_PORTL     (0x04+M32R_MFT2_OFFSET)  /* MFT2 b-port output status */
    140. 

  140. #define M32R_MFT2CUT_PORTL     (0x08+M32R_MFT2_OFFSET)  /* MFT2 count */
    141. 

  141. #define M32R_MFT2RLD_PORTL     (0x0C+M32R_MFT2_OFFSET)  /* MFT2 reload */
    142. 

  142. #define M32R_MFT2CMPRLD_PORTL  (0x10+M32R_MFT2_OFFSET)  /* MFT2 compare reload */
    143. 

  143. 

  144. #define M32R_MFT3_OFFSET       (0x400+M32R_MFT_OFFSET)
    145. 

  145. #define M32R_MFT3MOD_PORTL     (0x00+M32R_MFT3_OFFSET)  /* MFT3 mode */
    146. 

  146. #define M32R_MFT3BOS_PORTL     (0x04+M32R_MFT3_OFFSET)  /* MFT3 b-port output status */
    147. 

  147. #define M32R_MFT3CUT_PORTL     (0x08+M32R_MFT3_OFFSET)  /* MFT3 count */
    148. 

  148. #define M32R_MFT3RLD_PORTL     (0x0C+M32R_MFT3_OFFSET)  /* MFT3 reload */
    149. 

  149. #define M32R_MFT3CMPRLD_PORTL  (0x10+M32R_MFT3_OFFSET)  /* MFT3 compare reload */
    150. 

  150. 

  151. #define M32R_MFT4_OFFSET       (0x500+M32R_MFT_OFFSET)
    152. 

  152. #define M32R_MFT4MOD_PORTL     (0x00+M32R_MFT4_OFFSET)  /* MFT4 mode */
    153. 

  153. #define M32R_MFT4BOS_PORTL     (0x04+M32R_MFT4_OFFSET)  /* MFT4 b-port output status */
    154. 

  154. #define M32R_MFT4CUT_PORTL     (0x08+M32R_MFT4_OFFSET)  /* MFT4 count */
    155. 

  155. #define M32R_MFT4RLD_PORTL     (0x0C+M32R_MFT4_OFFSET)  /* MFT4 reload */
    156. 

  156. #define M32R_MFT4CMPRLD_PORTL  (0x10+M32R_MFT4_OFFSET)  /* MFT4 compare reload */
    157. 

  157. 

  158. #define M32R_MFT5_OFFSET       (0x600+M32R_MFT_OFFSET)
    159. 

  159. #define M32R_MFT5MOD_PORTL     (0x00+M32R_MFT5_OFFSET)  /* MFT4 mode */
    160. 

  160. #define M32R_MFT5BOS_PORTL     (0x04+M32R_MFT5_OFFSET)  /* MFT4 b-port output status */
    161. 

  161. #define M32R_MFT5CUT_PORTL     (0x08+M32R_MFT5_OFFSET)  /* MFT4 count */
    162. 

  162. #define M32R_MFT5RLD_PORTL     (0x0C+M32R_MFT5_OFFSET)  /* MFT4 reload */
    163. 

  163. #define M32R_MFT5CMPRLD_PORTL  (0x10+M32R_MFT5_OFFSET)  /* MFT4 compare reload */
    164. 

  164. 

  165. #define M32R_MFTCR_MFT0MSK  (1UL<<15)  /* b16 */
    166. 

  166. #define M32R_MFTCR_MFT1MSK  (1UL<<14)  /* b17 */
    167. 

  167. #define M32R_MFTCR_MFT2MSK  (1UL<<13)  /* b18 */
    168. 

  168. #define M32R_MFTCR_MFT3MSK  (1UL<<12)  /* b19 */
    169. 

  169. #define M32R_MFTCR_MFT4MSK  (1UL<<11)  /* b20 */
    170. 

  170. #define M32R_MFTCR_MFT5MSK  (1UL<<10)  /* b21 */
    171. 

  171. #define M32R_MFTCR_MFT0EN   (1UL<<7)   /* b24 */
    172. 

  172. #define M32R_MFTCR_MFT1EN   (1UL<<6)   /* b25 */
    173. 

  173. #define M32R_MFTCR_MFT2EN   (1UL<<5)   /* b26 */
    174. 

  174. #define M32R_MFTCR_MFT3EN   (1UL<<4)   /* b27 */
    175. 

  175. #define M32R_MFTCR_MFT4EN   (1UL<<3)   /* b28 */
    176. 

  176. #define M32R_MFTCR_MFT5EN   (1UL<<2)   /* b29 */
    177. 

  177. 

  178. #define M32R_MFTMOD_CC_MASK    (1UL<<15)  /* b16 */
    179. 

  179. #define M32R_MFTMOD_TCCR       (1UL<<13)  /* b18 */
    180. 

  180. #define M32R_MFTMOD_GTSEL000   (0UL<<8)   /* b21-23 : 000 */
    181. 

  181. #define M32R_MFTMOD_GTSEL001   (1UL<<8)   /* b21-23 : 001 */
    182. 

  182. #define M32R_MFTMOD_GTSEL010   (2UL<<8)   /* b21-23 : 010 */
    183. 

  183. #define M32R_MFTMOD_GTSEL011   (3UL<<8)   /* b21-23 : 011 */
    184. 

  184. #define M32R_MFTMOD_GTSEL110   (6UL<<8)   /* b21-23 : 110 */
    185. 

  185. #define M32R_MFTMOD_GTSEL111   (7UL<<8)   /* b21-23 : 111 */
    186. 

  186. #define M32R_MFTMOD_CMSEL      (1UL<<3)   /* b28 */
    187. 

  187. #define M32R_MFTMOD_CSSEL000   (0UL<<0)   /* b29-b31 : 000 */
    188. 

  188. #define M32R_MFTMOD_CSSEL001   (1UL<<0)   /* b29-b31 : 001 */
    189. 

  189. #define M32R_MFTMOD_CSSEL010   (2UL<<0)   /* b29-b31 : 010 */
    190. 

  190. #define M32R_MFTMOD_CSSEL011   (3UL<<0)   /* b29-b31 : 011 */
    191. 

  191. #define M32R_MFTMOD_CSSEL100   (4UL<<0)   /* b29-b31 : 100 */
    192. 

  192. #define M32R_MFTMOD_CSSEL110   (6UL<<0)   /* b29-b31 : 110 */
    193. 

  193. 

  194. /*
    195. 

  195.  * Serial I/O registers.
    196. 

  196.  */
    197. 

  197. #define M32R_SIO_OFFSET  (0x000FD000+M32R_SFR_OFFSET)
    198. 

  198. 

  199. #define M32R_SIO0_CR_PORTL     (0x000+M32R_SIO_OFFSET)
    200. 

  200. #define M32R_SIO0_MOD0_PORTL   (0x004+M32R_SIO_OFFSET)
    201. 

  201. #define M32R_SIO0_MOD1_PORTL   (0x008+M32R_SIO_OFFSET)
    202. 

  202. #define M32R_SIO0_STS_PORTL    (0x00C+M32R_SIO_OFFSET)
    203. 

  203. #define M32R_SIO0_TRCR_PORTL   (0x010+M32R_SIO_OFFSET)
    204. 

  204. #define M32R_SIO0_BAUR_PORTL   (0x014+M32R_SIO_OFFSET)
    205. 

  205. #define M32R_SIO0_RBAUR_PORTL  (0x018+M32R_SIO_OFFSET)
    206. 

  206. #define M32R_SIO0_TXB_PORTL    (0x01C+M32R_SIO_OFFSET)
    207. 

  207. #define M32R_SIO0_RXB_PORTL    (0x020+M32R_SIO_OFFSET)
    208. 

  208. 

  209. /*
    210. 

  210.  * Interrupt Control Unit registers.
    211. 

  211.  */
    212. 

  212. #define M32R_ICU_OFFSET  (0x000FF000+M32R_SFR_OFFSET)
    213. 

  213. 

  214. #define M32R_ICU_ISTS_PORTL     (0x004+M32R_ICU_OFFSET)
    215. 

  215. #define M32R_ICU_IREQ0_PORTL    (0x008+M32R_ICU_OFFSET)
    216. 

  216. #define M32R_ICU_IREQ1_PORTL    (0x00C+M32R_ICU_OFFSET)
    217. 

  217. #define M32R_ICU_SBICR_PORTL    (0x018+M32R_ICU_OFFSET)
    218. 

  218. #define M32R_ICU_IMASK_PORTL    (0x01C+M32R_ICU_OFFSET)
    219. 

  219. #define M32R_ICU_CR1_PORTL      (0x200+M32R_ICU_OFFSET)  /* INT0 */
    220.