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memoryDefinitionAgingAnalysisData.h

memoryDefinitionAgingAnalysisData.h 4.8 KB
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  1. /*
    2. 

  2.  * OMAP3430 Power/Reset Management register bits
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2007-2008 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2007-2008 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Written by Paul Walmsley
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License version 2 as
    11. 

  11.  * published by the Free Software Foundation.
    12. 

  12.  */
    13. 

  13. #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
    14. 

  14. #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
    15. 

  15. 

  16. 

  17. #include "prm3xxx.h"
    18. 

  18. 

  19. /* Shared register bits */
    20. 

  20. 

  21. /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
    22. 

  22. #define OMAP3430_ON_SHIFT				24
    23. 

  23. #define OMAP3430_ON_MASK				(0xff << 24)
    24. 

  24. #define OMAP3430_ONLP_SHIFT				16
    25. 

  25. #define OMAP3430_ONLP_MASK				(0xff << 16)
    26. 

  26. #define OMAP3430_RET_SHIFT				8
    27. 

  27. #define OMAP3430_RET_MASK				(0xff << 8)
    28. 

  28. #define OMAP3430_OFF_SHIFT				0
    29. 

  29. #define OMAP3430_OFF_MASK				(0xff << 0)
    30. 

  30. 

  31. /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
    32. 

  32. #define OMAP3430_ERROROFFSET_SHIFT			24
    33. 

  33. #define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
    34. 

  34. #define OMAP3430_ERRORGAIN_SHIFT			16
    35. 

  35. #define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
    36. 

  36. #define OMAP3430_INITVOLTAGE_SHIFT			8
    37. 

  37. #define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
    38. 

  38. #define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
    39. 

  39. #define OMAP3430_INITVDD_MASK				(1 << 2)
    40. 

  40. #define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
    41. 

  41. #define OMAP3430_VPENABLE_MASK				(1 << 0)
    42. 

  42. 

  43. /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
    44. 

  44. #define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
    45. 

  45. #define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
    46. 

  46. #define OMAP3430_VSTEPMIN_SHIFT				0
    47. 

  47. #define OMAP3430_VSTEPMIN_MASK				(0xff << 0)
    48. 

  48. 

  49. /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
    50. 

  50. #define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
    51. 

  51. #define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
    52. 

  52. #define OMAP3430_VSTEPMAX_SHIFT				0
    53. 

  53. #define OMAP3430_VSTEPMAX_MASK				(0xff << 0)
    54. 

  54. 

  55. /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
    56. 

  56. #define OMAP3430_VDDMAX_SHIFT				24
    57. 

  57. #define OMAP3430_VDDMAX_MASK				(0xff << 24)
    58. 

  58. #define OMAP3430_VDDMIN_SHIFT				16
    59. 

  59. #define OMAP3430_VDDMIN_MASK				(0xff << 16)
    60. 

  60. #define OMAP3430_TIMEOUT_SHIFT				0
    61. 

  61. #define OMAP3430_TIMEOUT_MASK				(0xffff << 0)
    62. 

  62. 

  63. /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
    64. 

  64. #define OMAP3430_VPVOLTAGE_SHIFT			0
    65. 

  65. #define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
    66. 

  66. 

  67. /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
    68. 

  68. #define OMAP3430_VPINIDLE_MASK				(1 << 0)
    69. 

  69. 

  70. /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
    71. 

  71. #define OMAP3430_EN_PER_SHIFT				7
    72. 

  72. #define OMAP3430_EN_PER_MASK				(1 << 7)
    73. 

  73. 

  74. /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
    75. 

  75. #define OMAP3430_MEMORYCHANGE_MASK			(1 << 3)
    76. 

  76. 

  77. /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
    78. 

  78. #define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
    79. 

  79. 

  80. /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
    81. 

  81. #define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
    82. 

  82. 

  83. /*
    84. 

  84.  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
    85. 

  85.  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
    86. 

  86.  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
    87. 

  87.  */
    88. 

  88. #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT		0
    89. 

  89. #define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
    90. 

  90. 

  91. /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
    92. 

  92. #define OMAP3430_WKUP_ST_MASK				(1 << 0)
    93. 

  93. 

  94. /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
    95. 

  95. #define OMAP3430_WKUP_EN_MASK				(1 << 0)
    96. 

  96. 

  97. /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
    98. 

  98. #define OMAP3430_GRPSEL_MMC2_MASK			(1 << 25)
    99. 

  99. #define OMAP3430_GRPSEL_MMC1_MASK			(1 << 24)
    100. 

  100. #define OMAP3430_GRPSEL_MCSPI4_MASK			(1 << 21)
    101. 

  101. #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
    102. 

  102. #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
    103. 

  103. #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
    104. 

  104. #define OMAP3430_GRPSEL_I2C3_SHIFT			17
    105. 

  105. #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
    106. 

  106. #define OMAP3430_GRPSEL_I2C2_SHIFT			16
    107. 

  107. #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
    108. 

  108. #define OMAP3430_GRPSEL_I2C1_SHIFT			15
    109. 

  109. #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
    110. 

  110. #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
    111. 

  111. #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
    112. 

  112. #define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12)
    113. 

  113. #define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11)
    114. 

  114. #define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
    115. 

  115. #define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
    116. 

  116. #define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4)
    117. 

  117. #define OMAP3430_GRPSEL_D2D_MASK			(1 << 3)
    118. 

  118. 

  119. /*
    120. 

  120.  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
    121. 

  121.  * PM_PWSTCTRL_PER shared bits
    122. 

  122.  */
    123. 

  123. #define OMAP3430_MEMONSTATE_SHIFT			16
    124. 

  124. #define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
    125. 

  125. #define OMAP3430_MEMRETSTATE_MASK			(1 << 8)
    126. 

  126. 

  127. /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
    128. 

  128. #define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
    129. 

  129. #define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
    130. 

  130. #define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
    131. 

  131. #define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
    132. 

  132. #define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
    133. 

  133. #define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
    134. 

  134. #define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
    135. 

  135. #define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10)
    136.