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synchronousMemoryDatabase.h

synchronousMemoryDatabase.h 1.7 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
    3. 

  3.  *
    4. 

  4.  * The code contained herein is licensed under the GNU General Public
    5. 

  5.  * License. You may obtain a copy of the GNU General Public License
    6. 

  6.  * Version 2 or later at the following locations:
    7. 

  7.  *
    8. 

  8.  * http://www.opensource.org/licenses/gpl-license.html
    9. 

  9.  * http://www.gnu.org/copyleft/gpl.html
    10. 

  10.  */
    11. 

  11. #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
    12. 

  12. #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
    13. 

  13. 

  14. #define MX51_CCM_BASE		MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
    15. 

  15. #define MX51_DPLL1_BASE		MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
    16. 

  16. #define MX51_DPLL2_BASE		MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
    17. 

  17. #define MX51_DPLL3_BASE		MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
    18. 

  18. #define MX51_CORTEXA8_BASE	MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
    19. 

  19. #define MX51_GPC_BASE		MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
    20. 

  20. 

  21. /*MX53*/
    22. 

  22. #define MX53_CCM_BASE		MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
    23. 

  23. #define MX53_DPLL1_BASE		MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
    24. 

  24. #define MX53_DPLL2_BASE		MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
    25. 

  25. #define MX53_DPLL3_BASE		MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
    26. 

  26. #define MX53_DPLL4_BASE		MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
    27. 

  27. 

  28. /* PLL Register Offsets */
    29. 

  29. #define MXC_PLL_DP_CTL			0x00
    30. 

  30. #define MXC_PLL_DP_CONFIG		0x04
    31. 

  31. #define MXC_PLL_DP_OP			0x08
    32. 

  32. #define MXC_PLL_DP_MFD			0x0C
    33. 

  33. #define MXC_PLL_DP_MFN			0x10
    34. 

  34. #define MXC_PLL_DP_MFNMINUS		0x14
    35. 

  35. #define MXC_PLL_DP_MFNPLUS		0x18
    36. 

  36. #define MXC_PLL_DP_HFS_OP		0x1C
    37. 

  37. #define MXC_PLL_DP_HFS_MFD		0x20
    38. 

  38. #define MXC_PLL_DP_HFS_MFN		0x24
    39. 

  39. #define MXC_PLL_DP_MFN_TOGC		0x28
    40. 

  40. #define MXC_PLL_DP_DESTAT		0x2c
    41. 

  41. 

  42. /* PLL Register Bit definitions */
    43. 

  43. #define MXC_PLL_DP_CTL_MUL_CTRL		0x2000
    44. 

  44. #define MXC_PLL_DP_CTL_DPDCK0_2_EN	0x1000
    45. 

  45. #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET	12
    46. 

  46. #define MXC_PLL_DP_CTL_ADE		0x800
    47. 

  47. #define MXC_PLL_DP_CTL_REF_CLK_DIV	0x400
    48.