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dataMonitoring.h

dataMonitoring.h 2.9 KB
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  1. /*
    2. 

  2.  *
    3. 

  3.  * arch/arm/mach-u300/include/mach/syscon.h
    4. 

  4.  *
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2008-2012 ST-Ericsson AB
    7. 

  7.  *
    8. 

  8.  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __MACH_SYSCON_H
    12. 

  12. #define __MACH_SYSCON_H
    13. 

  13. 

  14. /*
    15. 

  15.  * All register defines for SYSCON registers that concerns individual
    16. 

  16.  * block clocks and reset lines are registered here. This is because
    17. 

  17.  * we don't want any other file to try to fool around with this stuff.
    18. 

  18.  */
    19. 

  19. 

  20. /* APP side SYSCON registers */
    21. 

  21. /* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
    22. 

  22. /* CLK Control Register 16bit (R/W) */
    23. 

  23. #define U300_SYSCON_CCR						(0x0000)
    24. 

  24. #define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
    25. 

  25. #define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
    26. 

  26. #define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
    27. 

  27. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
    28. 

  28. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
    29. 

  29. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
    30. 

  30. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
    31. 

  31. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
    32. 

  32. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
    33. 

  33. /* CLK Status Register 16bit (R/W) */
    34. 

  34. #define U300_SYSCON_CSR						(0x0004)
    35. 

  35. #define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
    36. 

  36. #define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
    37. 

  37. /* Reset lines for SLOW devices 16bit (R/W) */
    38. 

  38. #define U300_SYSCON_RSR						(0x0014)
    39. 

  39. #define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
    40. 

  40. #define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
    41. 

  41. #define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
    42. 

  42. #define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
    43. 

  43. #define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
    44. 

  44. #define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
    45. 

  45. #define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
    46. 

  46. #define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
    47. 

  47. #define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
    48. 

  48. #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
    49. 

  49. /* Reset lines for FAST devices 16bit (R/W) */
    50. 

  50. #define U300_SYSCON_RFR						(0x0018)
    51. 

  51. #define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
    52. 

  52. #define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
    53. 

  53. #define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
    54. 

  54. #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
    55. 

  55. #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
    56. 

  56. #define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
    57. 

  57. #define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
    58. 

  58. #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
    59. 

  59. /* Reset lines for the rest of the peripherals 16bit (R/W) */
    60. 

  60. #define U300_SYSCON_RRR						(0x001c)
    61. 

  61. #define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
    62. 

  62. #define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
    63. 

  63. #define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
    64. 

  64. #define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
    65. 

  65. #define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
    66. 

  66. #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
    67. 

  67. #define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
    68. 

  68. #define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
    69. 

  69. #define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
    70.