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functionDefinition.h

functionDefinition.h 24 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF547_H
    8. 

  8. #define _DEF_BF547_H
    9. 

  9. 

  10. /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
    11. 

  11. #include "defBF54x_base.h"
    12. 

  12. 

  13. /* The following are the #defines needed by ADSP-BF547 that are not in the common header */
    14. 

  14. 

  15. /* Timer Registers */
    16. 

  16. 

  17. #define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
    18. 

  18. #define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
    19. 

  19. #define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
    20. 

  20. #define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
    21. 

  21. #define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
    22. 

  22. #define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
    23. 

  23. #define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
    24. 

  24. #define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
    25. 

  25. #define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
    26. 

  26. #define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
    27. 

  27. #define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
    28. 

  28. #define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
    29. 

  29. 

  30. /* Timer Group of 3 Registers */
    31. 

  31. 

  32. #define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
    33. 

  33. #define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
    34. 

  34. #define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
    35. 

  35. 

  36. /* SPORT0 Registers */
    37. 

  37. 

  38. #define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
    39. 

  39. #define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
    40. 

  40. #define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
    41. 

  41. #define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
    42. 

  42. #define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
    43. 

  43. #define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
    44. 

  44. #define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
    45. 

  45. #define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
    46. 

  46. #define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
    47. 

  47. #define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
    48. 

  48. #define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
    49. 

  49. #define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
    50. 

  50. #define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
    51. 

  51. #define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
    52. 

  52. #define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
    53. 

  53. #define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
    54. 

  54. #define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
    55. 

  55. #define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
    56. 

  56. #define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
    57. 

  57. #define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
    58. 

  58. #define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
    59. 

  59. #define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
    60. 

  60. 

  61. /* EPPI0 Registers */
    62. 

  62. 

  63. #define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
    64. 

  64. #define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
    65. 

  65. #define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
    66. 

  66. #define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
    67. 

  67. #define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
    68. 

  68. #define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
    69. 

  69. #define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
    70. 

  70. #define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
    71. 

  71. #define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
    72. 

  72. #define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
    73. 

  73. #define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
    74. 

  74. #define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
    75. 

  75. #define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
    76. 

  76. #define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
    77. 

  77. 

  78. /* UART2 Registers */
    79. 

  79. 

  80. #define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
    81. 

  81. #define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
    82. 

  82. #define                       UART2_GCTL  0xffc02108   /* Global Control Register */
    83. 

  83. #define                        UART2_LCR  0xffc0210c   /* Line Control Register */
    84. 

  84. #define                        UART2_MCR  0xffc02110   /* Modem Control Register */
    85. 

  85. #define                        UART2_LSR  0xffc02114   /* Line Status Register */
    86. 

  86. #define                        UART2_MSR  0xffc02118   /* Modem Status Register */
    87. 

  87. #define                        UART2_SCR  0xffc0211c   /* Scratch Register */
    88. 

  88. #define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
    89. 

  89. #define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
    90. 

  90. #define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
    91. 

  91. 

  92. /* Two Wire Interface Registers (TWI1) */
    93. 

  93. 

  94. #define                     TWI1_REGBASE  0xffc02200
    95. 

  95. #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
    96. 

  96. #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
    97. 

  97. #define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
    98. 

  98. #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
    99. 

  99. #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
    100. 

  100. #define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
    101. 

  101. #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
    102. 

  102. #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
    103. 

  103. #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
    104. 

  104. #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
    105. 

  105. #define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
    106. 

  106. #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
    107. 

  107. #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
    108. 

  108. #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
    109. 

  109. #define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
    110. 

  110. #define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
    111. 

  111. 

  112. /* SPI2  Registers */
    113. 

  113. 

  114. #define                     SPI2_REGBASE  0xffc02400
    115. 

  115. #define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
    116. 

  116. #define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
    117. 

  117. #define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
    118. 

  118. #define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
    119. 

  119. #define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
    120. 

  120. #define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
    121. 

  121. #define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
    122. 

  122. 

  123. /* ATAPI Registers */
    124. 

  124. 

  125. #define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
    126. 

  126. #define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
    127. 

  127. #define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
    128. 

  128. #define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
    129. 

  129. #define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
    130. 

  130. #define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
    131. 

  131. #define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
    132. 

  132. #define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
    133. 

  133. #define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
    134. 

  134. #define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
    135. 

  135. #define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
    136. 

  136. #define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
    137. 

  137. #define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
    138. 

  138. #define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
    139. 

  139. #define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
    140. 

  140. #define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
    141. 

  141. #define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
    142. 

  142. #define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
    143. 

  143. #define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
    144. 

  144. #define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
    145. 

  145. #define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
    146. 

  146. #define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
    147. 

  147. #define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
    148. 

  148. #define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
    149. 

  149. #define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
    150. 

  150. 

  151. /* SDH Registers */
    152. 

  152. 

  153. #define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
    154. 

  154. #define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
    155. 

  155. #define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
    156. 

  156. #define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
    157. 

  157. #define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
    158. 

  158. #define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
    159. 

  159. #define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
    160. 

  160. #define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
    161. 

  161. #define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
    162. 

  162. #define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
    163. 

  163. #define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
    164. 

  164. #define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
    165. 

  165. #define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
    166. 

  166. #define                       SDH_STATUS  0xffc03934   /* SDH Status */
    167. 

  167. #define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
    168. 

  168. #define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
    169. 

  169. #define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
    170. 

  170. #define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
    171. 

  171. #define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
    172. 

  172. #define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
    173. 

  173. #define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
    174. 

  174. #define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
    175. 

  175. #define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
    176. 

  176. #define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
    177. 

  177. #define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
    178. 

  178. #define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
    179. 

  179. #define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
    180. 

  180. #define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
    181. 

  181. #define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
    182. 

  182. #define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
    183. 

  183. #define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
    184. 

  184. 

  185. /* HOST Port Registers */
    186. 

  186. 

  187. #define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
    188. 

  188. #define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
    189. 

  189. #define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
    190. 

  190. 

  191. /* USB Control Registers */
    192. 

  192. 

  193. #define                        USB_FADDR  0xffc03c00   /* Function address register */
    194. 

  194. #define                        USB_POWER  0xffc03c04   /* Power management register */
    195. 

  195. #define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
    196. 

  196. #define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
    197. 

  197. #define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
    198. 

  198. #define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
    199. 

  199. #define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
    200. 

  200. #define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
    201. 

  201. #define                        USB_FRAME  0xffc03c20   /* USB frame number */
    202. 

  202. #define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
    203. 

  203. #define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
    204. 

  204. #define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
    205. 

  205. #define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
    206. 

  206. 

  207. /* USB Packet Control Registers */
    208. 

  208. 

  209. #define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
    210. 

  210. #define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    211. 

  211. #define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    212. 

  212. #define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
    213. 

  213. #define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
    214. 

  214. #define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    215. 

  215. #define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    216. 

  216. #define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
    217. 

  217. #define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    218. 

  218. #define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    219. 

  219. #define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
    220. 

  220. #define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
    221. 

  221. #define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
    222. 

  222. 

  223. /* USB Endpoint FIFO Registers */
    224. 

  224. 

  225. #define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
    226. 

  226. #define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
    227. 

  227. #define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
    228. 

  228. #define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
    229. 

  229. #define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
    230. 

  230. #define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
    231. 

  231. #define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
    232. 

  232. #define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
    233. 

  233. 

  234. /* USB OTG Control Registers */
    235. 

  235. 

  236. #define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
    237. 

  237. #define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
    238. 

  238. #define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
    239. 

  239. 

  240. /* USB Phy Control Registers */
    241. 

  241. 

  242. #define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
    243. 

  243. #define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
    244. 

  244. #define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
    245. 

  245. #define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
    246. 

  246. #define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
    247. 

  247. 

  248. /* (APHY_CNTRL is for ADI usage only) */
    249. 

  249. 

  250. #define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
    251. 

  251. 

  252. /* (APHY_CALIB is for ADI usage only) */
    253. 

  253. 

  254. #define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
    255. 

  255. #define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
    256. 

  256. 

  257. /* (PHY_TEST is for ADI usage only) */
    258. 

  258. 

  259. #define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
    260. 

  260. #define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
    261. 

  261. #define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
    262. 

  262. 

  263. /* USB Endpoint 0 Control Registers */
    264. 

  264. 

  265. #define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
    266. 

  266. #define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
    267. 

  267. #define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
    268. 

  268. #define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
    269. 

  269. #define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
    270. 

  270. #define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
    271. 

  271. #define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
    272. 

  272. #define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
    273. 

  273. #define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
    274. 

  274. #define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
    275. 

  275. 

  276. /* USB Endpoint 1 Control Registers */
    277. 

  277. 

  278. #define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
    279. 

  279. #define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
    280. 

  280. #define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
    281. 

  281. #define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
    282. 

  282. #define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
    283. 

  283. #define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
    284. 

  284. #define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
    285. 

  285. #define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
    286. 

  286. #define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
    287. 

  287. #define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
    288. 

  288. 

  289. /* USB Endpoint 2 Control Registers */
    290. 

  290. 

  291. #define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
    292. 

  292. #define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
    293. 

  293. #define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
    294. 

  294. #define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
    295. 

  295. #define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
    296. 

  296. #define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
    297. 

  297. #define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
    298. 

  298. #define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
    299. 

  299. #define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
    300. 

  300. #define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
    301. 

  301. 

  302. /* USB Endpoint 3 Control Registers */
    303. 

  303. 

  304. #define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
    305. 

  305. #define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
    306. 

  306. #define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
    307. 

  307. #define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
    308. 

  308. #define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
    309. 

  309. #define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
    310. 

  310. #define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
    311.