aiot/waterDataStatisticsCrossAssociation/dataAssociation/hiddenDangerAnalysis.h

/*
 * Copyright 2007-2010 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef _CDEF_BF522_H
#define _CDEF_BF522_H

/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
#define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)
#define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)
#define bfin_read_VR_CTL()			bfin_read16(VR_CTL)
#define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)
#define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)		bfin_write16(PLL_LOCKCNT, val)
#define bfin_read_CHIPID()			bfin_read32(CHIPID)
#define bfin_write_CHIPID(val)			bfin_write32(CHIPID, val)


/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
#define bfin_read_SWRST()			bfin_read16(SWRST)
#define bfin_write_SWRST(val)			bfin_write16(SWRST, val)
#define bfin_read_SYSCR()			bfin_read16(SYSCR)
#define bfin_write_SYSCR(val)			bfin_write16(SYSCR, val)

#define bfin_read_SIC_RVECT()			bfin_read32(SIC_RVECT)
#define bfin_write_SIC_RVECT(val)		bfin_write32(SIC_RVECT, val)
#define bfin_read_SIC_IMASK0()			bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val)		bfin_write32(SIC_IMASK0, val)
#define bfin_read_SIC_IMASK(x)			bfin_read32(SIC_IMASK0 + (x << 6))
#define bfin_write_SIC_IMASK(x, val)		bfin_write32((SIC_IMASK0 + (x << 6)), val)

#define bfin_read_SIC_IAR0()			bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)		bfin_write32(SIC_IAR0, val)
#define bfin_read_SIC_IAR1()			bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)		bfin_write32(SIC_IAR1, val)
#define bfin_read_SIC_IAR2()			bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)		bfin_write32(SIC_IAR2, val)
#define bfin_read_SIC_IAR3()			bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)		bfin_write32(SIC_IAR3, val)

#define bfin_read_SIC_ISR0()			bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val)		bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR(x)			bfin_read32(SIC_ISR0 + (x << 6))
#define bfin_write_SIC_ISR(x, val)		bfin_write32((SIC_ISR0 + (x << 6)), val)

#define bfin_read_SIC_IWR0()			bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val)		bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR(x)			bfin_read32(SIC_IWR0 + (x << 6))
#define bfin_write_SIC_IWR(x, val)		bfin_write32((SIC_IWR0 + (x << 6)), val)

/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */

#define bfin_read_SIC_IMASK1()			bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val)		bfin_write32(SIC_IMASK1, val)
#define bfin_read_SIC_IAR4()			bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val)		bfin_write32(SIC_IAR4, val)
#define bfin_read_SIC_IAR5()			bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val)		bfin_write32(SIC_IAR5, val)
#define bfin_read_SIC_IAR6()			bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val)		bfin_write32(SIC_IAR6, val)
#define bfin_read_SIC_IAR7()			bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val)		bfin_write32(SIC_IAR7, val)
#define bfin_read_SIC_ISR1()			bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val)		bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_IWR1()			bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val)		bfin_write32(SIC_IWR1, val)