commandProcessing.h 14 KB

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  1. /*
  2. * Copyright 2005-2010 Analog Devices Inc.
  3. *
  4. * Licensed under the GPL-2 or later
  5. */
  6. #ifndef _CDEF_BF532_H
  7. #define _CDEF_BF532_H
  8. /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
  9. #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
  10. #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
  11. #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
  12. #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
  13. #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
  14. #define bfin_read_CHIPID() bfin_read32(CHIPID)
  15. #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
  16. #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
  17. #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
  18. /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
  19. #define bfin_read_SWRST() bfin_read16(SWRST)
  20. #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
  21. #define bfin_read_SYSCR() bfin_read16(SYSCR)
  22. #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
  23. #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
  24. #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
  25. #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
  26. #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
  27. #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
  28. #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
  29. #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
  30. #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
  31. #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
  32. #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
  33. #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
  34. #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
  35. #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
  36. #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
  37. /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
  38. #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
  39. #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
  40. #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
  41. #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
  42. #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
  43. #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
  44. /* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
  45. #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
  46. #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
  47. #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
  48. #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
  49. #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
  50. #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
  51. #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
  52. #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
  53. #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
  54. #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
  55. #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
  56. #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
  57. #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
  58. #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
  59. /* DMA Traffic controls */
  60. #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
  61. #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
  62. #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
  63. #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
  64. /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
  65. #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
  66. #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
  67. #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
  68. #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
  69. #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
  70. #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
  71. #define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
  72. #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
  73. #define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
  74. #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
  75. #define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
  76. #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
  77. #define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
  78. #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
  79. #define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
  80. #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
  81. #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
  82. #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
  83. #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
  84. #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
  85. #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
  86. #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
  87. #define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
  88. #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
  89. #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
  90. #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
  91. #if ANOMALY_05000311
  92. /* Keep at the CPP expansion to avoid circular header dependency loops */
  93. #define BFIN_WRITE_FIO_FLAG(name, val) \
  94. do { \
  95. unsigned long __flags; \
  96. __flags = hard_local_irq_save(); \
  97. bfin_write16(FIO_FLAG_##name, val); \
  98. bfin_read_CHIPID(); \
  99. hard_local_irq_restore(__flags); \
  100. } while (0)
  101. #define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
  102. #define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
  103. #define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
  104. #define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
  105. #define BFIN_READ_FIO_FLAG(name) \
  106. ({ \
  107. unsigned long __flags; \
  108. u16 __ret; \
  109. __flags = hard_local_irq_save(); \
  110. __ret = bfin_read16(FIO_FLAG_##name); \
  111. bfin_read_CHIPID(); \
  112. hard_local_irq_restore(__flags); \
  113. __ret; \
  114. })
  115. #define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
  116. #define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
  117. #define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
  118. #define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
  119. #else
  120. #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
  121. #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
  122. #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
  123. #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
  124. #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
  125. #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
  126. #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
  127. #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
  128. #endif
  129. /* DMA Controller */
  130. #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
  131. #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
  132. #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
  133. #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
  134. #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
  135. #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
  136. #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
  137. #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
  138. #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
  139. #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
  140. #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
  141. #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
  142. #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
  143. #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
  144. #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
  145. #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
  146. #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
  147. #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
  148. #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
  149. #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
  150. #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
  151. #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
  152. #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
  153. #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
  154. #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
  155. #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
  156. #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
  157. #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
  158. #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
  159. #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
  160. #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
  161. #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
  162. #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
  163. #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
  164. #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
  165. #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
  166. #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
  167. #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
  168. #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
  169. #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
  170. #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
  171. #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
  172. #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
  173. #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
  174. #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
  175. #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
  176. #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
  177. #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
  178. #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
  179. #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
  180. #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
  181. #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
  182. #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
  183. #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
  184. #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
  185. #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
  186. #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
  187. #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
  188. #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
  189. #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
  190. #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
  191. #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
  192. #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
  193. #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
  194. #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
  195. #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
  196. #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
  197. #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
  198. #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
  199. #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
  200. #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
  201. #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
  202. #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
  203. #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
  204. #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
  205. #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
  206. #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
  207. #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
  208. #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
  209. #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
  210. #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
  211. #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
  212. #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
  213. #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)