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waterDataPreprocessing
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dataProcessing
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levelDataPreprocessingThread.h

levelDataPreprocessingThread.h 62 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF538_H
    8. 

  8. #define _DEF_BF538_H
    9. 

  9. 

  10. /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
    11. 

  11. #define	PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
    12. 

  12. #define	PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
    13. 

  13. #define	VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    14. 

  14. #define	PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
    15. 

  15. #define	PLL_LOCKCNT		0xFFC00010	/* PLL Lock	Count register (16-bit) */
    16. 

  16. #define	CHIPID			0xFFC00014	/* Chip	ID Register */
    17. 

  17. 

  18. /* CHIPID Masks */
    19. 

  19. #define CHIPID_VERSION         0xF0000000
    20. 

  20. #define CHIPID_FAMILY          0x0FFFF000
    21. 

  21. #define CHIPID_MANUFACTURE     0x00000FFE
    22. 

  22. 

  23. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
    24. 

  24. #define	SWRST			0xFFC00100  /* Software	Reset Register (16-bit) */
    25. 

  25. #define	SYSCR			0xFFC00104  /* System Configuration registe */
    26. 

  26. #define	SIC_RVECT		0xFFC00108
    27. 

  27. #define	SIC_IMASK0		0xFFC0010C  /* Interrupt Mask Register */
    28. 

  28. #define	SIC_IAR0		0xFFC00110  /* Interrupt Assignment Register 0 */
    29. 

  29. #define	SIC_IAR1		0xFFC00114  /* Interrupt Assignment Register 1 */
    30. 

  30. #define	SIC_IAR2		0xFFC00118  /* Interrupt Assignment Register 2 */
    31. 

  31. #define	SIC_IAR3			0xFFC0011C	/* Interrupt Assignment	Register 3 */
    32. 

  32. #define	SIC_ISR0			0xFFC00120  /* Interrupt Status	Register */
    33. 

  33. #define	SIC_IWR0			0xFFC00124  /* Interrupt Wakeup	Register */
    34. 

  34. #define	SIC_IMASK1			0xFFC00128	/* Interrupt Mask Register 1 */
    35. 

  35. #define	SIC_ISR1			0xFFC0012C	/* Interrupt Status Register 1 */
    36. 

  36. #define	SIC_IWR1			0xFFC00130	/* Interrupt Wakeup Register 1 */
    37. 

  37. #define	SIC_IAR4			0xFFC00134	/* Interrupt Assignment	Register 4 */
    38. 

  38. #define	SIC_IAR5			0xFFC00138	/* Interrupt Assignment	Register 5 */
    39. 

  39. #define	SIC_IAR6			0xFFC0013C	/* Interrupt Assignment	Register 6 */
    40. 

  40. 

  41. 

  42. /* Watchdog Timer (0xFFC00200 -	0xFFC002FF) */
    43. 

  43. #define	WDOG_CTL	0xFFC00200  /* Watchdog	Control	Register */
    44. 

  44. #define	WDOG_CNT	0xFFC00204  /* Watchdog	Count Register */
    45. 

  45. #define	WDOG_STAT	0xFFC00208  /* Watchdog	Status Register */
    46. 

  46. 

  47. 

  48. /* Real	Time Clock (0xFFC00300 - 0xFFC003FF) */
    49. 

  49. #define	RTC_STAT	0xFFC00300  /* RTC Status Register */
    50. 

  50. #define	RTC_ICTL	0xFFC00304  /* RTC Interrupt Control Register */
    51. 

  51. #define	RTC_ISTAT	0xFFC00308  /* RTC Interrupt Status Register */
    52. 

  52. #define	RTC_SWCNT	0xFFC0030C  /* RTC Stopwatch Count Register */
    53. 

  53. #define	RTC_ALARM	0xFFC00310  /* RTC Alarm Time Register */
    54. 

  54. #define	RTC_FAST	0xFFC00314  /* RTC Prescaler Enable Register */
    55. 

  55. #define	RTC_PREN		0xFFC00314  /* RTC Prescaler Enable Register (alternate	macro) */
    56. 

  56. 

  57. 

  58. /* UART0 Controller (0xFFC00400	- 0xFFC004FF) */
    59. 

  59. #define	UART0_THR	      0xFFC00400  /* Transmit Holding register */
    60. 

  60. #define	UART0_RBR	      0xFFC00400  /* Receive Buffer register */
    61. 

  61. #define	UART0_DLL	      0xFFC00400  /* Divisor Latch (Low-Byte) */
    62. 

  62. #define	UART0_IER	      0xFFC00404  /* Interrupt Enable Register */
    63. 

  63. #define	UART0_DLH	      0xFFC00404  /* Divisor Latch (High-Byte) */
    64. 

  64. #define	UART0_IIR	      0xFFC00408  /* Interrupt Identification Register */
    65. 

  65. #define	UART0_LCR	      0xFFC0040C  /* Line Control Register */
    66. 

  66. #define	UART0_MCR			 0xFFC00410  /*	Modem Control Register */
    67. 

  67. #define	UART0_LSR	      0xFFC00414  /* Line Status Register */
    68. 

  68. #define	UART0_SCR	      0xFFC0041C  /* SCR Scratch Register */
    69. 

  69. #define	UART0_GCTL		     0xFFC00424	 /* Global Control Register */
    70. 

  70. 

  71. 

  72. /* SPI0	Controller (0xFFC00500 - 0xFFC005FF) */
    73. 

  73. 

  74. #define	SPI0_CTL			0xFFC00500  /* SPI0 Control Register */
    75. 

  75. #define	SPI0_FLG			0xFFC00504  /* SPI0 Flag register */
    76. 

  76. #define	SPI0_STAT			0xFFC00508  /* SPI0 Status register */
    77. 

  77. #define	SPI0_TDBR			0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
    78. 

  78. #define	SPI0_RDBR			0xFFC00510  /* SPI0 Receive Data Buffer	Register */
    79. 

  79. #define	SPI0_BAUD			0xFFC00514  /* SPI0 Baud rate Register */
    80. 

  80. #define	SPI0_SHADOW			0xFFC00518  /* SPI0_RDBR Shadow	Register */
    81. 

  81. #define SPI0_REGBASE			SPI0_CTL
    82. 

  82. 

  83. 

  84. /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
    85. 

  85. #define	TIMER0_CONFIG			0xFFC00600     /* Timer	0 Configuration	Register */
    86. 

  86. #define	TIMER0_COUNTER				0xFFC00604     /* Timer	0 Counter Register */
    87. 

  87. #define	TIMER0_PERIOD			0xFFC00608     /* Timer	0 Period Register */
    88. 

  88. #define	TIMER0_WIDTH			0xFFC0060C     /* Timer	0 Width	Register */
    89. 

  89. 

  90. #define	TIMER1_CONFIG			0xFFC00610	/*  Timer 1 Configuration Register   */
    91. 

  91. #define	TIMER1_COUNTER			0xFFC00614	/*  Timer 1 Counter Register	     */
    92. 

  92. #define	TIMER1_PERIOD			0xFFC00618	/*  Timer 1 Period Register	     */
    93. 

  93. #define	TIMER1_WIDTH			0xFFC0061C	/*  Timer 1 Width Register	     */
    94. 

  94. 

  95. #define	TIMER2_CONFIG			0xFFC00620	/* Timer 2 Configuration Register   */
    96. 

  96. #define	TIMER2_COUNTER			0xFFC00624	/* Timer 2 Counter Register	    */
    97. 

  97. #define	TIMER2_PERIOD			0xFFC00628	/* Timer 2 Period Register	    */
    98. 

  98. #define	TIMER2_WIDTH			0xFFC0062C	/* Timer 2 Width Register	    */
    99. 

  99. 

  100. #define	TIMER_ENABLE				0xFFC00640	/* Timer Enable	Register */
    101. 

  101. #define	TIMER_DISABLE				0xFFC00644	/* Timer Disable Register */
    102. 

  102. #define	TIMER_STATUS				0xFFC00648	/* Timer Status	Register */
    103. 

  103. 

  104. 

  105. /* Programmable	Flags (0xFFC00700 - 0xFFC007FF) */
    106. 

  106. #define	FIO_FLAG_D				0xFFC00700  /* Flag Mask to directly specify state of pins */
    107. 

  107. #define	FIO_FLAG_C			0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
    108. 

  108. #define	FIO_FLAG_S			0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
    109. 

  109. #define	FIO_FLAG_T					0xFFC0070C  /* Flag Mask to directly toggle state of pins */
    110. 

  110. #define	FIO_MASKA_D			0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
    111. 

  111. #define	FIO_MASKA_C			0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
    112. 

  112. #define	FIO_MASKA_S			0xFFC00718  /* Flag Mask Interrupt A Register (set) */
    113. 

  113. #define	FIO_MASKA_T			0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
    114. 

  114. #define	FIO_MASKB_D			0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
    115. 

  115. #define	FIO_MASKB_C			0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
    116. 

  116. #define	FIO_MASKB_S			0xFFC00728  /* Flag Mask Interrupt B Register (set) */
    117. 

  117. #define	FIO_MASKB_T			0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
    118. 

  118. #define	FIO_DIR				0xFFC00730  /* Peripheral Flag Direction Register */
    119. 

  119. #define	FIO_POLAR			0xFFC00734  /* Flag Source Polarity Register */
    120. 

  120. #define	FIO_EDGE			0xFFC00738  /* Flag Source Sensitivity Register */
    121. 

  121. #define	FIO_BOTH			0xFFC0073C  /* Flag Set	on BOTH	Edges Register */
    122. 

  122. #define	FIO_INEN					0xFFC00740  /* Flag Input Enable Register  */
    123. 

  123. 

  124. 

  125. /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
    126. 

  126. #define	SPORT0_TCR1				0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
    127. 

  127. #define	SPORT0_TCR2				0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
    128. 

  128. #define	SPORT0_TCLKDIV			0xFFC00808  /* SPORT0 Transmit Clock Divider */
    129. 

  129. #define	SPORT0_TFSDIV			0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
    130. 

  130. #define	SPORT0_TX			0xFFC00810  /* SPORT0 TX Data Register */
    131. 

  131. #define	SPORT0_RX			0xFFC00818  /* SPORT0 RX Data Register */
    132. 

  132. #define	SPORT0_RCR1				0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
    133. 

  133. #define	SPORT0_RCR2				0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
    134. 

  134. #define	SPORT0_RCLKDIV			0xFFC00828  /* SPORT0 Receive Clock Divider */
    135. 

  135. #define	SPORT0_RFSDIV			0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
    136. 

  136. #define	SPORT0_STAT			0xFFC00830  /* SPORT0 Status Register */
    137. 

  137. #define	SPORT0_CHNL			0xFFC00834  /* SPORT0 Current Channel Register */
    138. 

  138. #define	SPORT0_MCMC1			0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
    139. 

  139. #define	SPORT0_MCMC2			0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
    140. 

  140. #define	SPORT0_MTCS0			0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
    141. 

  141. #define	SPORT0_MTCS1			0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
    142. 

  142. #define	SPORT0_MTCS2			0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
    143. 

  143. #define	SPORT0_MTCS3			0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
    144. 

  144. #define	SPORT0_MRCS0			0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
    145. 

  145. #define	SPORT0_MRCS1			0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
    146. 

  146. #define	SPORT0_MRCS2			0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
    147. 

  147. #define	SPORT0_MRCS3			0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
    148. 

  148. 

  149. 

  150. /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
    151. 

  151. #define	SPORT1_TCR1				0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
    152. 

  152. #define	SPORT1_TCR2				0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
    153. 

  153. #define	SPORT1_TCLKDIV			0xFFC00908  /* SPORT1 Transmit Clock Divider */
    154. 

  154. #define	SPORT1_TFSDIV			0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
    155. 

  155. #define	SPORT1_TX			0xFFC00910  /* SPORT1 TX Data Register */
    156. 

  156. #define	SPORT1_RX			0xFFC00918  /* SPORT1 RX Data Register */
    157. 

  157. #define	SPORT1_RCR1				0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
    158. 

  158. #define	SPORT1_RCR2				0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
    159. 

  159. #define	SPORT1_RCLKDIV			0xFFC00928  /* SPORT1 Receive Clock Divider */
    160. 

  160. #define	SPORT1_RFSDIV			0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
    161. 

  161. #define	SPORT1_STAT			0xFFC00930  /* SPORT1 Status Register */
    162. 

  162. #define	SPORT1_CHNL			0xFFC00934  /* SPORT1 Current Channel Register */
    163. 

  163. #define	SPORT1_MCMC1			0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
    164. 

  164. #define	SPORT1_MCMC2			0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
    165. 

  165. #define	SPORT1_MTCS0			0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
    166. 

  166. #define	SPORT1_MTCS1			0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
    167. 

  167. #define	SPORT1_MTCS2			0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
    168. 

  168. #define	SPORT1_MTCS3			0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
    169. 

  169. #define	SPORT1_MRCS0			0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
    170. 

  170. #define	SPORT1_MRCS1			0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
    171. 

  171. #define	SPORT1_MRCS2			0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
    172. 

  172. #define	SPORT1_MRCS3			0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
    173. 

  173. 

  174. 

  175. /* External Bus	Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
    176. 

  176. /* Asynchronous	Memory Controller  */
    177. 

  177. #define	EBIU_AMGCTL			0xFFC00A00  /* Asynchronous Memory Global Control Register */
    178. 

  178. #define	EBIU_AMBCTL0		0xFFC00A04  /* Asynchronous Memory Bank	Control	Register 0 */
    179. 

  179. #define	EBIU_AMBCTL1		0xFFC00A08  /* Asynchronous Memory Bank	Control	Register 1 */
    180. 

  180. 

  181. /* SDRAM Controller */
    182. 

  182. #define	EBIU_SDGCTL			0xFFC00A10  /* SDRAM Global Control Register */
    183. 

  183. #define	EBIU_SDBCTL			0xFFC00A14  /* SDRAM Bank Control Register */
    184. 

  184. #define	EBIU_SDRRC			0xFFC00A18  /* SDRAM Refresh Rate Control Register */
    185. 

  185. #define	EBIU_SDSTAT			0xFFC00A1C  /* SDRAM Status Register */
    186. 

  186. 

  187. 

  188. 

  189. /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
    190. 

  190. 

  191. #define	DMAC0_TC_PER			0xFFC00B0C	/* DMA Controller 0 Traffic Control Periods Register */
    192. 

  192. #define	DMAC0_TC_CNT			0xFFC00B10	/* DMA Controller 0 Traffic Control Current Counts Register */
    193. 

  193. 

  194. 

  195. 

  196. /* DMA Controller 0 (0xFFC00C00	- 0xFFC00FFF)							 */
    197. 

  197. 

  198. #define	DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
    199. 

  199. #define	DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register */
    200. 

  200. #define	DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register */
    201. 

  201. #define	DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register */
    202. 

  202. #define	DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register */
    203. 

  203. #define	DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register */
    204. 

  204. #define	DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
    205. 

  205. #define	DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
    206. 

  206. #define	DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register */
    207. 

  207. #define	DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
    208. 

  208. #define	DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map	Register */
    209. 

  209. #define	DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register */
    210. 

  210. #define	DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
    211. 

  211. 

  212. #define	DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
    213. 

  213. #define	DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register */
    214. 

  214. #define	DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register */
    215. 

  215. #define	DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register */
    216. 

  216. #define	DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register */
    217. 

  217. #define	DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register */
    218. 

  218. #define	DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
    219. 

  219. #define	DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
    220. 

  220. #define	DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register */
    221. 

  221. #define	DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
    222. 

  222. #define	DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map	Register */
    223. 

  223. #define	DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register */
    224. 

  224. #define	DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
    225. 

  225. 

  226. #define	DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
    227. 

  227. #define	DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register */
    228. 

  228. #define	DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register */
    229. 

  229. #define	DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register */
    230. 

  230. #define	DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register */
    231. 

  231. #define	DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register */
    232. 

  232. #define	DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
    233. 

  233. #define	DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
    234. 

  234. #define	DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register */
    235. 

  235. #define	DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
    236. 

  236. #define	DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map	Register */
    237. 

  237. #define	DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
    238. 

  238. #define	DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
    239. 

  239. 

  240. #define	DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
    241. 

  241. #define	DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register */
    242. 

  242. #define	DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register */
    243. 

  243. #define	DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register */
    244. 

  244. #define	DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register */
    245. 

  245. #define	DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register */
    246. 

  246. #define	DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
    247. 

  247. #define	DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
    248. 

  248. #define	DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register */
    249. 

  249. #define	DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
    250. 

  250. #define	DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map	Register */
    251. 

  251. #define	DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
    252. 

  252. #define	DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
    253. 

  253. 

  254. #define	DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
    255. 

  255. #define	DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register */
    256. 

  256. #define	DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register */
    257. 

  257. #define	DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register */
    258. 

  258. #define	DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register */
    259. 

  259. #define	DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register */
    260. 

  260. #define	DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
    261. 

  261. #define	DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
    262. 

  262. #define	DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register */
    263. 

  263. #define	DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
    264. 

  264. #define	DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map	Register */
    265. 

  265. #define	DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register */
    266. 

  266. #define	DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
    267. 

  267. 

  268. #define	DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
    269. 

  269. #define	DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register */
    270. 

  270. #define	DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register */
    271. 

  271. #define	DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register */
    272. 

  272. #define	DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register */
    273. 

  273. #define	DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register */
    274. 

  274. #define	DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
    275. 

  275. #define	DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
    276. 

  276. #define	DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register */
    277. 

  277. #define	DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
    278. 

  278. #define	DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map	Register */
    279. 

  279. #define	DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register */
    280. 

  280. #define	DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
    281. 

  281. 

  282. #define	DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
    283. 

  283. #define	DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register */
    284. 

  284. #define	DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register */
    285. 

  285. #define	DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register */
    286. 

  286. #define	DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register */
    287. 

  287. #define	DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register */
    288. 

  288. #define	DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
    289. 

  289. #define	DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
    290. 

  290. #define	DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register */
    291. 

  291. #define	DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
    292. 

  292. #define	DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map	Register */
    293. 

  293. #define	DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
    294. 

  294. #define	DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
    295. 

  295. 

  296. #define	DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
    297. 

  297. #define	DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register */
    298. 

  298. #define	DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register */
    299. 

  299. #define	DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register */
    300. 

  300. #define	DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register */
    301. 

  301. #define	DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register */
    302. 

  302. #define	DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
    303. 

  303. #define	DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
    304. 

  304. #define	DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register */
    305. 

  305. #define	DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
    306. 

  306. #define	DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map	Register */
    307. 

  307. #define	DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
    308. 

  308. #define	DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
    309. 

  309. 

  310. #define	MDMA_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA0 Stream 0 Destination	Next Descriptor	Pointer	Register */
    311. 

  311. #define	MDMA_D0_START_ADDR		0xFFC00E04	/* MemDMA0 Stream 0 Destination	Start Address Register */
    312. 

  312. #define	MDMA_D0_CONFIG			0xFFC00E08	/* MemDMA0 Stream 0 Destination	Configuration Register */
    313. 

  313. #define	MDMA_D0_X_COUNT		0xFFC00E10	/* MemDMA0 Stream 0 Destination	X Count	Register */
    314. 

  314. #define	MDMA_D0_X_MODIFY		0xFFC00E14	/* MemDMA0 Stream 0 Destination	X Modify Register */
    315. 

  315. #define	MDMA_D0_Y_COUNT		0xFFC00E18	/* MemDMA0 Stream 0 Destination	Y Count	Register */
    316. 

  316. #define	MDMA_D0_Y_MODIFY		0xFFC00E1C	/* MemDMA0 Stream 0 Destination	Y Modify Register */
    317. 

  317. #define	MDMA_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA0 Stream 0 Destination	Current	Descriptor Pointer Register */
    318. 

  318. #define	MDMA_D0_CURR_ADDR		0xFFC00E24	/* MemDMA0 Stream 0 Destination	Current	Address	Register */
    319. 

  319. #define	MDMA_D0_IRQ_STATUS		0xFFC00E28	/* MemDMA0 Stream 0 Destination	Interrupt/Status Register */
    320. 

  320. #define	MDMA_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA0 Stream 0 Destination	Peripheral Map Register */
    321. 

  321. #define	MDMA_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA0 Stream 0 Destination	Current	X Count	Register */
    322. 

  322. #define	MDMA_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA0 Stream 0 Destination	Current	Y Count	Register */
    323. 

  323. 

  324. #define	MDMA_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA0 Stream 0 Source Next	Descriptor Pointer Register */
    325. 

  325. #define	MDMA_S0_START_ADDR		0xFFC00E44	/* MemDMA0 Stream 0 Source Start Address Register */
    326. 

  326. #define	MDMA_S0_CONFIG			0xFFC00E48	/* MemDMA0 Stream 0 Source Configuration Register */
    327. 

  327. #define	MDMA_S0_X_COUNT		0xFFC00E50	/* MemDMA0 Stream 0 Source X Count Register */
    328. 

  328. #define	MDMA_S0_X_MODIFY		0xFFC00E54	/* MemDMA0 Stream 0 Source X Modify Register */
    329. 

  329. #define	MDMA_S0_Y_COUNT		0xFFC00E58	/* MemDMA0 Stream 0 Source Y Count Register */
    330. 

  330. #define	MDMA_S0_Y_MODIFY		0xFFC00E5C	/* MemDMA0 Stream 0 Source Y Modify Register */
    331. 

  331. #define	MDMA_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
    332. 

  332. #define	MDMA_S0_CURR_ADDR		0xFFC00E64	/* MemDMA0 Stream 0 Source Current Address Register */
    333. 

  333. #define	MDMA_S0_IRQ_STATUS		0xFFC00E68	/* MemDMA0 Stream 0 Source Interrupt/Status Register */
    334. 

  334. #define	MDMA_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA0 Stream 0 Source Peripheral Map Register */
    335. 

  335. #define	MDMA_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA0 Stream 0 Source Current X Count Register */
    336. 

  336. #define	MDMA_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA0 Stream 0 Source Current Y Count Register */
    337. 

  337. 

  338. #define	MDMA_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA0 Stream 1 Destination	Next Descriptor	Pointer	Register */
    339. 

  339. #define	MDMA_D1_START_ADDR		0xFFC00E84	/* MemDMA0 Stream 1 Destination	Start Address Register */
    340. 

  340. #define	MDMA_D1_CONFIG			0xFFC00E88	/* MemDMA0 Stream 1 Destination	Configuration Register */
    341. 

  341. #define	MDMA_D1_X_COUNT		0xFFC00E90	/* MemDMA0 Stream 1 Destination	X Count	Register */
    342. 

  342. #define	MDMA_D1_X_MODIFY		0xFFC00E94	/* MemDMA0 Stream 1 Destination	X Modify Register */
    343. 

  343. #define	MDMA_D1_Y_COUNT		0xFFC00E98	/* MemDMA0 Stream 1 Destination	Y Count	Register */
    344. 

  344. #define	MDMA_D1_Y_MODIFY		0xFFC00E9C	/* MemDMA0 Stream 1 Destination	Y Modify Register */
    345. 

  345. #define	MDMA_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA0 Stream 1 Destination	Current	Descriptor Pointer Register */
    346. 

  346. #define	MDMA_D1_CURR_ADDR		0xFFC00EA4	/* MemDMA0 Stream 1 Destination	Current	Address	Register */
    347. 

  347. #define	MDMA_D1_IRQ_STATUS		0xFFC00EA8	/* MemDMA0 Stream 1 Destination	Interrupt/Status Register */
    348. 

  348. #define	MDMA_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA0 Stream 1 Destination	Peripheral Map Register */
    349. 

  349. #define	MDMA_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA0 Stream 1 Destination	Current	X Count	Register */
    350. 

  350. #define	MDMA_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA0 Stream 1 Destination	Current	Y Count	Register */
    351. 

  351. 

  352. #define	MDMA_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA0 Stream 1 Source Next	Descriptor Pointer Register */
    353. 

  353. #define	MDMA_S1_START_ADDR		0xFFC00EC4	/* MemDMA0 Stream 1 Source Start Address Register */
    354. 

  354. #define	MDMA_S1_CONFIG			0xFFC00EC8	/* MemDMA0 Stream 1 Source Configuration Register */
    355. 

  355. #define	MDMA_S1_X_COUNT		0xFFC00ED0	/* MemDMA0 Stream 1 Source X Count Register */
    356. 

  356. #define	MDMA_S1_X_MODIFY		0xFFC00ED4	/* MemDMA0 Stream 1 Source X Modify Register */
    357. 

  357. #define	MDMA_S1_Y_COUNT		0xFFC00ED8	/* MemDMA0 Stream 1 Source Y Count Register */
    358. 

  358. #define	MDMA_S1_Y_MODIFY		0xFFC00EDC	/* MemDMA0 Stream 1 Source Y Modify Register */
    359. 

  359. #define	MDMA_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
    360. 

  360. #define	MDMA_S1_CURR_ADDR		0xFFC00EE4	/* MemDMA0 Stream 1 Source Current Address Register */
    361. 

  361. #define	MDMA_S1_IRQ_STATUS		0xFFC00EE8	/* MemDMA0 Stream 1 Source Interrupt/Status Register */
    362. 

  362. #define	MDMA_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA0 Stream 1 Source Peripheral Map Register */
    363. 

  363. #define	MDMA_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA0 Stream 1 Source Current X Count Register */
    364. 

  364. #define	MDMA_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA0 Stream 1 Source Current Y Count Register */
    365. 

  365. 

  366. 

  367. /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
    368. 

  368. #define	PPI_CONTROL			0xFFC01000	/* PPI Control Register */
    369. 

  369. #define	PPI_STATUS			0xFFC01004	/* PPI Status Register */
    370. 

  370. #define	PPI_COUNT			0xFFC01008	/* PPI Transfer	Count Register */
    371. 

  371. #define	PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register */
    372. 

  372. #define	PPI_FRAME			0xFFC01010	/* PPI Frame Length Register */
    373. 

  373. 

  374. 

  375. /* Two-Wire Interface 0	(0xFFC01400 - 0xFFC014FF)			 */
    376. 

  376. #define	TWI0_CLKDIV			0xFFC01400	/* Serial Clock	Divider	Register */
    377. 

  377. #define	TWI0_CONTROL		0xFFC01404	/* TWI0	Master Internal	Time Reference Register */
    378. 

  378. #define	TWI0_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register */
    379. 

  379. #define	TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register */
    380. 

  380. #define	TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register */
    381. 

  381. #define	TWI0_MASTER_CTL	0xFFC01414	/* Master Mode Control Register */
    382. 

  382. #define	TWI0_MASTER_STAT	0xFFC01418	/* Master Mode Status Register */
    383. 

  383. #define	TWI0_MASTER_ADDR	0xFFC0141C	/* Master Mode Address Register */
    384. 

  384. #define	TWI0_INT_STAT		0xFFC01420	/* TWI0	Master Interrupt Register */
    385. 

  385. #define	TWI0_INT_MASK		0xFFC01424	/* TWI0	Master Interrupt Mask Register */
    386. 

  386. #define	TWI0_FIFO_CTL		0xFFC01428	/* FIFO	Control	Register */
    387. 

  387. #define	TWI0_FIFO_STAT		0xFFC0142C	/* FIFO	Status Register */
    388. 

  388. #define	TWI0_XMT_DATA8		0xFFC01480	/* FIFO	Transmit Data Single Byte Register */
    389. 

  389. #define	TWI0_XMT_DATA16		0xFFC01484	/* FIFO	Transmit Data Double Byte Register */
    390. 

  390. #define	TWI0_RCV_DATA8		0xFFC01488	/* FIFO	Receive	Data Single Byte Register */
    391. 

  391. #define	TWI0_RCV_DATA16		0xFFC0148C	/* FIFO	Receive	Data Double Byte Register */
    392. 

  392. 

  393. #define TWI0_REGBASE		TWI0_CLKDIV
    394. 

  394. 

  395. /* the following are for backwards compatibility */
    396. 

  396. #define	TWI0_PRESCALE	 TWI0_CONTROL
    397. 

  397. #define	TWI0_INT_SRC	 TWI0_INT_STAT
    398. 

  398. #define	TWI0_INT_ENABLE	 TWI0_INT_MASK
    399. 

  399. 

  400. 

  401. /* General-Purpose Ports  (0xFFC01500 -	0xFFC015FF)	 */
    402. 

  402. 

  403. /* GPIO	Port C Register	Names */
    404. 

  404. #define PORTCIO_FER			0xFFC01500	/* GPIO	Pin Port C Configuration Register */
    405. 

  405. #define PORTCIO				0xFFC01510	/* GPIO	Pin Port C Data	Register */
    406. 

  406. #define PORTCIO_CLEAR			0xFFC01520	/* Clear GPIO Pin Port C Register */
    407. 

  407. #define PORTCIO_SET			0xFFC01530	/* Set GPIO Pin	Port C Register */
    408. 

  408. #define PORTCIO_TOGGLE			0xFFC01540	/* Toggle GPIO Pin Port	C Register */
    409. 

  409. #define PORTCIO_DIR			0xFFC01550	/* GPIO	Pin Port C Direction Register */
    410. 

  410. #define PORTCIO_INEN			0xFFC01560	/* GPIO	Pin Port C Input Enable	Register */
    411. 

  411. 

  412. /* GPIO	Port D Register	Names */
    413. 

  413. #define PORTDIO_FER			0xFFC01504	/* GPIO	Pin Port D Configuration Register */
    414. 

  414. #define PORTDIO				0xFFC01514	/* GPIO	Pin Port D Data	Register */
    415. 

  415. #define PORTDIO_CLEAR			0xFFC01524	/* Clear GPIO Pin Port D Register */
    416. 

  416. #define PORTDIO_SET			0xFFC01534	/* Set GPIO Pin	Port D Register */
    417. 

  417. #define PORTDIO_TOGGLE			0xFFC01544	/* Toggle GPIO Pin Port	D Register */
    418. 

  418. #define PORTDIO_DIR			0xFFC01554	/* GPIO	Pin Port D Direction Register */
    419. 

  419. #define PORTDIO_INEN			0xFFC01564	/* GPIO	Pin Port D Input Enable	Register */
    420. 

  420. 

  421. /* GPIO	Port E Register	Names */
    422. 

  422. #define PORTEIO_FER			0xFFC01508	/* GPIO	Pin Port E Configuration Register */
    423. 

  423. #define PORTEIO				0xFFC01518	/* GPIO	Pin Port E Data	Register */
    424. 

  424. #define PORTEIO_CLEAR			0xFFC01528	/* Clear GPIO Pin Port E Register */
    425. 

  425. #define PORTEIO_SET			0xFFC01538	/* Set GPIO Pin	Port E Register */
    426. 

  426. #define PORTEIO_TOGGLE			0xFFC01548	/* Toggle GPIO Pin Port	E Register */
    427. 

  427. #define PORTEIO_DIR			0xFFC01558	/* GPIO	Pin Port E Direction Register */
    428. 

  428. #define PORTEIO_INEN			0xFFC01568	/* GPIO	Pin Port E Input Enable	Register */
    429. 

  429. 

  430. /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
    431. 

  431. 

  432. #define	DMAC1_TC_PER			0xFFC01B0C	/* DMA Controller 1 Traffic Control Periods Register */
    433. 

  433. #define	DMAC1_TC_CNT			0xFFC01B10	/* DMA Controller 1 Traffic Control Current Counts Register */
    434. 

  434. 

  435. 

  436. 

  437. /* DMA Controller 1 (0xFFC01C00	- 0xFFC01FFF)							 */
    438. 

  438. #define	DMA8_NEXT_DESC_PTR		0xFFC01C00	/* DMA Channel 8 Next Descriptor Pointer Register */
    439. 

  439. #define	DMA8_START_ADDR			0xFFC01C04	/* DMA Channel 8 Start Address Register */
    440. 

  440. #define	DMA8_CONFIG				0xFFC01C08	/* DMA Channel 8 Configuration Register */
    441. 

  441. #define	DMA8_X_COUNT			0xFFC01C10	/* DMA Channel 8 X Count Register */
    442. 

  442. #define	DMA8_X_MODIFY			0xFFC01C14	/* DMA Channel 8 X Modify Register */
    443. 

  443. #define	DMA8_Y_COUNT			0xFFC01C18	/* DMA Channel 8 Y Count Register */
    444. 

  444. #define	DMA8_Y_MODIFY			0xFFC01C1C	/* DMA Channel 8 Y Modify Register */
    445. 

  445. #define	DMA8_CURR_DESC_PTR		0xFFC01C20	/* DMA Channel 8 Current Descriptor Pointer Register */
    446. 

  446. #define	DMA8_CURR_ADDR			0xFFC01C24	/* DMA Channel 8 Current Address Register */
    447. 

  447. #define	DMA8_IRQ_STATUS			0xFFC01C28	/* DMA Channel 8 Interrupt/Status Register */
    448. 

  448. #define	DMA8_PERIPHERAL_MAP		0xFFC01C2C	/* DMA Channel 8 Peripheral Map	Register */
    449. 

  449. #define	DMA8_CURR_X_COUNT		0xFFC01C30	/* DMA Channel 8 Current X Count Register */
    450. 

  450. #define	DMA8_CURR_Y_COUNT		0xFFC01C38	/* DMA Channel 8 Current Y Count Register */
    451. 

  451. 

  452. #define	DMA9_NEXT_DESC_PTR		0xFFC01C40	/* DMA Channel 9 Next Descriptor Pointer Register */
    453. 

  453. #define	DMA9_START_ADDR			0xFFC01C44	/* DMA Channel 9 Start Address Register */
    454. 

  454. #define	DMA9_CONFIG				0xFFC01C48	/* DMA Channel 9 Configuration Register */
    455. 

  455. #define	DMA9_X_COUNT			0xFFC01C50	/* DMA Channel 9 X Count Register */
    456. 

  456. #define	DMA9_X_MODIFY			0xFFC01C54	/* DMA Channel 9 X Modify Register */
    457. 

  457. #define	DMA9_Y_COUNT			0xFFC01C58	/* DMA Channel 9 Y Count Register */
    458. 

  458. #define	DMA9_Y_MODIFY			0xFFC01C5C	/* DMA Channel 9 Y Modify Register */
    459. 

  459. #define	DMA9_CURR_DESC_PTR		0xFFC01C60	/* DMA Channel 9 Current Descriptor Pointer Register */
    460. 

  460. #define	DMA9_CURR_ADDR			0xFFC01C64	/* DMA Channel 9 Current Address Register */
    461. 

  461. #define	DMA9_IRQ_STATUS			0xFFC01C68	/* DMA Channel 9 Interrupt/Status Register */
    462. 

  462. #define	DMA9_PERIPHERAL_MAP		0xFFC01C6C	/* DMA Channel 9 Peripheral Map	Register */
    463. 

  463. #define	DMA9_CURR_X_COUNT		0xFFC01C70	/* DMA Channel 9 Current X Count Register */
    464. 

  464. #define	DMA9_CURR_Y_COUNT		0xFFC01C78	/* DMA Channel 9 Current Y Count Register */
    465. 

  465. 

  466. #define	DMA10_NEXT_DESC_PTR		0xFFC01C80	/* DMA Channel 10 Next Descriptor Pointer Register */
    467. 

  467. #define	DMA10_START_ADDR		0xFFC01C84	/* DMA Channel 10 Start	Address	Register */
    468. 

  468. #define	DMA10_CONFIG			0xFFC01C88	/* DMA Channel 10 Configuration	Register */
    469. 

  469. #define	DMA10_X_COUNT			0xFFC01C90	/* DMA Channel 10 X Count Register */
    470. 

  470. #define	DMA10_X_MODIFY			0xFFC01C94	/* DMA Channel 10 X Modify Register */
    471. 

  471. #define	DMA10_Y_COUNT			0xFFC01C98	/* DMA Channel 10 Y Count Register */
    472. 

  472. #define	DMA10_Y_MODIFY			0xFFC01C9C	/* DMA Channel 10 Y Modify Register */
    473. 

  473. #define	DMA10_CURR_DESC_PTR		0xFFC01CA0	/* DMA Channel 10 Current Descriptor Pointer Register */
    474. 

  474. #define	DMA10_CURR_ADDR			0xFFC01CA4	/* DMA Channel 10 Current Address Register */
    475. 

  475. #define	DMA10_IRQ_STATUS		0xFFC01CA8	/* DMA Channel 10 Interrupt/Status Register */
    476. 

  476. #define	DMA10_PERIPHERAL_MAP	0xFFC01CAC	/* DMA Channel 10 Peripheral Map Register */
    477. 

  477. #define	DMA10_CURR_X_COUNT		0xFFC01CB0	/* DMA Channel 10 Current X Count Register */
    478. 

  478. #define	DMA10_CURR_Y_COUNT		0xFFC01CB8	/* DMA Channel 10 Current Y Count Register */
    479. 

  479. 

  480. #define	DMA11_NEXT_DESC_PTR		0xFFC01CC0	/* DMA Channel 11 Next Descriptor Pointer Register */
    481. 

  481. #define	DMA11_START_ADDR		0xFFC01CC4	/* DMA Channel 11 Start	Address	Register */
    482. 

  482. #define	DMA11_CONFIG			0xFFC01CC8	/* DMA Channel 11 Configuration	Register */
    483. 

  483. #define	DMA11_X_COUNT			0xFFC01CD0	/* DMA Channel 11 X Count Register */
    484. 

  484. #define	DMA11_X_MODIFY			0xFFC01CD4	/* DMA Channel 11 X Modify Register */
    485. 

  485. #define	DMA11_Y_COUNT			0xFFC01CD8	/* DMA Channel 11 Y Count Register */
    486. 

  486. #define	DMA11_Y_MODIFY			0xFFC01CDC	/* DMA Channel 11 Y Modify Register */
    487. 

  487. #define	DMA11_CURR_DESC_PTR		0xFFC01CE0	/* DMA Channel 11 Current Descriptor Pointer Register */
    488. 

  488. #define	DMA11_CURR_ADDR			0xFFC01CE4	/* DMA Channel 11 Current Address Register */
    489. 

  489. #define	DMA11_IRQ_STATUS		0xFFC01CE8	/* DMA Channel 11 Interrupt/Status Register */
    490. 

  490. #define	DMA11_PERIPHERAL_MAP	0xFFC01CEC	/* DMA Channel 11 Peripheral Map Register */
    491. 

  491. #define	DMA11_CURR_X_COUNT		0xFFC01CF0	/* DMA Channel 11 Current X Count Register */
    492. 

  492. #define	DMA11_CURR_Y_COUNT		0xFFC01CF8	/* DMA Channel 11 Current Y Count Register */
    493. 

  493. 

  494. #define	DMA12_NEXT_DESC_PTR		0xFFC01D00	/* DMA Channel 12 Next Descriptor Pointer Register */
    495. 

  495. #define	DMA12_START_ADDR		0xFFC01D04	/* DMA Channel 12 Start	Address	Register */
    496. 

  496. #define	DMA12_CONFIG			0xFFC01D08	/* DMA Channel 12 Configuration	Register */
    497. 

  497. #define	DMA12_X_COUNT			0xFFC01D10	/* DMA Channel 12 X Count Register */
    498. 

  498. #define	DMA12_X_MODIFY			0xFFC01D14	/* DMA Channel 12 X Modify Register */
    499. 

  499. #define	DMA12_Y_COUNT			0xFFC01D18	/* DMA Channel 12 Y Count Register */
    500. 

  500. #define	DMA12_Y_MODIFY			0xFFC01D1C	/* DMA Channel 12 Y Modify Register */
    501. 

  501. #define	DMA12_CURR_DESC_PTR		0xFFC01D20	/* DMA Channel 12 Current Descriptor Pointer Register */
    502. 

  502. #define	DMA12_CURR_ADDR			0xFFC01D24	/* DMA Channel 12 Current Address Register */
    503. 

  503. #define	DMA12_IRQ_STATUS		0xFFC01D28	/* DMA Channel 12 Interrupt/Status Register */
    504. 

  504. #define	DMA12_PERIPHERAL_MAP	0xFFC01D2C	/* DMA Channel 12 Peripheral Map Register */
    505. 

  505. #define	DMA12_CURR_X_COUNT		0xFFC01D30	/* DMA Channel 12 Current X Count Register */
    506. 

  506. #define	DMA12_CURR_Y_COUNT		0xFFC01D38	/* DMA Channel 12 Current Y Count Register */
    507. 

  507. 

  508. #define	DMA13_NEXT_DESC_PTR		0xFFC01D40	/* DMA Channel 13 Next Descriptor Pointer Register */
    509. 

  509. #define	DMA13_START_ADDR		0xFFC01D44	/* DMA Channel 13 Start	Address	Register */
    510. 

  510. #define	DMA13_CONFIG			0xFFC01D48	/* DMA Channel 13 Configuration	Register */
    511. 

  511. #define	DMA13_X_COUNT			0xFFC01D50	/* DMA Channel 13 X Count Register */
    512. 

  512. #define	DMA13_X_MODIFY			0xFFC01D54	/* DMA Channel 13 X Modify Register */
    513. 

  513. #define	DMA13_Y_COUNT			0xFFC01D58	/* DMA Channel 13 Y Count Register */
    514. 

  514. #define	DMA13_Y_MODIFY			0xFFC01D5C	/* DMA Channel 13 Y Modify Register */
    515. 

  515. #define	DMA13_CURR_DESC_PTR		0xFFC01D60	/* DMA Channel 13 Current Descriptor Pointer Register */
    516. 

  516. #define	DMA13_CURR_ADDR			0xFFC01D64	/* DMA Channel 13 Current Address Register */
    517. 

  517. #define	DMA13_IRQ_STATUS		0xFFC01D68	/* DMA Channel 13 Interrupt/Status Register */
    518. 

  518. #define	DMA13_PERIPHERAL_MAP	0xFFC01D6C	/* DMA Channel 13 Peripheral Map Register */
    519. 

  519. #define	DMA13_CURR_X_COUNT		0xFFC01D70	/* DMA Channel 13 Current X Count Register */
    520. 

  520. #define	DMA13_CURR_Y_COUNT		0xFFC01D78	/* DMA Channel 13 Current Y Count Register */
    521. 

  521. 

  522. #define	DMA14_NEXT_DESC_PTR		0xFFC01D80	/* DMA Channel 14 Next Descriptor Pointer Register */
    523. 

  523. #define	DMA14_START_ADDR		0xFFC01D84	/* DMA Channel 14 Start	Address	Register */
    524. 

  524. #define	DMA14_CONFIG			0xFFC01D88	/* DMA Channel 14 Configuration	Register */
    525. 

  525. #define	DMA14_X_COUNT			0xFFC01D90	/* DMA Channel 14 X Count Register */
    526. 

  526. #define	DMA14_X_MODIFY			0xFFC01D94	/* DMA Channel 14 X Modify Register */
    527. 

  527. #define	DMA14_Y_COUNT			0xFFC01D98	/* DMA Channel 14 Y Count Register */
    528. 

  528. #define	DMA14_Y_MODIFY			0xFFC01D9C	/* DMA Channel 14 Y Modify Register */
    529. 

  529. #define	DMA14_CURR_DESC_PTR		0xFFC01DA0	/* DMA Channel 14 Current Descriptor Pointer Register */
    530. 

  530. #define	DMA14_CURR_ADDR			0xFFC01DA4	/* DMA Channel 14 Current Address Register */
    531. 

  531. #define	DMA14_IRQ_STATUS		0xFFC01DA8	/* DMA Channel 14 Interrupt/Status Register */
    532. 

  532. #define	DMA14_PERIPHERAL_MAP	0xFFC01DAC	/* DMA Channel 14 Peripheral Map Register */
    533. 

  533. #define	DMA14_CURR_X_COUNT		0xFFC01DB0	/* DMA Channel 14 Current X Count Register */
    534. 

  534. #define	DMA14_CURR_Y_COUNT		0xFFC01DB8	/* DMA Channel 14 Current Y Count Register */
    535. 

  535. 

  536. #define	DMA15_NEXT_DESC_PTR		0xFFC01DC0	/* DMA Channel 15 Next Descriptor Pointer Register */
    537. 

  537. #define	DMA15_START_ADDR		0xFFC01DC4	/* DMA Channel 15 Start	Address	Register */
    538. 

  538. #define	DMA15_CONFIG			0xFFC01DC8	/* DMA Channel 15 Configuration	Register */
    539. 

  539. #define	DMA15_X_COUNT			0xFFC01DD0	/* DMA Channel 15 X Count Register */
    540. 

  540. #define	DMA15_X_MODIFY			0xFFC01DD4	/* DMA Channel 15 X Modify Register */
    541. 

  541. #define	DMA15_Y_COUNT			0xFFC01DD8	/* DMA Channel 15 Y Count Register */
    542. 

  542. #define	DMA15_Y_MODIFY			0xFFC01DDC	/* DMA Channel 15 Y Modify Register */
    543. 

  543. #define	DMA15_CURR_DESC_PTR		0xFFC01DE0	/* DMA Channel 15 Current Descriptor Pointer Register */
    544. 

  544. #define	DMA15_CURR_ADDR			0xFFC01DE4	/* DMA Channel 15 Current Address Register */
    545. 

  545. #define	DMA15_IRQ_STATUS		0xFFC01DE8	/* DMA Channel 15 Interrupt/Status Register */
    546. 

  546. #define	DMA15_PERIPHERAL_MAP	0xFFC01DEC	/* DMA Channel 15 Peripheral Map Register */
    547. 

  547. #define	DMA15_CURR_X_COUNT		0xFFC01DF0	/* DMA Channel 15 Current X Count Register */
    548. 

  548. #define	DMA15_CURR_Y_COUNT		0xFFC01DF8	/* DMA Channel 15 Current Y Count Register */
    549. 

  549. 

  550. #define	DMA16_NEXT_DESC_PTR		0xFFC01E00	/* DMA Channel 16 Next Descriptor Pointer Register */
    551. 

  551. #define	DMA16_START_ADDR		0xFFC01E04	/* DMA Channel 16 Start	Address	Register */
    552. 

  552. #define	DMA16_CONFIG			0xFFC01E08	/* DMA Channel 16 Configuration	Register */
    553. 

  553. #define	DMA16_X_COUNT			0xFFC01E10	/* DMA Channel 16 X Count Register */
    554. 

  554. #define	DMA16_X_MODIFY			0xFFC01E14	/* DMA Channel 16 X Modify Register */
    555. 

  555. #define	DMA16_Y_COUNT			0xFFC01E18	/* DMA Channel 16 Y Count Register */
    556. 

  556. #define	DMA16_Y_MODIFY			0xFFC01E1C	/* DMA Channel 16 Y Modify Register */
    557. 

  557. #define	DMA16_CURR_DESC_PTR		0xFFC01E20	/* DMA Channel 16 Current Descriptor Pointer Register */
    558. 

  558. #define	DMA16_CURR_ADDR			0xFFC01E24	/* DMA Channel 16 Current Address Register */
    559. 

  559. #define	DMA16_IRQ_STATUS		0xFFC01E28	/* DMA Channel 16 Interrupt/Status Register */
    560. 

  560. #define	DMA16_PERIPHERAL_MAP	0xFFC01E2C	/* DMA Channel 16 Peripheral Map Register */
    561. 

  561. #define	DMA16_CURR_X_COUNT		0xFFC01E30	/* DMA Channel 16 Current X Count Register */
    562. 

  562. #define	DMA16_CURR_Y_COUNT		0xFFC01E38	/* DMA Channel 16 Current Y Count Register */
    563. 

  563. 

  564. #define	DMA17_NEXT_DESC_PTR		0xFFC01E40	/* DMA Channel 17 Next Descriptor Pointer Register */
    565. 

  565. #define	DMA17_START_ADDR		0xFFC01E44	/* DMA Channel 17 Start	Address	Register */
    566. 

  566. #define	DMA17_CONFIG			0xFFC01E48	/* DMA Channel 17 Configuration	Register */
    567. 

  567. #define	DMA17_X_COUNT			0xFFC01E50	/* DMA Channel 17 X Count Register */
    568. 

  568. #define	DMA17_X_MODIFY			0xFFC01E54	/* DMA Channel 17 X Modify Register */
    569. 

  569. #define	DMA17_Y_COUNT			0xFFC01E58	/* DMA Channel 17 Y Count Register */
    570. 

  570. #define	DMA17_Y_MODIFY			0xFFC01E5C	/* DMA Channel 17 Y Modify Register */
    571. 

  571. #define	DMA17_CURR_DESC_PTR		0xFFC01E60	/* DMA Channel 17 Current Descriptor Pointer Register */
    572. 

  572. #define	DMA17_CURR_ADDR			0xFFC01E64	/* DMA Channel 17 Current Address Register */
    573. 

  573. #define	DMA17_IRQ_STATUS		0xFFC01E68	/* DMA Channel 17 Interrupt/Status Register */
    574. 

  574. #define	DMA17_PERIPHERAL_MAP	0xFFC01E6C	/* DMA Channel 17 Peripheral Map Register */
    575. 

  575. #define	DMA17_CURR_X_COUNT		0xFFC01E70	/* DMA Channel 17 Current X Count Register */
    576. 

  576. #define	DMA17_CURR_Y_COUNT		0xFFC01E78	/* DMA Channel 17 Current Y Count Register */
    577. 

  577. 

  578. #define	DMA18_NEXT_DESC_PTR		0xFFC01E80	/* DMA Channel 18 Next Descriptor Pointer Register */
    579. 

  579. #define	DMA18_START_ADDR		0xFFC01E84	/* DMA Channel 18 Start	Address	Register */
    580. 

  580. #define	DMA18_CONFIG			0xFFC01E88	/* DMA Channel 18 Configuration	Register */
    581. 

  581. #define	DMA18_X_COUNT			0xFFC01E90	/* DMA Channel 18 X Count Register */
    582. 

  582. #define	DMA18_X_MODIFY			0xFFC01E94	/* DMA Channel 18 X Modify Register */
    583. 

  583. #define	DMA18_Y_COUNT			0xFFC01E98	/* DMA Channel 18 Y Count Register */
    584. 

  584. #define	DMA18_Y_MODIFY			0xFFC01E9C	/* DMA Channel 18 Y Modify Register */
    585. 

  585. #define	DMA18_CURR_DESC_PTR		0xFFC01EA0	/* DMA Channel 18 Current Descriptor Pointer Register */
    586. 

  586. #define	DMA18_CURR_ADDR			0xFFC01EA4	/* DMA Channel 18 Current Address Register */
    587. 

  587. #define	DMA18_IRQ_STATUS		0xFFC01EA8	/* DMA Channel 18 Interrupt/Status Register */
    588. 

  588. #define	DMA18_PERIPHERAL_MAP	0xFFC01EAC	/* DMA Channel 18 Peripheral Map Register */
    589. 

  589. #define	DMA18_CURR_X_COUNT		0xFFC01EB0	/* DMA Channel 18 Current X Count Register */
    590. 

  590. #define	DMA18_CURR_Y_COUNT		0xFFC01EB8	/* DMA Channel 18 Current Y Count Register */
    591. 

  591. 

  592. #define	DMA19_NEXT_DESC_PTR		0xFFC01EC0	/* DMA Channel 19 Next Descriptor Pointer Register */
    593. 

  593. #define	DMA19_START_ADDR		0xFFC01EC4	/* DMA Channel 19 Start	Address	Register */
    594. 

  594. #define	DMA19_CONFIG			0xFFC01EC8	/* DMA Channel 19 Configuration	Register */
    595. 

  595. #define	DMA19_X_COUNT			0xFFC01ED0	/* DMA Channel 19 X Count Register */
    596. 

  596. #define	DMA19_X_MODIFY			0xFFC01ED4	/* DMA Channel 19 X Modify Register */
    597. 

  597. #define	DMA19_Y_COUNT			0xFFC01ED8	/* DMA Channel 19 Y Count Register */
    598. 

  598. #define	DMA19_Y_MODIFY			0xFFC01EDC	/* DMA Channel 19 Y Modify Register */
    599. 

  599. #define	DMA19_CURR_DESC_PTR		0xFFC01EE0	/* DMA Channel 19 Current Descriptor Pointer Register */
    600. 

  600. #define	DMA19_CURR_ADDR			0xFFC01EE4	/* DMA Channel 19 Current Address Register */
    601. 

  601. #define	DMA19_IRQ_STATUS		0xFFC01EE8	/* DMA Channel 19 Interrupt/Status Register */
    602. 

  602. #define	DMA19_PERIPHERAL_MAP	0xFFC01EEC	/* DMA Channel 19 Peripheral Map Register */
    603. 

  603. #define	DMA19_CURR_X_COUNT		0xFFC01EF0	/* DMA Channel 19 Current X Count Register */
    604. 

  604. #define	DMA19_CURR_Y_COUNT		0xFFC01EF8	/* DMA Channel 19 Current Y Count Register */
    605. 

  605. 

  606. #define	MDMA_D2_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination	Next Descriptor	Pointer	Register */
    607. 

  607. #define	MDMA_D2_START_ADDR		0xFFC01F04	/* MemDMA1 Stream 0 Destination	Start Address Register */
    608. 

  608. #define	MDMA_D2_CONFIG			0xFFC01F08	/* MemDMA1 Stream 0 Destination	Configuration Register */
    609. 

  609. #define	MDMA_D2_X_COUNT		0xFFC01F10	/* MemDMA1 Stream 0 Destination	X Count	Register */
    610. 

  610. #define	MDMA_D2_X_MODIFY		0xFFC01F14	/* MemDMA1 Stream 0 Destination	X Modify Register */
    611. 

  611. #define	MDMA_D2_Y_COUNT		0xFFC01F18	/* MemDMA1 Stream 0 Destination	Y Count	Register */
    612. 

  612. #define	MDMA_D2_Y_MODIFY		0xFFC01F1C	/* MemDMA1 Stream 0 Destination	Y Modify Register */
    613. 

  613. #define	MDMA_D2_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Destination	Current	Descriptor Pointer Register */
    614. 

  614. #define	MDMA_D2_CURR_ADDR		0xFFC01F24	/* MemDMA1 Stream 0 Destination	Current	Address	Register */
    615. 

  615. #define	MDMA_D2_IRQ_STATUS		0xFFC01F28	/* MemDMA1 Stream 0 Destination	Interrupt/Status Register */
    616. 

  616. #define	MDMA_D2_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination	Peripheral Map Register */
    617. 

  617. #define	MDMA_D2_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Destination	Current	X Count	Register */
    618. 

  618. #define	MDMA_D2_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Destination	Current	Y Count	Register */
    619. 

  619. 

  620. #define	MDMA_S2_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next	Descriptor Pointer Register */
    621. 

  621. #define	MDMA_S2_START_ADDR		0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address Register */
    622. 

  622. #define	MDMA_S2_CONFIG			0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration Register */
    623. 

  623. #define	MDMA_S2_X_COUNT		0xFFC01F50	/* MemDMA1 Stream 0 Source X Count Register */
    624. 

  624. #define	MDMA_S2_X_MODIFY		0xFFC01F54	/* MemDMA1 Stream 0 Source X Modify Register */
    625. 

  625. #define	MDMA_S2_Y_COUNT		0xFFC01F58	/* MemDMA1 Stream 0 Source Y Count Register */
    626. 

  626. #define	MDMA_S2_Y_MODIFY		0xFFC01F5C	/* MemDMA1 Stream 0 Source Y Modify Register */
    627. 

  627. #define	MDMA_S2_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
    628. 

  628. #define	MDMA_S2_CURR_ADDR		0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address Register */
    629. 

  629. #define	MDMA_S2_IRQ_STATUS		0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status Register */
    630. 

  630. #define	MDMA_S2_PERIPHERAL_MAP	0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map Register */
    631. 

  631. #define	MDMA_S2_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current X Count Register */
    632. 

  632. #define	MDMA_S2_CURR_Y_COUNT	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Y Count Register */
    633. 

  633. 

  634. #define	MDMA_D3_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination	Next Descriptor	Pointer	Register */
    635. 

  635. #define	MDMA_D3_START_ADDR		0xFFC01F84	/* MemDMA1 Stream 1 Destination	Start Address Register */
    636. 

  636. #define	MDMA_D3_CONFIG			0xFFC01F88	/* MemDMA1 Stream 1 Destination	Configuration Register */
    637. 

  637. #define	MDMA_D3_X_COUNT		0xFFC01F90	/* MemDMA1 Stream 1 Destination	X Count	Register */
    638. 

  638. #define	MDMA_D3_X_MODIFY		0xFFC01F94	/* MemDMA1 Stream 1 Destination	X Modify Register */
    639. 

  639. #define	MDMA_D3_Y_COUNT		0xFFC01F98	/* MemDMA1 Stream 1 Destination	Y Count	Register */
    640. 

  640. #define	MDMA_D3_Y_MODIFY		0xFFC01F9C	/* MemDMA1 Stream 1 Destination	Y Modify Register */
    641. 

  641. #define	MDMA_D3_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Destination	Current	Descriptor Pointer Register */
    642. 

  642. #define	MDMA_D3_CURR_ADDR		0xFFC01FA4	/* MemDMA1 Stream 1 Destination	Current	Address	Register */
    643. 

  643. #define	MDMA_D3_IRQ_STATUS		0xFFC01FA8	/* MemDMA1 Stream 1 Destination	Interrupt/Status Register */
    644. 

  644. #define	MDMA_D3_PERIPHERAL_MAP	0xFFC01FAC	/* MemDMA1 Stream 1 Destination	Peripheral Map Register */
    645. 

  645. #define	MDMA_D3_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Destination	Current	X Count	Register */
    646. 

  646. #define	MDMA_D3_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Destination	Current	Y Count	Register */
    647. 

  647. 

  648. #define	MDMA_S3_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next	Descriptor Pointer Register */
    649. 

  649. #define	MDMA_S3_START_ADDR		0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address Register */
    650. 

  650. #define	MDMA_S3_CONFIG			0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration Register */
    651. 

  651. #define	MDMA_S3_X_COUNT		0xFFC01FD0	/* MemDMA1 Stream 1 Source X Count Register */
    652. 

  652. #define	MDMA_S3_X_MODIFY		0xFFC01FD4	/* MemDMA1 Stream 1 Source X Modify Register */
    653. 

  653. #define	MDMA_S3_Y_COUNT		0xFFC01FD8	/* MemDMA1 Stream 1 Source Y Count Register */
    654. 

  654. #define	MDMA_S3_Y_MODIFY		0xFFC01FDC	/* MemDMA1 Stream 1 Source Y Modify Register */
    655. 

  655. #define	MDMA_S3_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
    656. 

  656. #define	MDMA_S3_CURR_ADDR		0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address Register */
    657. 

  657. #define	MDMA_S3_IRQ_STATUS		0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status Register */
    658. 

  658. #define	MDMA_S3_PERIPHERAL_MAP	0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map Register */
    659. 

  659. #define	MDMA_S3_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current X Count Register */
    660. 

  660. #define	MDMA_S3_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Y Count Register */
    661. 

  661. 

  662. 

  663. /* UART1 Controller		(0xFFC02000 - 0xFFC020FF)	 */
    664. 

  664. #define	UART1_THR			0xFFC02000	/* Transmit Holding register */
    665. 

  665. #define	UART1_RBR			0xFFC02000	/* Receive Buffer register */
    666. 

  666. #define	UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte) */
    667. 

  667. #define	UART1_IER			0xFFC02004	/* Interrupt Enable Register */
    668. 

  668. #define	UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte) */
    669. 

  669. #define	UART1_IIR			0xFFC02008	/* Interrupt Identification Register */
    670. 

  670. #define	UART1_LCR			0xFFC0200C	/* Line	Control	Register */
    671. 

  671. #define	UART1_MCR			0xFFC02010	/* Modem Control Register */
    672. 

  672. #define	UART1_LSR			0xFFC02014	/* Line	Status Register */
    673. 

  673. #define	UART1_SCR			0xFFC0201C	/* SCR Scratch Register */
    674. 

  674. #define	UART1_GCTL			0xFFC02024	/* Global Control Register */
    675. 

  675. 

  676. 

  677. /* UART2 Controller		(0xFFC02100 - 0xFFC021FF)	 */
    678. 

  678. #define	UART2_THR			0xFFC02100	/* Transmit Holding register */
    679. 

  679. #define	UART2_RBR			0xFFC02100	/* Receive Buffer register */
    680. 

  680. #define	UART2_DLL			0xFFC02100	/* Divisor Latch (Low-Byte) */
    681. 

  681. #define	UART2_IER			0xFFC02104	/* Interrupt Enable Register */
    682. 

  682. #define	UART2_DLH			0xFFC02104	/* Divisor Latch (High-Byte) */
    683. 

  683. #define	UART2_IIR			0xFFC02108	/* Interrupt Identification Register */
    684. 

  684. #define	UART2_LCR			0xFFC0210C	/* Line	Control	Register */
    685. 

  685. #define	UART2_MCR			0xFFC02110	/* Modem Control Register */
    686. 

  686. #define	UART2_LSR			0xFFC02114	/* Line	Status Register */
    687. 

  687. #define	UART2_SCR			0xFFC0211C	/* SCR Scratch Register */
    688. 

  688. #define	UART2_GCTL			0xFFC02124	/* Global Control Register */
    689. 

  689. 

  690. 

  691. /* Two-Wire Interface 1	(0xFFC02200 - 0xFFC022FF)			 */
    692. 

  692. #define	TWI1_CLKDIV			0xFFC02200	/* Serial Clock	Divider	Register */
    693. 

  693. #define	TWI1_CONTROL		0xFFC02204	/* TWI1	Master Internal	Time Reference Register */
    694. 

  694. #define	TWI1_SLAVE_CTL		0xFFC02208	/* Slave Mode Control Register */
    695. 

  695. #define	TWI1_SLAVE_STAT		0xFFC0220C	/* Slave Mode Status Register */
    696. 

  696. #define	TWI1_SLAVE_ADDR		0xFFC02210	/* Slave Mode Address Register */
    697. 

  697. #define	TWI1_MASTER_CTL	0xFFC02214	/* Master Mode Control Register */
    698. 

  698. #define	TWI1_MASTER_STAT	0xFFC02218	/* Master Mode Status Register */
    699. 

  699. #define	TWI1_MASTER_ADDR	0xFFC0221C	/* Master Mode Address Register */
    700. 

  700. #define	TWI1_INT_STAT		0xFFC02220	/* TWI1	Master Interrupt Register */
    701. 

  701. #define	TWI1_INT_MASK		0xFFC02224	/* TWI1	Master Interrupt Mask Register */
    702. 

  702. #define	TWI1_FIFO_CTL		0xFFC02228	/* FIFO	Control	Register */
    703. 

  703. #define	TWI1_FIFO_STAT		0xFFC0222C	/* FIFO	Status Register */
    704. 

  704. #define	TWI1_XMT_DATA8		0xFFC02280	/* FIFO	Transmit Data Single Byte Register */
    705. 

  705. #define	TWI1_XMT_DATA16		0xFFC02284	/* FIFO	Transmit Data Double Byte Register */
    706. 

  706. #define	TWI1_RCV_DATA8		0xFFC02288	/* FIFO	Receive	Data Single Byte Register */
    707. 

  707. #define	TWI1_RCV_DATA16		0xFFC0228C	/* FIFO	Receive	Data Double Byte Register */
    708. 

  708. #define TWI1_REGBASE		TWI1_CLKDIV
    709. 

  709. 

  710. 

  711. /* the following are for backwards compatibility */
    712. 

  712. #define	TWI1_PRESCALE	  TWI1_CONTROL
    713. 

  713. #define	TWI1_INT_SRC	  TWI1_INT_STAT
    714. 

  714. #define	TWI1_INT_ENABLE	  TWI1_INT_MASK
    715. 

  715. 

  716. 

  717. /* SPI1	Controller		(0xFFC02300 - 0xFFC023FF)	 */
    718. 

  718. #define	SPI1_CTL			0xFFC02300  /* SPI1 Control Register */
    719. 

  719. #define	SPI1_FLG			0xFFC02304  /* SPI1 Flag register */
    720. 

  720. #define	SPI1_STAT			0xFFC02308  /* SPI1 Status register */
    721. 

  721. #define	SPI1_TDBR			0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
    722. 

  722. #define	SPI1_RDBR			0xFFC02310  /* SPI1 Receive Data Buffer	Register */
    723. 

  723. #define	SPI1_BAUD			0xFFC02314  /* SPI1 Baud rate Register */
    724. 

  724. #define	SPI1_SHADOW			0xFFC02318  /* SPI1_RDBR Shadow	Register */
    725. 

  725. #define SPI1_REGBASE			SPI1_CTL
    726. 

  726. 

  727. /* SPI2	Controller		(0xFFC02400 - 0xFFC024FF)	 */
    728. 

  728. #define	SPI2_CTL			0xFFC02400  /* SPI2 Control Register */
    729. 

  729. #define	SPI2_FLG			0xFFC02404  /* SPI2 Flag register */
    730. 

  730. #define	SPI2_STAT			0xFFC02408  /* SPI2 Status register */
    731. 

  731. #define	SPI2_TDBR			0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
    732. 

  732. #define	SPI2_RDBR			0xFFC02410  /* SPI2 Receive Data Buffer	Register */
    733. 

  733. #define	SPI2_BAUD			0xFFC02414  /* SPI2 Baud rate Register */
    734. 

  734. #define	SPI2_SHADOW			0xFFC02418  /* SPI2_RDBR Shadow	Register */
    735. 

  735. #define SPI2_REGBASE			SPI2_CTL
    736. 

  736. 

  737. /* SPORT2 Controller		(0xFFC02500 - 0xFFC025FF)			 */
    738. 

  738. #define	SPORT2_TCR1			0xFFC02500	/* SPORT2 Transmit Configuration 1 Register */
    739. 

  739. #define	SPORT2_TCR2			0xFFC02504	/* SPORT2 Transmit Configuration 2 Register */
    740. 

  740. #define	SPORT2_TCLKDIV		0xFFC02508	/* SPORT2 Transmit Clock Divider */
    741. 

  741. #define	SPORT2_TFSDIV		0xFFC0250C	/* SPORT2 Transmit Frame Sync Divider */
    742. 

  742. #define	SPORT2_TX			0xFFC02510	/* SPORT2 TX Data Register */
    743. 

  743. #define	SPORT2_RX			0xFFC02518	/* SPORT2 RX Data Register */
    744. 

  744. #define	SPORT2_RCR1			0xFFC02520	/* SPORT2 Transmit Configuration 1 Register */
    745. 

  745. #define	SPORT2_RCR2			0xFFC02524	/* SPORT2 Transmit Configuration 2 Register */
    746. 

  746. #define	SPORT2_RCLKDIV		0xFFC02528	/* SPORT2 Receive Clock	Divider */
    747. 

  747. #define	SPORT2_RFSDIV		0xFFC0252C	/* SPORT2 Receive Frame	Sync Divider */
    748. 

  748. #define	SPORT2_STAT			0xFFC02530	/* SPORT2 Status Register */
    749. 

  749. #define	SPORT2_CHNL			0xFFC02534	/* SPORT2 Current Channel Register */
    750. 

  750. #define	SPORT2_MCMC1		0xFFC02538	/* SPORT2 Multi-Channel	Configuration Register 1 */
    751. 

  751. #define	SPORT2_MCMC2		0xFFC0253C	/* SPORT2 Multi-Channel	Configuration Register 2 */
    752. 

  752. #define	SPORT2_MTCS0		0xFFC02540	/* SPORT2 Multi-Channel	Transmit Select	Register 0 */
    753. 

  753. #define	SPORT2_MTCS1		0xFFC02544	/* SPORT2 Multi-Channel	Transmit Select	Register 1 */
    754. 

  754. #define	SPORT2_MTCS2		0xFFC02548	/* SPORT2 Multi-Channel	Transmit Select	Register 2 */
    755. 

  755. #define	SPORT2_MTCS3		0xFFC0254C	/* SPORT2 Multi-Channel	Transmit Select	Register 3 */
    756. 

  756. #define	SPORT2_MRCS0		0xFFC02550	/* SPORT2 Multi-Channel	Receive	Select Register	0 */
    757. 

  757. #define	SPORT2_MRCS1		0xFFC02554	/* SPORT2 Multi-Channel	Receive	Select Register	1 */
    758. 

  758. #define	SPORT2_MRCS2		0xFFC02558	/* SPORT2 Multi-Channel	Receive	Select Register	2 */
    759. 

  759. #define	SPORT2_MRCS3		0xFFC0255C	/* SPORT2 Multi-Channel	Receive	Select Register	3 */
    760. 

  760. 

  761. 

  762. /* SPORT3 Controller		(0xFFC02600 - 0xFFC026FF)			 */
    763. 

  763. #define	SPORT3_TCR1			0xFFC02600	/* SPORT3 Transmit Configuration 1 Register */
    764. 

  764. #define	SPORT3_TCR2			0xFFC02604	/* SPORT3 Transmit Configuration 2 Register */
    765. 

  765. #define	SPORT3_TCLKDIV		0xFFC02608	/* SPORT3 Transmit Clock Divider */
    766. 

  766. #define	SPORT3_TFSDIV		0xFFC0260C	/* SPORT3 Transmit Frame Sync Divider */
    767. 

  767. #define	SPORT3_TX			0xFFC02610	/* SPORT3 TX Data Register */
    768. 

  768. #define	SPORT3_RX			0xFFC02618	/* SPORT3 RX Data Register */
    769. 

  769. #define	SPORT3_RCR1			0xFFC02620	/* SPORT3 Transmit Configuration 1 Register */
    770. 

  770. #define	SPORT3_RCR2			0xFFC02624	/* SPORT3 Transmit Configuration 2 Register */
    771. 

  771. #define	SPORT3_RCLKDIV		0xFFC02628	/* SPORT3 Receive Clock	Divider */
    772. 

  772. #define	SPORT3_RFSDIV		0xFFC0262C	/* SPORT3 Receive Frame	Sync Divider */
    773. 

  773. #define	SPORT3_STAT			0xFFC02630	/* SPORT3 Status Register */
    774. 

  774. #define	SPORT3_CHNL			0xFFC02634	/* SPORT3 Current Channel Register */
    775. 

  775. #define	SPORT3_MCMC1		0xFFC02638	/* SPORT3 Multi-Channel	Configuration Register 1 */
    776. 

  776. #define	SPORT3_MCMC2		0xFFC0263C	/* SPORT3 Multi-Channel	Configuration Register 2 */
    777. 

  777. #define	SPORT3_MTCS0		0xFFC02640	/* SPORT3 Multi-Channel	Transmit Select	Register 0 */
    778. 

  778. #define	SPORT3_MTCS1		0xFFC02644	/* SPORT3 Multi-Channel	Transmit Select	Register 1 */
    779. 

  779. #define	SPORT3_MTCS2		0xFFC02648	/* SPORT3 Multi-Channel	Transmit Select	Register 2 */
    780. 

  780. #define	SPORT3_MTCS3		0xFFC0264C	/* SPORT3 Multi-Channel	Transmit Select	Register 3 */
    781. 

  781. #define	SPORT3_MRCS0		0xFFC02650	/* SPORT3 Multi-Channel	Receive	Select Register	0 */
    782. 

  782. #define	SPORT3_MRCS1		0xFFC02654	/* SPORT3 Multi-Channel	Receive	Select Register	1 */
    783. 

  783. #define	SPORT3_MRCS2		0xFFC02658	/* SPORT3 Multi-Channel	Receive	Select Register	2 */
    784. 

  784. #define	SPORT3_MRCS3		0xFFC0265C	/* SPORT3 Multi-Channel	Receive	Select Register	3 */
    785. 

  785. 

  786. 

  787. /* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)				 */
    788. 

  788. /* For Mailboxes 0-15											 */
    789. 

  789. #define	CAN_MC1				0xFFC02A00	/* Mailbox config reg 1	 */
    790. 

  790. #define	CAN_MD1				0xFFC02A04	/* Mailbox direction reg 1 */
    791. 

  791. #define	CAN_TRS1			0xFFC02A08	/* Transmit Request Set	reg 1 */
    792. 

  792. #define	CAN_TRR1			0xFFC02A0C	/* Transmit Request Reset reg 1 */
    793. 

  793. #define	CAN_TA1				0xFFC02A10	/* Transmit Acknowledge	reg 1 */
    794. 

  794. #define	CAN_AA1				0xFFC02A14	/* Transmit Abort Acknowledge reg 1 */
    795. 

  795. #define	CAN_RMP1			0xFFC02A18	/* Receive Message Pending reg 1 */
    796. 

  796. #define	CAN_RML1			0xFFC02A1C	/* Receive Message Lost	reg 1 */
    797. 

  797. #define	CAN_MBTIF1			0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1 */
    798. 

  798. #define	CAN_MBRIF1			0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1 */
    799. 

  799. #define	CAN_MBIM1			0xFFC02A28	/* Mailbox Interrupt Mask reg 1 */
    800. 

  800. #define	CAN_RFH1			0xFFC02A2C	/* Remote Frame	Handling reg 1 */
    801. 

  801. #define	CAN_OPSS1			0xFFC02A30	/* Overwrite Protection	Single Shot Xmission reg 1 */
    802. 

  802. 

  803. /* For Mailboxes 16-31											 */
    804. 

  804. #define	CAN_MC2				0xFFC02A40	/* Mailbox config reg 2	 */
    805. 

  805. #define	CAN_MD2				0xFFC02A44	/* Mailbox direction reg 2 */
    806. 

  806. #define	CAN_TRS2			0xFFC02A48	/* Transmit Request Set	reg 2 */
    807. 

  807. #define	CAN_TRR2			0xFFC02A4C	/* Transmit Request Reset reg 2 */
    808. 

  808. #define	CAN_TA2				0xFFC02A50	/* Transmit Acknowledge	reg 2 */
    809. 

  809. #define	CAN_AA2				0xFFC02A54	/* Transmit Abort Acknowledge reg 2 */
    810. 

  810. #define	CAN_RMP2			0xFFC02A58	/* Receive Message Pending reg 2 */
    811. 

  811. #define	CAN_RML2			0xFFC02A5C	/* Receive Message Lost	reg 2 */
    812. 

  812. #define	CAN_MBTIF2			0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2 */
    813. 

  813. #define	CAN_MBRIF2			0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2 */
    814. 

  814. #define	CAN_MBIM2			0xFFC02A68	/* Mailbox Interrupt Mask reg 2 */
    815. 

  815. #define	CAN_RFH2			0xFFC02A6C	/* Remote Frame	Handling reg 2 */
    816. 

  816. #define	CAN_OPSS2			0xFFC02A70	/* Overwrite Protection	Single Shot Xmission reg 2 */
    817. 

  817. 

  818. #define	CAN_CLOCK			0xFFC02A80	/* Bit Timing Configuration register 0 */
    819. 

  819. #define	CAN_TIMING			0xFFC02A84	/* Bit Timing Configuration register 1 */
    820. 

  820. 

  821. #define	CAN_DEBUG			0xFFC02A88	/* Debug Register		 */
    822. 

  822. /* the following is for	backwards compatibility */
    823. 

  823. #define	CAN_CNF		 CAN_DEBUG
    824. 

  824. 

  825. #define	CAN_STATUS			0xFFC02A8C	/* Global Status Register */
    826. 

  826. #define	CAN_CEC				0xFFC02A90	/* Error Counter Register */
    827. 

  827. #define	CAN_GIS				0xFFC02A94	/* Global Interrupt Status Register */
    828. 

  828. #define	CAN_GIM				0xFFC02A98	/* Global Interrupt Mask Register */
    829. 

  829. #define	CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register */
    830. 

  830. #define	CAN_CONTROL			0xFFC02AA0	/* Master Control Register */
    831. 

  831. #define	CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register */
    832. 

  832. #define	CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature */
    833. 

  833. #define	CAN_EWR				0xFFC02AB0	/* Programmable	Warning	Level */
    834. 

  834. #define	CAN_ESR				0xFFC02AB4	/* Error Status	Register */
    835. 

  835. #define	CAN_UCCNT			0xFFC02AC4	/* Universal Counter	 */
    836. 

  836. #define	CAN_UCRC			0xFFC02AC8	/* Universal Counter Reload/Capture Register */
    837. 

  837. #define	CAN_UCCNF			0xFFC02ACC	/* Universal Counter Configuration Register */
    838. 

  838. 

  839. /* Mailbox Acceptance Masks					 */
    840. 

  840. #define	CAN_AM00L			0xFFC02B00	/* Mailbox 0 Low Acceptance Mask */
    841. 

  841. #define	CAN_AM00H			0xFFC02B04	/* Mailbox 0 High Acceptance Mask */
    842. 

  842. #define	CAN_AM01L			0xFFC02B08	/* Mailbox 1 Low Acceptance Mask */
    843. 

  843. #define	CAN_AM01H			0xFFC02B0C	/* Mailbox 1 High Acceptance Mask */
    844. 

  844. #define	CAN_AM02L			0xFFC02B10	/* Mailbox 2 Low Acceptance Mask */
    845. 

  845. #define	CAN_AM02H			0xFFC02B14	/* Mailbox 2 High Acceptance Mask */
    846. 

  846. #define	CAN_AM03L			0xFFC02B18	/* Mailbox 3 Low Acceptance Mask */
    847. 

  847. #define	CAN_AM03H			0xFFC02B1C	/* Mailbox 3 High Acceptance Mask */
    848. 

  848. #define	CAN_AM04L			0xFFC02B20	/* Mailbox 4 Low Acceptance Mask */
    849. 

  849. #define	CAN_AM04H			0xFFC02B24	/* Mailbox 4 High Acceptance Mask */
    850. 

  850. #define	CAN_AM05L			0xFFC02B28	/* Mailbox 5 Low Acceptance Mask */
    851. 

  851. #define	CAN_AM05H			0xFFC02B2C	/* Mailbox 5 High Acceptance Mask */
    852. 

  852. #define	CAN_AM06L			0xFFC02B30	/* Mailbox 6 Low Acceptance Mask */
    853. 

  853. #define	CAN_AM06H			0xFFC02B34	/* Mailbox 6 High Acceptance Mask */
    854. 

  854. #define	CAN_AM07L			0xFFC02B38	/* Mailbox 7 Low Acceptance Mask */
    855. 

  855. #define	CAN_AM07H			0xFFC02B3C	/* Mailbox 7 High Acceptance Mask */
    856. 

  856. #define	CAN_AM08L			0xFFC02B40	/* Mailbox 8 Low Acceptance Mask */
    857. 

  857. #define	CAN_AM08H			0xFFC02B44	/* Mailbox 8 High Acceptance Mask */
    858. 

  858. #define	CAN_AM09L			0xFFC02B48	/* Mailbox 9 Low Acceptance Mask */
    859. 

  859. #define	CAN_AM09H			0xFFC02B4C	/* Mailbox 9 High Acceptance Mask */
    860. 

  860. #define	CAN_AM10L			0xFFC02B50	/* Mailbox 10 Low Acceptance Mask */
    861. 

  861. #define	CAN_AM10H			0xFFC02B54	/* Mailbox 10 High Acceptance Mask */
    862. 

  862. #define	CAN_AM11L			0xFFC02B58	/* Mailbox 11 Low Acceptance Mask */
    863. 

  863. #define	CAN_AM11H			0xFFC02B5C	/* Mailbox 11 High Acceptance Mask */
    864. 

  864. #define	CAN_AM12L			0xFFC02B60	/* Mailbox 12 Low Acceptance Mask */
    865. 

  865. #define	CAN_AM12H			0xFFC02B64	/* Mailbox 12 High Acceptance Mask */
    866. 

  866. #define	CAN_AM13L			0xFFC02B68	/* Mailbox 13 Low Acceptance Mask */
    867. 

  867. #define	CAN_AM13H			0xFFC02B6C	/* Mailbox 13 High Acceptance Mask */
    868. 

  868. #define	CAN_AM14L			0xFFC02B70	/* Mailbox 14 Low Acceptance Mask */
    869. 

  869. #define	CAN_AM14H			0xFFC02B74	/* Mailbox 14 High Acceptance Mask */
    870. 

  870. #define	CAN_AM15L			0xFFC02B78	/* Mailbox 15 Low Acceptance Mask */
    871. 

  871. #define	CAN_AM15H			0xFFC02B7C	/* Mailbox 15 High Acceptance Mask */
    872. 

  872. 

  873. #define	CAN_AM16L			0xFFC02B80	/* Mailbox 16 Low Acceptance Mask */
    874. 

  874. #define	CAN_AM16H			0xFFC02B84	/* Mailbox 16 High Acceptance Mask */
    875. 

  875. #define	CAN_AM17L			0xFFC02B88	/* Mailbox 17 Low Acceptance Mask */
    876. 

  876. #define	CAN_AM17H			0xFFC02B8C	/* Mailbox 17 High Acceptance Mask */
    877. 

  877. #define	CAN_AM18L			0xFFC02B90	/* Mailbox 18 Low Acceptance Mask */
    878. 

  878. #define	CAN_AM18H			0xFFC02B94	/* Mailbox 18 High Acceptance Mask */
    879. 

  879. #define	CAN_AM19L			0xFFC02B98	/* Mailbox 19 Low Acceptance Mask */
    880. 

  880. #define	CAN_AM19H			0xFFC02B9C	/* Mailbox 19 High Acceptance Mask */
    881. 

  881. #define	CAN_AM20L			0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask */
    882. 

  882. #define	CAN_AM20H			0xFFC02BA4	/* Mailbox 20 High Acceptance Mask */
    883. 

  883. #define	CAN_AM21L			0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask */
    884. 

  884. #define	CAN_AM21H			0xFFC02BAC	/* Mailbox 21 High Acceptance Mask */
    885. 

  885. #define	CAN_AM22L			0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask */
    886. 

  886. #define	CAN_AM22H			0xFFC02BB4	/* Mailbox 22 High Acceptance Mask */
    887. 

  887. #define	CAN_AM23L			0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask */
    888. 

  888. #define	CAN_AM23H			0xFFC02BBC	/* Mailbox 23 High Acceptance Mask */
    889. 

  889. #define	CAN_AM24L			0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask */
    890. 

  890. #define	CAN_AM24H			0xFFC02BC4	/* Mailbox 24 High Acceptance Mask */
    891. 

  891. #define	CAN_AM25L			0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask */
    892. 

  892. #define	CAN_AM25H			0xFFC02BCC	/* Mailbox 25 High Acceptance Mask */
    893. 

  893. #define	CAN_AM26L			0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask */
    894. 

  894. #define	CAN_AM26H			0xFFC02BD4	/* Mailbox 26 High Acceptance Mask */
    895. 

  895. #define	CAN_AM27L			0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask */
    896. 

  896. #define	CAN_AM27H			0xFFC02BDC	/* Mailbox 27 High Acceptance Mask */
    897. 

  897. #define	CAN_AM28L			0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask */
    898. 

  898. #define	CAN_AM28H			0xFFC02BE4	/* Mailbox 28 High Acceptance Mask */
    899. 

  899. #define	CAN_AM29L			0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask */
    900. 

  900. #define	CAN_AM29H			0xFFC02BEC	/* Mailbox 29 High Acceptance Mask */
    901. 

  901. #define	CAN_AM30L			0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask */
    902. 

  902. #define	CAN_AM30H			0xFFC02BF4	/* Mailbox 30 High Acceptance Mask */
    903. 

  903. #define	CAN_AM31L			0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask */
    904. 

  904. #define	CAN_AM31H			0xFFC02BFC	/* Mailbox 31 High Acceptance Mask */
    905. 

  905. 

  906. /* CAN Acceptance Mask Macros */
    907. 

  907. #define	CAN_AM_L(x)			(CAN_AM00L+((x)*0x8))
    908. 

  908. #define	CAN_AM_H(x)			(CAN_AM00H+((x)*0x8))
    909. 

  909. 

  910. /* Mailbox Registers									 */
    911. 

  911. #define	CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0]	Register */
    912. 

  912. #define	CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register */
    913. 

  913. #define	CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register */
    914. 

  914. #define	CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register */
    915. 

  915. #define	CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register */
    916. 

  916. #define	CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp	Value Register */
    917. 

  917. #define	CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier	Low Register */
    918. 

  918. #define	CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier	High Register */
    919. 

  919. 

  920. #define	CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0]	Register */
    921. 

  921. #define	CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register */
    922. 

  922. #define	CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register */
    923. 

  923. #define	CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register */
    924. 

  924. #define	CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register */
    925. 

  925. #define	CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp	Value Register */
    926. 

  926. #define	CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier	Low Register */
    927. 

  927. #define	CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier	High Register */
    928. 

  928. 

  929. #define	CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0]	Register */
    930. 

  930. #define	CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register */
    931. 

  931. #define	CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register */
    932. 

  932. #define	CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register */
    933. 

  933. #define	CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register */
    934. 

  934. #define	CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp	Value Register */
    935. 

  935. #define	CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier	Low Register */
    936. 

  936. #define	CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier	High Register */
    937. 

  937. 

  938. #define	CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0]	Register */
    939. 

  939. #define	CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register */
    940. 

  940. #define	CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register */
    941. 

  941. #define	CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register */
    942. 

  942. #define	CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register */
    943. 

  943. #define	CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp	Value Register */
    944. 

  944. #define	CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier	Low Register */
    945. 

  945. #define	CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier	High Register */
    946. 

  946. 

  947. #define	CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0]	Register */
    948. 

  948. #define	CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register */
    949. 

  949. #define	CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register */
    950. 

  950. #define	CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register */
    951.