aiot/waterHeterogeneousDataSynchronization/monitoringDataProcessing/connectTheSignalSlot.h

/*
 * Blackfin core register bit & address definitions
 *
 * Copyright 2005-2008 Analog Devices Inc.
 *
 * Licensed under the Clear BSD license or GPL-2 (or later).
 */

#ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H

#include <mach/anomaly.h>

#define MK_BMSK_(x) (1<<x)
#define BFIN_DEPOSIT(mask, x)	(((x) << __ffs(mask)) & (mask))
#define BFIN_EXTRACT(mask, x)	(((x) & (mask)) >> __ffs(mask))

#ifndef __ASSEMBLY__

#include <linux/types.h>

#if ANOMALY_05000198
# define NOP_PAD_ANOMALY_05000198 "nop;"
#else
# define NOP_PAD_ANOMALY_05000198
#endif

#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
	u32 __v; \
	__asm__ __volatile__( \
		NOP_PAD_ANOMALY_05000198 \
		"%0 = " #asm_size "[%1]" #asm_ext ";" \
		: "=d" (__v) \
		: "a" (addr) \
	); \
	__v; })
#define _bfin_writeX(addr, val, size, asm_size) \
	__asm__ __volatile__( \
		NOP_PAD_ANOMALY_05000198 \
		#asm_size "[%0] = %1;" \
		: \
		: "a" (addr), "d" ((u##size)(val)) \
		: "memory" \
	)

#define bfin_read8(addr)  _bfin_readX(addr,  8, b, (z))
#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
#define bfin_read32(addr) _bfin_readX(addr, 32,  ,    )
#define bfin_write8(addr, val)  _bfin_writeX(addr, val,  8, b)
#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32,  )

#define bfin_read(addr) \
({ \
	sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
	sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
	sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
	({ BUG(); 0; }); \
})
#define bfin_write(addr, val) \
do { \
	switch (sizeof(*(addr))) { \
	case 1: bfin_write8(addr, val);  break; \
	case 2: bfin_write16(addr, val); break; \
	case 4: bfin_write32(addr, val); break; \
	default: BUG(); \
	} \
} while (0)

#define bfin_write_or(addr, bits) \
do { \
	typeof(addr) __addr = (addr); \
	bfin_write(__addr, bfin_read(__addr) | (bits)); \
} while (0)

#define bfin_write_and(addr, bits) \
do { \
	typeof(addr) __addr = (addr); \
	bfin_write(__addr, bfin_read(__addr) & (bits)); \
} while (0)

#endif /* __ASSEMBLY__ */

/**************************************************
 * System Register Bits
 **************************************************/

/**************************************************
 * ASTAT register
 **************************************************/

/* definitions of ASTAT bit positions*/

/*Result of last ALU0 or shifter operation is zero*/
#define ASTAT_AZ_P         0x00000000
/*Result of last ALU0 or shifter operation is negative*/
#define ASTAT_AN_P         0x00000001
/*Condition Code, used for holding comparison results*/
#define ASTAT_CC_P         0x00000005
/*Quotient Bit*/
#define ASTAT_AQ_P         0x00000006
/*Rounding mode, set for biased, clear for unbiased*/
#define ASTAT_RND_MOD_P    0x00000008
/*Result of last ALU0 operation generated a carry*/
#define ASTAT_AC0_P        0x0000000C
/*Result of last ALU0 operation generated a carry*/
#define ASTAT_AC0_COPY_P   0x00000002
/*Result of last ALU1 operation generated a carry*/
#define ASTAT_AC1_P        0x0000000D
/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
#define ASTAT_AV0_P        0x00000010
/*Sticky version of ASTAT_AV0 */
#define ASTAT_AV0S_P       0x00000011
/*Result of last MAC1 operation overflowed, sticky for MAC*/
#define ASTAT_AV1_P        0x00000012
/*Sticky version of ASTAT_AV1 */
#define ASTAT_AV1S_P       0x00000013
/*Result of last ALU0 or MAC0 operation overflowed*/
#define ASTAT_V_P          0x00000018
/*Result of last ALU0 or MAC0 operation overflowed*/
#define ASTAT_V_COPY_P     0x00000003
/*Sticky version of ASTAT_V*/
#define ASTAT_VS_P         0x00000019

/* Masks */

/*Result of last ALU0 or shifter operation is zero*/
#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)
/*Result of last ALU0 or shifter operation is negative*/
#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)
/*Result of last ALU0 operation generated a carry*/
#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)
/*Result of last ALU0 operation generated a carry*/
#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)
/*Result of last ALU0 operation generated a carry*/
#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)
/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)
/*Result of last MAC1 operation overflowed, sticky for MAC*/
#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)
/*Condition Code, used for holding comparison results*/
#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)
/*Quotient Bit*/
#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)
/*Rounding mode, set for biased, clear for unbiased*/
#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)
/*Overflow Bit*/
#define ASTAT_V            MK_BMSK_(ASTAT_V_P)
/*Overflow Bit*/
#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)

/**************************************************
 *   SEQSTAT register
 **************************************************/

/* Bit Positions  */
#define SEQSTAT_EXCAUSE0_P      0x00000000	/* Last exception cause bit 0 */
#define SEQSTAT_EXCAUSE1_P      0x00000001	/* Last exception cause bit 1 */
#define SEQSTAT_EXCAUSE2_P      0x00000002	/* Last exception cause bit 2 */
#define SEQSTAT_EXCAUSE3_P      0x00000003	/* Last exception cause bit 3 */
#define SEQSTAT_EXCAUSE4_P      0x00000004	/* Last exception cause bit 4 */
#define SEQSTAT_EXCAUSE5_P      0x00000005	/* Last exception cause bit 5 */
#define SEQSTAT_IDLE_REQ_P      0x0000000C	/* Pending idle mode request,
						 * set by IDLE instruction.
						 */
#define SEQSTAT_SFTRESET_P      0x0000000D	/* Indicates whether the last
						 * reset was a software reset
						 * (=1)
						 */
#define SEQSTAT_HWERRCAUSE0_P   0x0000000E	/* Last hw error cause bit 0 */
#define SEQSTAT_HWERRCAUSE1_P   0x0000000F	/* Last hw error cause bit 1 */
#define SEQSTAT_HWERRCAUSE2_P   0x00000010	/* Last hw error cause bit 2 */
#define SEQSTAT_HWERRCAUSE3_P   0x00000011	/* Last hw error cause bit 3 */
#define SEQSTAT_HWERRCAUSE4_P   0x00000012	/* Last hw error cause bit 4 */
/* Masks */
/* Exception cause */
#define SEQSTAT_EXCAUSE        (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
                                MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
                                MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
                                MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
                                MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
                                MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
                                0)

/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET       (MK_BMSK_(SEQSTAT_SFTRESET_P))

/* Last hw error cause */
#define SEQSTAT_HWERRCAUSE     (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
                                MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
                                MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
                                MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
                                MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
                                0)

/* Translate bits to something useful */

/* Last hw error cause */
#define SEQSTAT_HWERRCAUSE_SHIFT         (14)
#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR    (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
#define SEQSTAT_HWERRCAUSE_PERF_FLOW     (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
#define SEQSTAT_HWERRCAUSE_RAISE_5       (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)

/**************************************************
 *   SYSCFG register
 **************************************************/

/* Bit Positions */
#define SYSCFG_SSSTEP_P     0x00000000	/* Supervisor single step, when
					 * set it forces an exception
					 * for each instruction executed
					 */
#define SYSCFG_CCEN_P       0x00000001	/* Enable cycle counter (=1) */
#define SYSCFG_SNEN_P       0x00000002	/* Self nesting Interrupt Enable */

/* Masks */

/* Supervisor single step, when set it forces an exception for each
 *instruction executed
 */
#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )
/* Enable cycle counter (=1) */
#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )
/* Self Nesting Interrupt Enable */
#define SYSCFG_SNEN	       MK_BMSK_(SYSCFG_SNEN_P)
/* Backward-compatibility for typos in prior releases */
#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
#define SYSCFG_CCCEN           SYSCFG_CCEN

/****************************************************
 * Core MMR Register Map
 ****************************************************/

/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */

#define SRAM_BASE_ADDRESS  0xFFE00000	/* SRAM Base Address Register */
#define DMEM_CONTROL       0xFFE00004	/* Data memory control */
#define DCPLB_STATUS       0xFFE00008	/* Data Cache Programmable Look-Aside
					 * Buffer Status
					 */
#define DCPLB_FAULT_STATUS 0xFFE00008	/* "" (older define) */
#define DCPLB_FAULT_ADDR   0xFFE0000C	/* Data Cache Programmable Look-Aside
					 * Buffer Fault Address
					 */
#define DCPLB_ADDR0        0xFFE00100	/* Data Cache Protection Lookaside
					 * Buffer 0
					 */
#define DCPLB_ADDR1        0xFFE00104	/* Data Cache Protection Lookaside
					 * Buffer 1
					 */
#define DCPLB_ADDR2        0xFFE00108	/* Data Cache Protection Lookaside
					 * Buffer 2
					 */
#define DCPLB_ADDR3        0xFFE0010C	/* Data Cacheability Protection
					 * Lookaside Buffer 3
					 */
#define DCPLB_ADDR4        0xFFE00110	/* Data Cacheability Protection
					 * Lookaside Buffer 4
					 */