Startsida Utforska Hjälp
Logga in
lixinru
/
aiot
1
0
Fork 0
Filer Ärenden 0 Pull-förfrågningar 0 Wiki
Träd: 5fd3d6d1cb
Grenar Taggar
aiot
/
efDataDiscreteRateMining
/
averageCalculation
/
calculationOfAverageCurrent.h

calculationOfAverageCurrent.h 6.9 KB
Historik Rå

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203 
  1. #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
    2. 

  2. #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
    3. 

  3. 

  4. /*
    5. 

  5.  * OMAP24XX Clock Management register bits
    6. 

  6.  *
    7. 

  7.  * Copyright (C) 2007 Texas Instruments, Inc.
    8. 

  8.  * Copyright (C) 2007 Nokia Corporation
    9. 

  9.  *
    10. 

  10.  * Written by Paul Walmsley
    11. 

  11.  *
    12. 

  12.  * This program is free software; you can redistribute it and/or modify
    13. 

  13.  * it under the terms of the GNU General Public License version 2 as
    14. 

  14.  * published by the Free Software Foundation.
    15. 

  15.  */
    16. 

  16. 

  17. /* Bits shared between registers */
    18. 

  18. 

  19. /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
    20. 

  20. #define OMAP24XX_EN_CAM_SHIFT				31
    21. 

  21. #define OMAP24XX_EN_CAM_MASK				(1 << 31)
    22. 

  22. #define OMAP24XX_EN_WDT4_SHIFT				29
    23. 

  23. #define OMAP24XX_EN_WDT4_MASK				(1 << 29)
    24. 

  24. #define OMAP2420_EN_WDT3_SHIFT				28
    25. 

  25. #define OMAP2420_EN_WDT3_MASK				(1 << 28)
    26. 

  26. #define OMAP24XX_EN_MSPRO_SHIFT				27
    27. 

  27. #define OMAP24XX_EN_MSPRO_MASK				(1 << 27)
    28. 

  28. #define OMAP24XX_EN_FAC_SHIFT				25
    29. 

  29. #define OMAP24XX_EN_FAC_MASK				(1 << 25)
    30. 

  30. #define OMAP2420_EN_EAC_SHIFT				24
    31. 

  31. #define OMAP2420_EN_EAC_MASK				(1 << 24)
    32. 

  32. #define OMAP24XX_EN_HDQ_SHIFT				23
    33. 

  33. #define OMAP24XX_EN_HDQ_MASK				(1 << 23)
    34. 

  34. #define OMAP2420_EN_I2C2_SHIFT				20
    35. 

  35. #define OMAP2420_EN_I2C2_MASK				(1 << 20)
    36. 

  36. #define OMAP2420_EN_I2C1_SHIFT				19
    37. 

  37. #define OMAP2420_EN_I2C1_MASK				(1 << 19)
    38. 

  38. 

  39. /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
    40. 

  40. #define OMAP2430_EN_MCBSP5_SHIFT			5
    41. 

  41. #define OMAP2430_EN_MCBSP5_MASK				(1 << 5)
    42. 

  42. #define OMAP2430_EN_MCBSP4_SHIFT			4
    43. 

  43. #define OMAP2430_EN_MCBSP4_MASK				(1 << 4)
    44. 

  44. #define OMAP2430_EN_MCBSP3_SHIFT			3
    45. 

  45. #define OMAP2430_EN_MCBSP3_MASK				(1 << 3)
    46. 

  46. #define OMAP24XX_EN_SSI_SHIFT				1
    47. 

  47. #define OMAP24XX_EN_SSI_MASK				(1 << 1)
    48. 

  48. 

  49. /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
    50. 

  50. #define OMAP24XX_EN_MPU_WDT_SHIFT			3
    51. 

  51. #define OMAP24XX_EN_MPU_WDT_MASK			(1 << 3)
    52. 

  52. 

  53. /* Bits specific to each register */
    54. 

  54. 

  55. /* CM_IDLEST_MPU */
    56. 

  56. /* 2430 only */
    57. 

  57. #define OMAP2430_ST_MPU_MASK				(1 << 0)
    58. 

  58. 

  59. /* CM_CLKSEL_MPU */
    60. 

  60. #define OMAP24XX_CLKSEL_MPU_SHIFT			0
    61. 

  61. #define OMAP24XX_CLKSEL_MPU_MASK			(0x1f << 0)
    62. 

  62. #define OMAP24XX_CLKSEL_MPU_WIDTH			5
    63. 

  63. 

  64. /* CM_CLKSTCTRL_MPU */
    65. 

  65. #define OMAP24XX_AUTOSTATE_MPU_SHIFT			0
    66. 

  66. #define OMAP24XX_AUTOSTATE_MPU_MASK			(1 << 0)
    67. 

  67. 

  68. /* CM_FCLKEN1_CORE specific bits*/
    69. 

  69. #define OMAP24XX_EN_TV_SHIFT				2
    70. 

  70. #define OMAP24XX_EN_TV_MASK				(1 << 2)
    71. 

  71. #define OMAP24XX_EN_DSS2_SHIFT				1
    72. 

  72. #define OMAP24XX_EN_DSS2_MASK				(1 << 1)
    73. 

  73. #define OMAP24XX_EN_DSS1_SHIFT				0
    74. 

  74. #define OMAP24XX_EN_DSS1_MASK				(1 << 0)
    75. 

  75. 

  76. /* CM_FCLKEN2_CORE specific bits */
    77. 

  77. #define OMAP2430_EN_I2CHS2_SHIFT			20
    78. 

  78. #define OMAP2430_EN_I2CHS2_MASK				(1 << 20)
    79. 

  79. #define OMAP2430_EN_I2CHS1_SHIFT			19
    80. 

  80. #define OMAP2430_EN_I2CHS1_MASK				(1 << 19)
    81. 

  81. #define OMAP2430_EN_MMCHSDB2_SHIFT			17
    82. 

  82. #define OMAP2430_EN_MMCHSDB2_MASK			(1 << 17)
    83. 

  83. #define OMAP2430_EN_MMCHSDB1_SHIFT			16
    84. 

  84. #define OMAP2430_EN_MMCHSDB1_MASK			(1 << 16)
    85. 

  85. 

  86. /* CM_ICLKEN1_CORE specific bits */
    87. 

  87. #define OMAP24XX_EN_MAILBOXES_SHIFT			30
    88. 

  88. #define OMAP24XX_EN_MAILBOXES_MASK			(1 << 30)
    89. 

  89. #define OMAP24XX_EN_DSS_SHIFT				0
    90. 

  90. #define OMAP24XX_EN_DSS_MASK				(1 << 0)
    91. 

  91. 

  92. /* CM_ICLKEN2_CORE specific bits */
    93. 

  93. 

  94. /* CM_ICLKEN3_CORE */
    95. 

  95. /* 2430 only */
    96. 

  96. #define OMAP2430_EN_SDRC_SHIFT				2
    97. 

  97. #define OMAP2430_EN_SDRC_MASK				(1 << 2)
    98. 

  98. 

  99. /* CM_ICLKEN4_CORE */
    100. 

  100. #define OMAP24XX_EN_PKA_SHIFT				4
    101. 

  101. #define OMAP24XX_EN_PKA_MASK				(1 << 4)
    102. 

  102. #define OMAP24XX_EN_AES_SHIFT				3
    103. 

  103. #define OMAP24XX_EN_AES_MASK				(1 << 3)
    104. 

  104. #define OMAP24XX_EN_RNG_SHIFT				2
    105. 

  105. #define OMAP24XX_EN_RNG_MASK				(1 << 2)
    106. 

  106. #define OMAP24XX_EN_SHA_SHIFT				1
    107. 

  107. #define OMAP24XX_EN_SHA_MASK				(1 << 1)
    108. 

  108. #define OMAP24XX_EN_DES_SHIFT				0
    109. 

  109. #define OMAP24XX_EN_DES_MASK				(1 << 0)
    110. 

  110. 

  111. /* CM_IDLEST1_CORE specific bits */
    112. 

  112. #define OMAP24XX_ST_MAILBOXES_SHIFT			30
    113. 

  113. #define OMAP24XX_ST_MAILBOXES_MASK			(1 << 30)
    114. 

  114. #define OMAP24XX_ST_WDT4_SHIFT				29
    115. 

  115. #define OMAP24XX_ST_WDT4_MASK				(1 << 29)
    116. 

  116. #define OMAP2420_ST_WDT3_SHIFT				28
    117. 

  117. #define OMAP2420_ST_WDT3_MASK				(1 << 28)
    118. 

  118. #define OMAP24XX_ST_MSPRO_SHIFT				27
    119. 

  119. #define OMAP24XX_ST_MSPRO_MASK				(1 << 27)
    120. 

  120. #define OMAP24XX_ST_FAC_SHIFT				25
    121. 

  121. #define OMAP24XX_ST_FAC_MASK				(1 << 25)
    122. 

  122. #define OMAP2420_ST_EAC_SHIFT				24
    123. 

  123. #define OMAP2420_ST_EAC_MASK				(1 << 24)
    124. 

  124. #define OMAP24XX_ST_HDQ_SHIFT				23
    125. 

  125. #define OMAP24XX_ST_HDQ_MASK				(1 << 23)
    126. 

  126. #define OMAP2420_ST_I2C2_SHIFT				20
    127. 

  127. #define OMAP2420_ST_I2C2_MASK				(1 << 20)
    128. 

  128. #define OMAP2430_ST_I2CHS1_SHIFT			19
    129. 

  129. #define OMAP2430_ST_I2CHS1_MASK				(1 << 19)
    130. 

  130. #define OMAP2420_ST_I2C1_SHIFT				19
    131. 

  131. #define OMAP2420_ST_I2C1_MASK				(1 << 19)
    132. 

  132. #define OMAP2430_ST_I2CHS2_SHIFT			20
    133. 

  133. #define OMAP2430_ST_I2CHS2_MASK				(1 << 20)
    134. 

  134. #define OMAP24XX_ST_MCBSP2_SHIFT			16
    135. 

  135. #define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
    136. 

  136. #define OMAP24XX_ST_MCBSP1_SHIFT			15
    137. 

  137. #define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
    138. 

  138. #define OMAP24XX_ST_DSS_SHIFT				0
    139. 

  139. #define OMAP24XX_ST_DSS_MASK				(1 << 0)
    140. 

  140. 

  141. /* CM_IDLEST2_CORE */
    142. 

  142. #define OMAP2430_ST_MCBSP5_SHIFT			5
    143. 

  143. #define OMAP2430_ST_MCBSP5_MASK				(1 << 5)
    144. 

  144. #define OMAP2430_ST_MCBSP4_SHIFT			4
    145. 

  145. #define OMAP2430_ST_MCBSP4_MASK				(1 << 4)
    146. 

  146. #define OMAP2430_ST_MCBSP3_SHIFT			3
    147. 

  147. #define OMAP2430_ST_MCBSP3_MASK				(1 << 3)
    148. 

  148. #define OMAP24XX_ST_SSI_SHIFT				1
    149. 

  149. #define OMAP24XX_ST_SSI_MASK				(1 << 1)
    150. 

  150. 

  151. /* CM_IDLEST3_CORE */
    152. 

  152. /* 2430 only */
    153. 

  153. #define OMAP2430_ST_SDRC_MASK				(1 << 2)
    154. 

  154. 

  155. /* CM_IDLEST4_CORE */
    156. 

  156. #define OMAP24XX_ST_PKA_SHIFT				4
    157. 

  157. #define OMAP24XX_ST_PKA_MASK				(1 << 4)
    158. 

  158. #define OMAP24XX_ST_AES_SHIFT				3
    159. 

  159. #define OMAP24XX_ST_AES_MASK				(1 << 3)
    160. 

  160. #define OMAP24XX_ST_RNG_SHIFT				2
    161. 

  161. #define OMAP24XX_ST_RNG_MASK				(1 << 2)
    162. 

  162. #define OMAP24XX_ST_SHA_SHIFT				1
    163. 

  163. #define OMAP24XX_ST_SHA_MASK				(1 << 1)
    164. 

  164. #define OMAP24XX_ST_DES_SHIFT				0
    165. 

  165. #define OMAP24XX_ST_DES_MASK				(1 << 0)
    166. 

  166. 

  167. /* CM_AUTOIDLE1_CORE */
    168. 

  168. #define OMAP24XX_AUTO_CAM_MASK				(1 << 31)
    169. 

  169. #define OMAP24XX_AUTO_MAILBOXES_MASK			(1 << 30)
    170. 

  170. #define OMAP24XX_AUTO_WDT4_MASK				(1 << 29)
    171. 

  171. #define OMAP2420_AUTO_WDT3_MASK				(1 << 28)
    172. 

  172. #define OMAP24XX_AUTO_MSPRO_MASK			(1 << 27)
    173. 

  173. #define OMAP2420_AUTO_MMC_MASK				(1 << 26)
    174. 

  174. #define OMAP24XX_AUTO_FAC_MASK				(1 << 25)
    175. 

  175. #define OMAP2420_AUTO_EAC_MASK				(1 << 24)
    176. 

  176. #define OMAP24XX_AUTO_HDQ_MASK				(1 << 23)
    177. 

  177. #define OMAP24XX_AUTO_UART2_MASK			(1 << 22)
    178. 

  178. #define OMAP24XX_AUTO_UART1_MASK			(1 << 21)
    179. 

  179. #define OMAP24XX_AUTO_I2C2_MASK				(1 << 20)
    180. 

  180. #define OMAP24XX_AUTO_I2C1_MASK				(1 << 19)
    181. 

  181. #define OMAP24XX_AUTO_MCSPI2_MASK			(1 << 18)
    182. 

  182. #define OMAP24XX_AUTO_MCSPI1_MASK			(1 << 17)
    183. 

  183. #define OMAP24XX_AUTO_MCBSP2_MASK			(1 << 16)
    184. 

  184. #define OMAP24XX_AUTO_MCBSP1_MASK			(1 << 15)
    185. 

  185. #define OMAP24XX_AUTO_GPT12_MASK			(1 << 14)
    186. 

  186. #define OMAP24XX_AUTO_GPT11_MASK			(1 << 13)
    187. 

  187. #define OMAP24XX_AUTO_GPT10_MASK			(1 << 12)
    188. 

  188. #define OMAP24XX_AUTO_GPT9_MASK				(1 << 11)
    189. 

  189. #define OMAP24XX_AUTO_GPT8_MASK				(1 << 10)
    190. 

  190. #define OMAP24XX_AUTO_GPT7_MASK				(1 << 9)
    191. 

  191. #define OMAP24XX_AUTO_GPT6_MASK				(1 << 8)
    192. 

  192. #define OMAP24XX_AUTO_GPT5_MASK				(1 << 7)
    193. 

  193. #define OMAP24XX_AUTO_GPT4_MASK				(1 << 6)
    194. 

  194. #define OMAP24XX_AUTO_GPT3_MASK				(1 << 5)
    195. 

  195. #define OMAP24XX_AUTO_GPT2_MASK				(1 << 4)
    196. 

  196. #define OMAP2420_AUTO_VLYNQ_MASK			(1 << 3)
    197. 

  197. #define OMAP24XX_AUTO_DSS_MASK				(1 << 0)
    198. 

  198. 

  199. /* CM_AUTOIDLE2_CORE */
    200. 

  200. #define OMAP2430_AUTO_MDM_INTC_MASK			(1 << 11)
    201. 

  201. #define OMAP2430_AUTO_GPIO5_MASK			(1 << 10)
    202. 

  202. #define OMAP2430_AUTO_MCSPI3_MASK			(1 << 9)
    203. 

  203. #define OMAP2430_AUTO_MMCHS2_MASK			(1 << 8)
    204.