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aiot
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waterDataStatistics
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alarmProcessingDataCalculation
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realizationOfDataCalculation.h

realizationOfDataCalculation.h 8.0 KB
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  1. /*
    2. 

  2.  * Copyright 2007-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF54X_H
    8. 

  8. #define _CDEF_BF54X_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* PLL Registers */
    15. 

  15. 

  16. #define bfin_read_PLL_CTL()		bfin_read16(PLL_CTL)
    17. 

  17. #define bfin_read_PLL_DIV()		bfin_read16(PLL_DIV)
    18. 

  18. #define bfin_write_PLL_DIV(val)		bfin_write16(PLL_DIV, val)
    19. 

  19. #define bfin_read_VR_CTL()		bfin_read16(VR_CTL)
    20. 

  20. #define bfin_read_PLL_STAT()		bfin_read16(PLL_STAT)
    21. 

  21. #define bfin_write_PLL_STAT(val)	bfin_write16(PLL_STAT, val)
    22. 

  22. #define bfin_read_PLL_LOCKCNT()		bfin_read16(PLL_LOCKCNT)
    23. 

  23. #define bfin_write_PLL_LOCKCNT(val)	bfin_write16(PLL_LOCKCNT, val)
    24. 

  24. 

  25. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
    26. 

  26. 

  27. #define bfin_read_CHIPID()		bfin_read32(CHIPID)
    28. 

  28. #define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
    29. 

  29. 

  30. /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
    31. 

  31. 

  32. #define bfin_read_SWRST()		bfin_read16(SWRST)
    33. 

  33. #define bfin_write_SWRST(val)		bfin_write16(SWRST, val)
    34. 

  34. #define bfin_read_SYSCR()		bfin_read16(SYSCR)
    35. 

  35. #define bfin_write_SYSCR(val)		bfin_write16(SYSCR, val)
    36. 

  36. 

  37. /* SIC Registers */
    38. 

  38. 

  39. #define bfin_read_SIC_RVECT()		bfin_read32(SIC_RVECT)
    40. 

  40. #define bfin_write_SIC_RVECT(val)	bfin_write32(SIC_RVECT, val)
    41. 

  41. #define bfin_read_SIC_IMASK0()		bfin_read32(SIC_IMASK0)
    42. 

  42. #define bfin_write_SIC_IMASK0(val)	bfin_write32(SIC_IMASK0, val)
    43. 

  43. #define bfin_read_SIC_IMASK1()		bfin_read32(SIC_IMASK1)
    44. 

  44. #define bfin_write_SIC_IMASK1(val)	bfin_write32(SIC_IMASK1, val)
    45. 

  45. #define bfin_read_SIC_IMASK2()		bfin_read32(SIC_IMASK2)
    46. 

  46. #define bfin_write_SIC_IMASK2(val)	bfin_write32(SIC_IMASK2, val)
    47. 

  47. #define bfin_read_SIC_IMASK(x)		bfin_read32(SIC_IMASK0 + (x << 2))
    48. 

  48. #define bfin_write_SIC_IMASK(x, val)	bfin_write32((SIC_IMASK0 + (x << 2)), val)
    49. 

  49. 

  50. #define bfin_read_SIC_ISR0()		bfin_read32(SIC_ISR0)
    51. 

  51. #define bfin_write_SIC_ISR0(val)	bfin_write32(SIC_ISR0, val)
    52. 

  52. #define bfin_read_SIC_ISR1()		bfin_read32(SIC_ISR1)
    53. 

  53. #define bfin_write_SIC_ISR1(val)	bfin_write32(SIC_ISR1, val)
    54. 

  54. #define bfin_read_SIC_ISR2()		bfin_read32(SIC_ISR2)
    55. 

  55. #define bfin_write_SIC_ISR2(val)	bfin_write32(SIC_ISR2, val)
    56. 

  56. #define bfin_read_SIC_ISR(x)		bfin_read32(SIC_ISR0 + (x << 2))
    57. 

  57. #define bfin_write_SIC_ISR(x, val)	bfin_write32((SIC_ISR0 + (x << 2)), val)
    58. 

  58. 

  59. #define bfin_read_SIC_IWR0()		bfin_read32(SIC_IWR0)
    60. 

  60. #define bfin_write_SIC_IWR0(val)	bfin_write32(SIC_IWR0, val)
    61. 

  61. #define bfin_read_SIC_IWR1()		bfin_read32(SIC_IWR1)
    62. 

  62. #define bfin_write_SIC_IWR1(val)	bfin_write32(SIC_IWR1, val)
    63. 

  63. #define bfin_read_SIC_IWR2()		bfin_read32(SIC_IWR2)
    64. 

  64. #define bfin_write_SIC_IWR2(val)	bfin_write32(SIC_IWR2, val)
    65. 

  65. #define bfin_read_SIC_IAR0()		bfin_read32(SIC_IAR0)
    66. 

  66. #define bfin_write_SIC_IAR0(val)	bfin_write32(SIC_IAR0, val)
    67. 

  67. #define bfin_read_SIC_IAR1()		bfin_read32(SIC_IAR1)
    68. 

  68. #define bfin_write_SIC_IAR1(val)	bfin_write32(SIC_IAR1, val)
    69. 

  69. #define bfin_read_SIC_IAR2()		bfin_read32(SIC_IAR2)
    70. 

  70. #define bfin_write_SIC_IAR2(val)	bfin_write32(SIC_IAR2, val)
    71. 

  71. #define bfin_read_SIC_IAR3()		bfin_read32(SIC_IAR3)
    72. 

  72. #define bfin_write_SIC_IAR3(val)	bfin_write32(SIC_IAR3, val)
    73. 

  73. #define bfin_read_SIC_IAR4()		bfin_read32(SIC_IAR4)
    74. 

  74. #define bfin_write_SIC_IAR4(val)	bfin_write32(SIC_IAR4, val)
    75. 

  75. #define bfin_read_SIC_IAR5()		bfin_read32(SIC_IAR5)
    76. 

  76. #define bfin_write_SIC_IAR5(val)	bfin_write32(SIC_IAR5, val)
    77. 

  77. #define bfin_read_SIC_IAR6()		bfin_read32(SIC_IAR6)
    78. 

  78. #define bfin_write_SIC_IAR6(val)	bfin_write32(SIC_IAR6, val)
    79. 

  79. #define bfin_read_SIC_IAR7()		bfin_read32(SIC_IAR7)
    80. 

  80. #define bfin_write_SIC_IAR7(val)	bfin_write32(SIC_IAR7, val)
    81. 

  81. #define bfin_read_SIC_IAR8()		bfin_read32(SIC_IAR8)
    82. 

  82. #define bfin_write_SIC_IAR8(val)	bfin_write32(SIC_IAR8, val)
    83. 

  83. #define bfin_read_SIC_IAR9()		bfin_read32(SIC_IAR9)
    84. 

  84. #define bfin_write_SIC_IAR9(val)	bfin_write32(SIC_IAR9, val)
    85. 

  85. #define bfin_read_SIC_IAR10()		bfin_read32(SIC_IAR10)
    86. 

  86. #define bfin_write_SIC_IAR10(val)	bfin_write32(SIC_IAR10, val)
    87. 

  87. #define bfin_read_SIC_IAR11()		bfin_read32(SIC_IAR11)
    88. 

  88. #define bfin_write_SIC_IAR11(val)	bfin_write32(SIC_IAR11, val)
    89. 

  89. 

  90. /* Watchdog Timer Registers */
    91. 

  91. 

  92. #define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
    93. 

  93. #define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
    94. 

  94. #define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
    95. 

  95. #define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
    96. 

  96. #define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
    97. 

  97. #define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)
    98. 

  98. 

  99. /* RTC Registers */
    100. 

  100. 

  101. #define bfin_read_RTC_STAT()		bfin_read32(RTC_STAT)
    102. 

  102. #define bfin_write_RTC_STAT(val)	bfin_write32(RTC_STAT, val)
    103. 

  103. #define bfin_read_RTC_ICTL()		bfin_read16(RTC_ICTL)
    104. 

  104. #define bfin_write_RTC_ICTL(val)	bfin_write16(RTC_ICTL, val)
    105. 

  105. #define bfin_read_RTC_ISTAT()		bfin_read16(RTC_ISTAT)
    106. 

  106. #define bfin_write_RTC_ISTAT(val)	bfin_write16(RTC_ISTAT, val)
    107. 

  107. #define bfin_read_RTC_SWCNT()		bfin_read16(RTC_SWCNT)
    108. 

  108. #define bfin_write_RTC_SWCNT(val)	bfin_write16(RTC_SWCNT, val)
    109. 

  109. #define bfin_read_RTC_ALARM()		bfin_read32(RTC_ALARM)
    110. 

  110. #define bfin_write_RTC_ALARM(val)	bfin_write32(RTC_ALARM, val)
    111. 

  111. #define bfin_read_RTC_PREN()		bfin_read16(RTC_PREN)
    112. 

  112. #define bfin_write_RTC_PREN(val)	bfin_write16(RTC_PREN, val)
    113. 

  113. 

  114. /* UART0 Registers */
    115. 

  115. 

  116. #define bfin_read_UART0_DLL()		bfin_read16(UART0_DLL)
    117. 

  117. #define bfin_write_UART0_DLL(val)	bfin_write16(UART0_DLL, val)
    118. 

  118. #define bfin_read_UART0_DLH()		bfin_read16(UART0_DLH)
    119. 

  119. #define bfin_write_UART0_DLH(val)	bfin_write16(UART0_DLH, val)
    120. 

  120. #define bfin_read_UART0_GCTL()		bfin_read16(UART0_GCTL)
    121. 

  121. #define bfin_write_UART0_GCTL(val)	bfin_write16(UART0_GCTL, val)
    122. 

  122. #define bfin_read_UART0_LCR()		bfin_read16(UART0_LCR)
    123. 

  123. #define bfin_write_UART0_LCR(val)	bfin_write16(UART0_LCR, val)
    124. 

  124. #define bfin_read_UART0_MCR()		bfin_read16(UART0_MCR)
    125. 

  125. #define bfin_write_UART0_MCR(val)	bfin_write16(UART0_MCR, val)
    126. 

  126. #define bfin_read_UART0_LSR()		bfin_read16(UART0_LSR)
    127. 

  127. #define bfin_write_UART0_LSR(val)	bfin_write16(UART0_LSR, val)
    128. 

  128. #define bfin_read_UART0_MSR()		bfin_read16(UART0_MSR)
    129. 

  129. #define bfin_write_UART0_MSR(val)	bfin_write16(UART0_MSR, val)
    130. 

  130. #define bfin_read_UART0_SCR()		bfin_read16(UART0_SCR)
    131. 

  131. #define bfin_write_UART0_SCR(val)	bfin_write16(UART0_SCR, val)
    132. 

  132. #define bfin_read_UART0_IER_SET()	bfin_read16(UART0_IER_SET)
    133. 

  133. #define bfin_write_UART0_IER_SET(val)	bfin_write16(UART0_IER_SET, val)
    134. 

  134. #define bfin_read_UART0_IER_CLEAR()	bfin_read16(UART0_IER_CLEAR)
    135. 

  135. #define bfin_write_UART0_IER_CLEAR(val)	bfin_write16(UART0_IER_CLEAR, val)
    136. 

  136. #define bfin_read_UART0_THR()		bfin_read16(UART0_THR)
    137. 

  137. #define bfin_write_UART0_THR(val)	bfin_write16(UART0_THR, val)
    138. 

  138. #define bfin_read_UART0_RBR()		bfin_read16(UART0_RBR)
    139. 

  139. #define bfin_write_UART0_RBR(val)	bfin_write16(UART0_RBR, val)
    140. 

  140. 

  141. /* SPI0 Registers */
    142. 

  142. 

  143. #define bfin_read_SPI0_CTL()		bfin_read16(SPI0_CTL)
    144. 

  144. #define bfin_write_SPI0_CTL(val)	bfin_write16(SPI0_CTL, val)
    145. 

  145. #define bfin_read_SPI0_FLG()		bfin_read16(SPI0_FLG)
    146. 

  146. #define bfin_write_SPI0_FLG(val)	bfin_write16(SPI0_FLG, val)
    147. 

  147. #define bfin_read_SPI0_STAT()		bfin_read16(SPI0_STAT)
    148. 

  148. #define bfin_write_SPI0_STAT(val)	bfin_write16(SPI0_STAT, val)
    149. 

  149. #define bfin_read_SPI0_TDBR()		bfin_read16(SPI0_TDBR)
    150. 

  150. #define bfin_write_SPI0_TDBR(val)	bfin_write16(SPI0_TDBR, val)
    151. 

  151. #define bfin_read_SPI0_RDBR()		bfin_read16(SPI0_RDBR)
    152. 

  152. #define bfin_write_SPI0_RDBR(val)	bfin_write16(SPI0_RDBR, val)
    153. 

  153. #define bfin_read_SPI0_BAUD()		bfin_read16(SPI0_BAUD)
    154. 

  154. #define bfin_write_SPI0_BAUD(val)	bfin_write16(SPI0_BAUD, val)
    155. 

  155. #define bfin_read_SPI0_SHADOW()		bfin_read16(SPI0_SHADOW)
    156. 

  156. #define bfin_write_SPI0_SHADOW(val)	bfin_write16(SPI0_SHADOW, val)
    157. 

  157. 

  158. /* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
    159. 

  159. 

  160. /* Two Wire Interface Registers (TWI0) */
    161. 

  161. 

  162. /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
    163. 

  163. 

  164. /* SPORT1 Registers */
    165. 

  165. 

  166. #define bfin_read_SPORT1_TCR1()		bfin_read16(SPORT1_TCR1)
    167. 

  167. #define bfin_write_SPORT1_TCR1(val)	bfin_write16(SPORT1_TCR1, val)
    168. 

  168. #define bfin_read_SPORT1_TCR2()		bfin_read16(SPORT1_TCR2)
    169. 

  169. #define bfin_write_SPORT1_TCR2(val)	bfin_write16(SPORT1_TCR2, val)
    170. 

  170. #define bfin_read_SPORT1_TCLKDIV()	bfin_read16(SPORT1_TCLKDIV)
    171. 

  171. #define bfin_write_SPORT1_TCLKDIV(val)	bfin_write16(SPORT1_TCLKDIV, val)
    172.