liquidLevelDifference.c 3.7 KB

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  1. /*
  2. * r8a7779 processor support - PFC hardware block
  3. *
  4. * Copyright (C) 2011 Renesas Solutions Corp.
  5. * Copyright (C) 2011 Magnus Damm
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/sh_pfc.h>
  23. #include <linux/ioport.h>
  24. #include <mach/r8a7779.h>
  25. #define CPU_32_PORT(fn, pfx, sfx) \
  26. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  27. PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
  28. PORT_1(fn, pfx##31, sfx)
  29. #define CPU_32_PORT6(fn, pfx, sfx) \
  30. PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
  31. PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
  32. PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
  33. PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
  34. PORT_1(fn, pfx##8, sfx)
  35. #define CPU_ALL_PORT(fn, pfx, sfx) \
  36. CPU_32_PORT(fn, pfx##_0_, sfx), \
  37. CPU_32_PORT(fn, pfx##_1_, sfx), \
  38. CPU_32_PORT(fn, pfx##_2_, sfx), \
  39. CPU_32_PORT(fn, pfx##_3_, sfx), \
  40. CPU_32_PORT(fn, pfx##_4_, sfx), \
  41. CPU_32_PORT(fn, pfx##_5_, sfx), \
  42. CPU_32_PORT6(fn, pfx##_6_, sfx)
  43. #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
  44. #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
  45. GP##pfx##_IN, GP##pfx##_OUT)
  46. #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
  47. #define _GP_INDT(pfx, sfx) GP##pfx##_DATA
  48. #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
  49. #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
  50. #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
  51. #define PORT_10_REV(fn, pfx, sfx) \
  52. PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
  53. PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
  54. PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
  55. PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
  56. PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
  57. #define CPU_32_PORT_REV(fn, pfx, sfx) \
  58. PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
  59. PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
  60. PORT_10_REV(fn, pfx, sfx)
  61. #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
  62. #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
  63. #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  64. #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  65. FN_##ipsr, FN_##fn)
  66. enum {
  67. PINMUX_RESERVED = 0,
  68. PINMUX_DATA_BEGIN,
  69. GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
  70. PINMUX_DATA_END,
  71. PINMUX_INPUT_BEGIN,
  72. GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
  73. PINMUX_INPUT_END,
  74. PINMUX_OUTPUT_BEGIN,
  75. GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
  76. PINMUX_OUTPUT_END,
  77. PINMUX_FUNCTION_BEGIN,
  78. GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
  79. /* GPSR0 */
  80. FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
  81. FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
  82. FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
  83. FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
  84. FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
  85. FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
  86. FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
  87. FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
  88. /* GPSR1 */
  89. FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,