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waterHeterogeneousDataSynchronization
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monitoringDataProcessing
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preliminaryDataProcessing.h

preliminaryDataProcessing.h 16 KB
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  1. /*
    2. 

  2.  * Copyright 2005-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF561_H
    8. 

  8. #define _CDEF_BF561_H
    9. 

  9. 

  10. /*********************************************************************************** */
    11. 

  11. /* System MMR Register Map */
    12. 

  12. /*********************************************************************************** */
    13. 

  13. 

  14. /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
    15. 

  15. #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
    16. 

  16. #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
    17. 

  17. #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
    18. 

  18. #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
    19. 

  19. #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
    20. 

  20. #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
    21. 

  21. #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
    22. 

  22. #define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
    23. 

  23. #define bfin_read_CHIPID()                   bfin_read32(CHIPID)
    24. 

  24. 

  25. /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
    26. 

  26. #define bfin_read_SWRST()                    bfin_read16(SWRST)
    27. 

  27. #define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
    28. 

  28. #define bfin_read_SYSCR()                    bfin_read16(SYSCR)
    29. 

  29. #define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
    30. 

  30. #define bfin_read_SIC_RVECT()                bfin_read16(SIC_RVECT)
    31. 

  31. #define bfin_write_SIC_RVECT(val)            bfin_write16(SIC_RVECT,val)
    32. 

  32. #define bfin_read_SIC_IMASK0()               bfin_read32(SIC_IMASK0)
    33. 

  33. #define bfin_write_SIC_IMASK0(val)           bfin_write32(SIC_IMASK0,val)
    34. 

  34. #define bfin_read_SIC_IMASK1()               bfin_read32(SIC_IMASK1)
    35. 

  35. #define bfin_write_SIC_IMASK1(val)           bfin_write32(SIC_IMASK1,val)
    36. 

  36. #define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
    37. 

  37. #define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
    38. 

  38. #define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
    39. 

  39. #define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
    40. 

  40. #define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
    41. 

  41. #define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
    42. 

  42. #define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
    43. 

  43. #define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
    44. 

  44. #define bfin_read_SIC_IAR4()                 bfin_read32(SIC_IAR4)
    45. 

  45. #define bfin_write_SIC_IAR4(val)             bfin_write32(SIC_IAR4,val)
    46. 

  46. #define bfin_read_SIC_IAR5()                 bfin_read32(SIC_IAR5)
    47. 

  47. #define bfin_write_SIC_IAR5(val)             bfin_write32(SIC_IAR5,val)
    48. 

  48. #define bfin_read_SIC_IAR6()                 bfin_read32(SIC_IAR6)
    49. 

  49. #define bfin_write_SIC_IAR6(val)             bfin_write32(SIC_IAR6,val)
    50. 

  50. #define bfin_read_SIC_IAR7()                 bfin_read32(SIC_IAR7)
    51. 

  51. #define bfin_write_SIC_IAR7(val)             bfin_write32(SIC_IAR7,val)
    52. 

  52. #define bfin_read_SIC_ISR0()                 bfin_read32(SIC_ISR0)
    53. 

  53. #define bfin_write_SIC_ISR0(val)             bfin_write32(SIC_ISR0,val)
    54. 

  54. #define bfin_read_SIC_ISR1()                 bfin_read32(SIC_ISR1)
    55. 

  55. #define bfin_write_SIC_ISR1(val)             bfin_write32(SIC_ISR1,val)
    56. 

  56. #define bfin_read_SIC_IWR0()                 bfin_read32(SIC_IWR0)
    57. 

  57. #define bfin_write_SIC_IWR0(val)             bfin_write32(SIC_IWR0,val)
    58. 

  58. #define bfin_read_SIC_IWR1()                 bfin_read32(SIC_IWR1)
    59. 

  59. #define bfin_write_SIC_IWR1(val)             bfin_write32(SIC_IWR1,val)
    60. 

  60. 

  61. /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
    62. 

  62. #define bfin_read_SICB_SWRST()               bfin_read16(SICB_SWRST)
    63. 

  63. #define bfin_write_SICB_SWRST(val)           bfin_write16(SICB_SWRST,val)
    64. 

  64. #define bfin_read_SICB_SYSCR()               bfin_read16(SICB_SYSCR)
    65. 

  65. #define bfin_write_SICB_SYSCR(val)           bfin_write16(SICB_SYSCR,val)
    66. 

  66. #define bfin_read_SICB_RVECT()               bfin_read16(SICB_RVECT)
    67. 

  67. #define bfin_write_SICB_RVECT(val)           bfin_write16(SICB_RVECT,val)
    68. 

  68. #define bfin_read_SICB_IMASK0()              bfin_read32(SICB_IMASK0)
    69. 

  69. #define bfin_write_SICB_IMASK0(val)          bfin_write32(SICB_IMASK0,val)
    70. 

  70. #define bfin_read_SICB_IMASK1()              bfin_read32(SICB_IMASK1)
    71. 

  71. #define bfin_write_SICB_IMASK1(val)          bfin_write32(SICB_IMASK1,val)
    72. 

  72. #define bfin_read_SICB_IAR0()                bfin_read32(SICB_IAR0)
    73. 

  73. #define bfin_write_SICB_IAR0(val)            bfin_write32(SICB_IAR0,val)
    74. 

  74. #define bfin_read_SICB_IAR1()                bfin_read32(SICB_IAR1)
    75. 

  75. #define bfin_write_SICB_IAR1(val)            bfin_write32(SICB_IAR1,val)
    76. 

  76. #define bfin_read_SICB_IAR2()                bfin_read32(SICB_IAR2)
    77. 

  77. #define bfin_write_SICB_IAR2(val)            bfin_write32(SICB_IAR2,val)
    78. 

  78. #define bfin_read_SICB_IAR3()                bfin_read32(SICB_IAR3)
    79. 

  79. #define bfin_write_SICB_IAR3(val)            bfin_write32(SICB_IAR3,val)
    80. 

  80. #define bfin_read_SICB_IAR4()                bfin_read32(SICB_IAR4)
    81. 

  81. #define bfin_write_SICB_IAR4(val)            bfin_write32(SICB_IAR4,val)
    82. 

  82. #define bfin_read_SICB_IAR5()                bfin_read32(SICB_IAR5)
    83. 

  83. #define bfin_write_SICB_IAR5(val)            bfin_write32(SICB_IAR5,val)
    84. 

  84. #define bfin_read_SICB_IAR6()                bfin_read32(SICB_IAR6)
    85. 

  85. #define bfin_write_SICB_IAR6(val)            bfin_write32(SICB_IAR6,val)
    86. 

  86. #define bfin_read_SICB_IAR7()                bfin_read32(SICB_IAR7)
    87. 

  87. #define bfin_write_SICB_IAR7(val)            bfin_write32(SICB_IAR7,val)
    88. 

  88. #define bfin_read_SICB_ISR0()                bfin_read32(SICB_ISR0)
    89. 

  89. #define bfin_write_SICB_ISR0(val)            bfin_write32(SICB_ISR0,val)
    90. 

  90. #define bfin_read_SICB_ISR1()                bfin_read32(SICB_ISR1)
    91. 

  91. #define bfin_write_SICB_ISR1(val)            bfin_write32(SICB_ISR1,val)
    92. 

  92. #define bfin_read_SICB_IWR0()                bfin_read32(SICB_IWR0)
    93. 

  93. #define bfin_write_SICB_IWR0(val)            bfin_write32(SICB_IWR0,val)
    94. 

  94. #define bfin_read_SICB_IWR1()                bfin_read32(SICB_IWR1)
    95. 

  95. #define bfin_write_SICB_IWR1(val)            bfin_write32(SICB_IWR1,val)
    96. 

  96. /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
    97. 

  97. #define bfin_read_WDOGA_CTL()                bfin_read16(WDOGA_CTL)
    98. 

  98. #define bfin_write_WDOGA_CTL(val)            bfin_write16(WDOGA_CTL,val)
    99. 

  99. #define bfin_read_WDOGA_CNT()                bfin_read32(WDOGA_CNT)
    100. 

  100. #define bfin_write_WDOGA_CNT(val)            bfin_write32(WDOGA_CNT,val)
    101. 

  101. #define bfin_read_WDOGA_STAT()               bfin_read32(WDOGA_STAT)
    102. 

  102. #define bfin_write_WDOGA_STAT(val)           bfin_write32(WDOGA_STAT,val)
    103. 

  103. 

  104. /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
    105. 

  105. #define bfin_read_WDOGB_CTL()                bfin_read16(WDOGB_CTL)
    106. 

  106. #define bfin_write_WDOGB_CTL(val)            bfin_write16(WDOGB_CTL,val)
    107. 

  107. #define bfin_read_WDOGB_CNT()                bfin_read32(WDOGB_CNT)
    108. 

  108. #define bfin_write_WDOGB_CNT(val)            bfin_write32(WDOGB_CNT,val)
    109. 

  109. #define bfin_read_WDOGB_STAT()               bfin_read32(WDOGB_STAT)
    110. 

  110. #define bfin_write_WDOGB_STAT(val)           bfin_write32(WDOGB_STAT,val)
    111. 

  111. 

  112. /* UART Controller (0xFFC00400 - 0xFFC004FF) */
    113. 

  113. #define bfin_read_UART_THR()                 bfin_read16(UART_THR)
    114. 

  114. #define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
    115. 

  115. #define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
    116. 

  116. #define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
    117. 

  117. #define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
    118. 

  118. #define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
    119. 

  119. #define bfin_read_UART_IER()                 bfin_read16(UART_IER)
    120. 

  120. #define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
    121. 

  121. #define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
    122. 

  122. #define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
    123. 

  123. #define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
    124. 

  124. #define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
    125. 

  125. #define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
    126. 

  126. #define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
    127. 

  127. #define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
    128. 

  128. #define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
    129. 

  129. #define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
    130. 

  130. #define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
    131. 

  131. #define bfin_read_UART_MSR()                 bfin_read16(UART_MSR)
    132. 

  132. #define bfin_write_UART_MSR(val)             bfin_write16(UART_MSR,val)
    133. 

  133. #define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
    134. 

  134. #define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
    135. 

  135. #define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
    136. 

  136. #define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
    137. 

  137. 

  138. /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
    139. 

  139. #define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
    140. 

  140. #define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
    141. 

  141. #define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
    142. 

  142. #define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
    143. 

  143. #define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
    144. 

  144. #define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
    145. 

  145. #define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
    146. 

  146. #define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
    147. 

  147. #define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
    148. 

  148. #define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
    149. 

  149. #define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
    150. 

  150. #define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
    151. 

  151. #define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
    152. 

  152. #define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
    153. 

  153. 

  154. /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
    155. 

  155. #define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
    156. 

  156. #define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
    157. 

  157. #define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
    158. 

  158. #define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
    159. 

  159. #define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
    160. 

  160. #define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
    161. 

  161. #define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
    162. 

  162. #define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
    163. 

  163. #define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
    164. 

  164. #define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
    165. 

  165. #define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
    166. 

  166. #define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
    167. 

  167. #define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
    168. 

  168. #define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
    169. 

  169. #define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
    170. 

  170. #define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
    171. 

  171. #define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
    172. 

  172. #define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
    173. 

  173. #define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
    174. 

  174. #define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
    175. 

  175. #define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
    176. 

  176. #define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
    177. 

  177. #define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
    178. 

  178. #define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
    179. 

  179. #define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
    180. 

  180. #define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
    181. 

  181. #define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
    182. 

  182. #define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
    183. 

  183. #define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
    184. 

  184. #define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
    185. 

  185. #define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
    186. 

  186. #define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
    187. 

  187. #define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
    188. 

  188. #define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
    189. 

  189. #define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
    190. 

  190. #define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
    191. 

  191. #define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
    192. 

  192. #define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
    193. 

  193. #define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
    194. 

  194. #define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
    195. 

  195. #define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
    196. 

  196. #define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
    197. 

  197. #define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
    198. 

  198. #define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
    199. 

  199. #define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
    200. 

  200. #define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
    201. 

  201. #define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
    202. 

  202. #define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
    203. 

  203. #define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
    204. 

  204. #define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
    205. 

  205. #define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
    206. 

  206. #define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
    207. 

  207. #define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
    208. 

  208. #define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
    209. 

  209. #define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
    210. 

  210. #define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
    211. 

  211. #define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
    212. 

  212. #define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
    213. 

  213. #define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
    214. 

  214. #define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
    215. 

  215. #define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
    216. 

  216. #define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
    217. 

  217. #define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
    218. 

  218. #define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
    219. 

  219. 

  220. /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
    221. 

  221. #define bfin_read_TMRS8_ENABLE()             bfin_read16(TMRS8_ENABLE)
    222. 

  222. #define bfin_write_TMRS8_ENABLE(val)         bfin_write16(TMRS8_ENABLE,val)
    223. 

  223. #define bfin_read_TMRS8_DISABLE()            bfin_read16(TMRS8_DISABLE)
    224. 

  224. #define bfin_write_TMRS8_DISABLE(val)        bfin_write16(TMRS8_DISABLE,val)
    225. 

  225. #define bfin_read_TMRS8_STATUS()             bfin_read32(TMRS8_STATUS)
    226. 

  226. #define bfin_write_TMRS8_STATUS(val)         bfin_write32(TMRS8_STATUS,val)
    227. 

  227. #define bfin_read_TIMER8_CONFIG()            bfin_read16(TIMER8_CONFIG)
    228. 

  228. #define bfin_write_TIMER8_CONFIG(val)        bfin_write16(TIMER8_CONFIG,val)
    229. 

  229. #define bfin_read_TIMER8_COUNTER()           bfin_read32(TIMER8_COUNTER)
    230. 

  230. #define bfin_write_TIMER8_COUNTER(val)       bfin_write32(TIMER8_COUNTER,val)
    231. 

  231. #define bfin_read_TIMER8_PERIOD()            bfin_read32(TIMER8_PERIOD)
    232. 

  232. #define bfin_write_TIMER8_PERIOD(val)        bfin_write32(TIMER8_PERIOD,val)
    233. 

  233. #define bfin_read_TIMER8_WIDTH()             bfin_read32(TIMER8_WIDTH)
    234. 

  234. #define bfin_write_TIMER8_WIDTH(val)         bfin_write32(TIMER8_WIDTH,val)
    235. 

  235. #define bfin_read_TIMER9_CONFIG()            bfin_read16(TIMER9_CONFIG)
    236. 

  236. #define bfin_write_TIMER9_CONFIG(val)        bfin_write16(TIMER9_CONFIG,val)
    237. 

  237. #define bfin_read_TIMER9_COUNTER()           bfin_read32(TIMER9_COUNTER)
    238. 

  238. #define bfin_write_TIMER9_COUNTER(val)       bfin_write32(TIMER9_COUNTER,val)
    239. 

  239. #define bfin_read_TIMER9_PERIOD()            bfin_read32(TIMER9_PERIOD)
    240. 

  240. #define bfin_write_TIMER9_PERIOD(val)        bfin_write32(TIMER9_PERIOD,val)
    241. 

  241. #define bfin_read_TIMER9_WIDTH()             bfin_read32(TIMER9_WIDTH)
    242. 

  242. #define bfin_write_TIMER9_WIDTH(val)         bfin_write32(TIMER9_WIDTH,val)
    243. 

  243. #define bfin_read_TIMER10_CONFIG()           bfin_read16(TIMER10_CONFIG)
    244. 

  244. #define bfin_write_TIMER10_CONFIG(val)       bfin_write16(TIMER10_CONFIG,val)
    245. 

  245. #define bfin_read_TIMER10_COUNTER()          bfin_read32(TIMER10_COUNTER)
    246. 

  246. #define bfin_write_TIMER10_COUNTER(val)      bfin_write32(TIMER10_COUNTER,val)
    247.