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aiot
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waterHeterogeneousDataSynchronization
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externalConnectionMonitoring
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tcpConnectionMonitoring.h

tcpConnectionMonitoring.h 6.4 KB
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  1. /*
    2. 

  2.  * System & MMR bit and Address definitions for ADSP-BF532
    3. 

  3.  *
    4. 

  4.  * Copyright 2005-2010 Analog Devices Inc.
    5. 

  5.  *
    6. 

  6.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef _DEF_BF532_H
    10. 

  10. #define _DEF_BF532_H
    11. 

  11. 

  12. /*********************************************************************************** */
    13. 

  13. /* System MMR Register Map */
    14. 

  14. /*********************************************************************************** */
    15. 

  15. /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
    16. 

  16. 

  17. #define PLL_CTL                0xFFC00000	/* PLL Control register (16-bit) */
    18. 

  18. #define PLL_DIV			 0xFFC00004	/* PLL Divide Register (16-bit) */
    19. 

  19. #define VR_CTL			 0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    20. 

  20. #define PLL_STAT               0xFFC0000C	/* PLL Status register (16-bit) */
    21. 

  21. #define PLL_LOCKCNT            0xFFC00010	/* PLL Lock Count register (16-bit) */
    22. 

  22. #define CHIPID                 0xFFC00014       /* Chip ID Register */
    23. 

  23. 

  24. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
    25. 

  25. #define SWRST			0xFFC00100  /* Software Reset Register (16-bit) */
    26. 

  26. #define SYSCR			0xFFC00104  /* System Configuration registe */
    27. 

  27. #define SIC_RVECT             		0xFFC00108	/* Interrupt Reset Vector Address Register */
    28. 

  28. #define SIC_IMASK             		0xFFC0010C	/* Interrupt Mask Register */
    29. 

  29. #define SIC_IAR0               		0xFFC00110	/* Interrupt Assignment Register 0 */
    30. 

  30. #define SIC_IAR1               		0xFFC00114	/* Interrupt Assignment Register 1 */
    31. 

  31. #define SIC_IAR2              		0xFFC00118	/* Interrupt Assignment Register 2 */
    32. 

  32. #define SIC_ISR                		0xFFC00120	/* Interrupt Status Register */
    33. 

  33. #define SIC_IWR                		0xFFC00124	/* Interrupt Wakeup Register */
    34. 

  34. 

  35. /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
    36. 

  36. #define WDOG_CTL                	0xFFC00200	/* Watchdog Control Register */
    37. 

  37. #define WDOG_CNT                	0xFFC00204	/* Watchdog Count Register */
    38. 

  38. #define WDOG_STAT               	0xFFC00208	/* Watchdog Status Register */
    39. 

  39. 

  40. /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
    41. 

  41. #define RTC_STAT                	0xFFC00300	/* RTC Status Register */
    42. 

  42. #define RTC_ICTL                	0xFFC00304	/* RTC Interrupt Control Register */
    43. 

  43. #define RTC_ISTAT               	0xFFC00308	/* RTC Interrupt Status Register */
    44. 

  44. #define RTC_SWCNT               	0xFFC0030C	/* RTC Stopwatch Count Register */
    45. 

  45. #define RTC_ALARM               	0xFFC00310	/* RTC Alarm Time Register */
    46. 

  46. #define RTC_FAST                	0xFFC00314	/* RTC Prescaler Enable Register */
    47. 

  47. #define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Register (alternate macro) */
    48. 

  48. 

  49. /* UART Controller (0xFFC00400 - 0xFFC004FF) */
    50. 

  50. 

  51. /*
    52. 

  52.  * Because include/linux/serial_reg.h have defined UART_*,
    53. 

  53.  * So we define blackfin uart regs to BFIN_UART_*.
    54. 

  54.  */
    55. 

  55. #define BFIN_UART_THR			0xFFC00400	/* Transmit Holding register */
    56. 

  56. #define BFIN_UART_RBR			0xFFC00400	/* Receive Buffer register */
    57. 

  57. #define BFIN_UART_DLL			0xFFC00400	/* Divisor Latch (Low-Byte) */
    58. 

  58. #define BFIN_UART_IER			0xFFC00404	/* Interrupt Enable Register */
    59. 

  59. #define BFIN_UART_DLH			0xFFC00404	/* Divisor Latch (High-Byte) */
    60. 

  60. #define BFIN_UART_IIR			0xFFC00408	/* Interrupt Identification Register */
    61. 

  61. #define BFIN_UART_LCR			0xFFC0040C	/* Line Control Register */
    62. 

  62. #define BFIN_UART_MCR			0xFFC00410	/* Modem Control Register */
    63. 

  63. #define BFIN_UART_LSR			0xFFC00414	/* Line Status Register */
    64. 

  64. #if 0
    65. 

  65. #define BFIN_UART_MSR			0xFFC00418	/* Modem Status Register (UNUSED in ADSP-BF532) */
    66. 

  66. #endif
    67. 

  67. #define BFIN_UART_SCR			0xFFC0041C	/* SCR Scratch Register */
    68. 

  68. #define BFIN_UART_GCTL			0xFFC00424	/* Global Control Register */
    69. 

  69. 

  70. /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
    71. 

  71. #define SPI0_REGBASE          		0xFFC00500
    72. 

  72. #define SPI_CTL               		0xFFC00500	/* SPI Control Register */
    73. 

  73. #define SPI_FLG               		0xFFC00504	/* SPI Flag register */
    74. 

  74. #define SPI_STAT              		0xFFC00508	/* SPI Status register */
    75. 

  75. #define SPI_TDBR              		0xFFC0050C	/* SPI Transmit Data Buffer Register */
    76. 

  76. #define SPI_RDBR              		0xFFC00510	/* SPI Receive Data Buffer Register */
    77. 

  77. #define SPI_BAUD              		0xFFC00514	/* SPI Baud rate Register */
    78. 

  78. #define SPI_SHADOW            		0xFFC00518	/* SPI_RDBR Shadow Register */
    79. 

  79. 

  80. /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
    81. 

  81. 

  82. #define TIMER0_CONFIG          		0xFFC00600	/* Timer 0 Configuration Register */
    83. 

  83. #define TIMER0_COUNTER			0xFFC00604	/* Timer 0 Counter Register */
    84. 

  84. #define TIMER0_PERIOD       		0xFFC00608	/* Timer 0 Period Register */
    85. 

  85. #define TIMER0_WIDTH        		0xFFC0060C	/* Timer 0 Width Register */
    86. 

  86. 

  87. #define TIMER1_CONFIG          		0xFFC00610	/*  Timer 1 Configuration Register   */
    88. 

  88. #define TIMER1_COUNTER         		0xFFC00614	/*  Timer 1 Counter Register         */
    89. 

  89. #define TIMER1_PERIOD          		0xFFC00618	/*  Timer 1 Period Register          */
    90. 

  90. #define TIMER1_WIDTH           		0xFFC0061C	/*  Timer 1 Width Register           */
    91. 

  91. 

  92. #define TIMER2_CONFIG          		0xFFC00620	/* Timer 2 Configuration Register   */
    93. 

  93. #define TIMER2_COUNTER         		0xFFC00624	/* Timer 2 Counter Register         */
    94. 

  94. #define TIMER2_PERIOD          		0xFFC00628	/* Timer 2 Period Register          */
    95. 

  95. #define TIMER2_WIDTH           		0xFFC0062C	/* Timer 2 Width Register           */
    96. 

  96. 

  97. #define TIMER_ENABLE			0xFFC00640	/* Timer Enable Register */
    98. 

  98. #define TIMER_DISABLE			0xFFC00644	/* Timer Disable Register */
    99. 

  99. #define TIMER_STATUS			0xFFC00648	/* Timer Status Register */
    100. 

  100. 

  101. /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
    102. 

  102. 

  103. #define FIO_FLAG_D	       		0xFFC00700	/* Flag Mask to directly specify state of pins */
    104. 

  104. #define FIO_FLAG_C             		0xFFC00704	/* Peripheral Interrupt Flag Register (clear) */
    105. 

  105. #define FIO_FLAG_S             		0xFFC00708	/* Peripheral Interrupt Flag Register (set) */
    106. 

  106. #define FIO_FLAG_T			0xFFC0070C	/* Flag Mask to directly toggle state of pins */
    107. 

  107. #define FIO_MASKA_D            		0xFFC00710	/* Flag Mask Interrupt A Register (set directly) */
    108. 

  108. #define FIO_MASKA_C            		0xFFC00714	/* Flag Mask Interrupt A Register (clear) */
    109. 

  109. #define FIO_MASKA_S            		0xFFC00718	/* Flag Mask Interrupt A Register (set) */
    110. 

  110. #define FIO_MASKA_T            		0xFFC0071C	/* Flag Mask Interrupt A Register (toggle) */
    111. 

  111. #define FIO_MASKB_D            		0xFFC00720	/* Flag Mask Interrupt B Register (set directly) */
    112. 

  112. #define FIO_MASKB_C            		0xFFC00724	/* Flag Mask Interrupt B Register (clear) */
    113. 

  113. #define FIO_MASKB_S            		0xFFC00728	/* Flag Mask Interrupt B Register (set) */
    114. 

  114. #define FIO_MASKB_T            		0xFFC0072C	/* Flag Mask Interrupt B Register (toggle) */
    115. 

  115. #define FIO_DIR                		0xFFC00730	/* Peripheral Flag Direction Register */
    116.