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aiot
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waterHeterogeneousDataSynchronization
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externalConnectionMonitoring
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commandProcessing.h

commandProcessing.h 19 KB
文件歷史 原始文件

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  1. /*
    2. 

  2.  * Copyright 2005-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF561_H
    8. 

  8. #define _DEF_BF561_H
    9. 

  9. 

  10. /*********************************************************************************** */
    11. 

  11. /* System MMR Register Map */
    12. 

  12. /*********************************************************************************** */
    13. 

  13. 

  14. /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
    15. 

  15. 

  16. #define PLL_CTL                0xFFC00000	/* PLL Control register (16-bit) */
    17. 

  17. #define PLL_DIV			        0xFFC00004	/* PLL Divide Register (16-bit) */
    18. 

  18. #define VR_CTL			        0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    19. 

  19. #define PLL_STAT               0xFFC0000C	/* PLL Status register (16-bit) */
    20. 

  20. #define PLL_LOCKCNT            0xFFC00010	/* PLL Lock Count register (16-bit) */
    21. 

  21. #define CHIPID                 0xFFC00014       /* Chip ID Register */
    22. 

  22. 

  23. /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
    24. 

  24. #define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
    25. 

  25. #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
    26. 

  26. #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
    27. 

  27. #define RESET_SOFTWARE          (SWRST_OCCURRED)
    28. 

  28. 

  29. /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
    30. 

  30. #define SWRST                   0xFFC00100	/* Software Reset register */
    31. 

  31. #define SYSCR                   0xFFC00104	/* System Reset Configuration register */
    32. 

  32. #define SIC_RVECT               0xFFC00108	/* SIC Reset Vector Address Register */
    33. 

  33. #define SIC_IMASK0              0xFFC0010C	/* SIC Interrupt Mask register 0 */
    34. 

  34. #define SIC_IMASK1              0xFFC00110	/* SIC Interrupt Mask register 1 */
    35. 

  35. #define SIC_IAR0                0xFFC00124	/* SIC Interrupt Assignment Register 0 */
    36. 

  36. #define SIC_IAR1                0xFFC00128	/* SIC Interrupt Assignment Register 1 */
    37. 

  37. #define SIC_IAR2                0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
    38. 

  38. #define SIC_IAR3                0xFFC00130	/* SIC Interrupt Assignment Register 3 */
    39. 

  39. #define SIC_IAR4                0xFFC00134	/* SIC Interrupt Assignment Register 4 */
    40. 

  40. #define SIC_IAR5                0xFFC00138	/* SIC Interrupt Assignment Register 5 */
    41. 

  41. #define SIC_IAR6                0xFFC0013C	/* SIC Interrupt Assignment Register 6 */
    42. 

  42. #define SIC_IAR7                0xFFC00140	/* SIC Interrupt Assignment Register 7 */
    43. 

  43. #define SIC_ISR0                0xFFC00114	/* SIC Interrupt Status register 0 */
    44. 

  44. #define SIC_ISR1                0xFFC00118	/* SIC Interrupt Status register 1 */
    45. 

  45. #define SIC_IWR0                0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
    46. 

  46. #define SIC_IWR1                0xFFC00120	/* SIC Interrupt Wakeup-Enable register 1 */
    47. 

  47. 

  48. /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
    49. 

  49. #define SICB_SWRST              0xFFC01100	/* reserved */
    50. 

  50. #define SICB_SYSCR              0xFFC01104	/* reserved */
    51. 

  51. #define SICB_RVECT              0xFFC01108	/* SIC Reset Vector Address Register */
    52. 

  52. #define SICB_IMASK0             0xFFC0110C	/* SIC Interrupt Mask register 0 */
    53. 

  53. #define SICB_IMASK1             0xFFC01110	/* SIC Interrupt Mask register 1 */
    54. 

  54. #define SICB_IAR0               0xFFC01124	/* SIC Interrupt Assignment Register 0 */
    55. 

  55. #define SICB_IAR1               0xFFC01128	/* SIC Interrupt Assignment Register 1 */
    56. 

  56. #define SICB_IAR2               0xFFC0112C	/* SIC Interrupt Assignment Register 2 */
    57. 

  57. #define SICB_IAR3               0xFFC01130	/* SIC Interrupt Assignment Register 3 */
    58. 

  58. #define SICB_IAR4               0xFFC01134	/* SIC Interrupt Assignment Register 4 */
    59. 

  59. #define SICB_IAR5               0xFFC01138	/* SIC Interrupt Assignment Register 5 */
    60. 

  60. #define SICB_IAR6               0xFFC0113C	/* SIC Interrupt Assignment Register 6 */
    61. 

  61. #define SICB_IAR7               0xFFC01140	/* SIC Interrupt Assignment Register 7 */
    62. 

  62. #define SICB_ISR0               0xFFC01114	/* SIC Interrupt Status register 0 */
    63. 

  63. #define SICB_ISR1               0xFFC01118	/* SIC Interrupt Status register 1 */
    64. 

  64. #define SICB_IWR0               0xFFC0111C	/* SIC Interrupt Wakeup-Enable register 0 */
    65. 

  65. #define SICB_IWR1               0xFFC01120	/* SIC Interrupt Wakeup-Enable register 1 */
    66. 

  66. 

  67. /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
    68. 

  68. #define WDOGA_CTL 				0xFFC00200	/* Watchdog Control register */
    69. 

  69. #define WDOGA_CNT 				0xFFC00204	/* Watchdog Count register */
    70. 

  70. #define WDOGA_STAT 				0xFFC00208	/* Watchdog Status register */
    71. 

  71. 

  72. /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
    73. 

  73. #define WDOGB_CTL 				0xFFC01200	/* Watchdog Control register */
    74. 

  74. #define WDOGB_CNT 				0xFFC01204	/* Watchdog Count register */
    75. 

  75. #define WDOGB_STAT 				0xFFC01208	/* Watchdog Status register */
    76. 

  76. 

  77. /* UART Controller (0xFFC00400 - 0xFFC004FF) */
    78. 

  78. 

  79. /*
    80. 

  80.  * Because include/linux/serial_reg.h have defined UART_*,
    81. 

  81.  * So we define blackfin uart regs to BFIN_UART0_*.
    82. 

  82.  */
    83. 

  83. #define BFIN_UART_THR			0xFFC00400  /* Transmit Holding register */
    84. 

  84. #define BFIN_UART_RBR			0xFFC00400  /* Receive Buffer register */
    85. 

  85. #define BFIN_UART_DLL			0xFFC00400  /* Divisor Latch (Low-Byte) */
    86. 

  86. #define BFIN_UART_IER			0xFFC00404  /* Interrupt Enable Register */
    87. 

  87. #define BFIN_UART_DLH			0xFFC00404  /* Divisor Latch (High-Byte) */
    88. 

  88. #define BFIN_UART_IIR			0xFFC00408  /* Interrupt Identification Register */
    89. 

  89. #define BFIN_UART_LCR			0xFFC0040C  /* Line Control Register */
    90. 

  90. #define BFIN_UART_MCR			0xFFC00410  /* Modem Control Register */
    91. 

  91. #define BFIN_UART_LSR			0xFFC00414  /* Line Status Register */
    92. 

  92. #define BFIN_UART_MSR			0xFFC00418  /* Modem Status Register */
    93. 

  93. #define BFIN_UART_SCR			0xFFC0041C  /* SCR Scratch Register */
    94. 

  94. #define BFIN_UART_GCTL			0xFFC00424  /* Global Control Register */
    95. 

  95. 

  96. /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
    97. 

  97. #define SPI0_REGBASE          		0xFFC00500
    98. 

  98. #define SPI_CTL               		0xFFC00500	/* SPI Control Register */
    99. 

  99. #define SPI_FLG               		0xFFC00504	/* SPI Flag register */
    100. 

  100. #define SPI_STAT              		0xFFC00508	/* SPI Status register */
    101. 

  101. #define SPI_TDBR              		0xFFC0050C	/* SPI Transmit Data Buffer Register */
    102. 

  102. #define SPI_RDBR              		0xFFC00510	/* SPI Receive Data Buffer Register */
    103. 

  103. #define SPI_BAUD              		0xFFC00514	/* SPI Baud rate Register */
    104. 

  104. #define SPI_SHADOW            		0xFFC00518	/* SPI_RDBR Shadow Register */
    105. 

  105. 

  106. /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
    107. 

  107. #define TIMER0_CONFIG 				0xFFC00600	/* Timer0 Configuration register */
    108. 

  108. #define TIMER0_COUNTER 				0xFFC00604	/* Timer0 Counter register */
    109. 

  109. #define TIMER0_PERIOD 				0xFFC00608	/* Timer0 Period register */
    110. 

  110. #define TIMER0_WIDTH 				0xFFC0060C	/* Timer0 Width register */
    111. 

  111. 

  112. #define TIMER1_CONFIG 				0xFFC00610	/* Timer1 Configuration register */
    113. 

  113. #define TIMER1_COUNTER 				0xFFC00614	/* Timer1 Counter register */
    114. 

  114. #define TIMER1_PERIOD 				0xFFC00618	/* Timer1 Period register */
    115. 

  115. #define TIMER1_WIDTH 				0xFFC0061C	/* Timer1 Width register */
    116. 

  116. 

  117. #define TIMER2_CONFIG 				0xFFC00620	/* Timer2 Configuration register */
    118. 

  118. #define TIMER2_COUNTER 				0xFFC00624	/* Timer2 Counter register */
    119. 

  119. #define TIMER2_PERIOD 				0xFFC00628	/* Timer2 Period register */
    120. 

  120. #define TIMER2_WIDTH 				0xFFC0062C	/* Timer2 Width register */
    121. 

  121. 

  122. #define TIMER3_CONFIG 				0xFFC00630	/* Timer3 Configuration register */
    123. 

  123. #define TIMER3_COUNTER 				0xFFC00634	/* Timer3 Counter register */
    124. 

  124. #define TIMER3_PERIOD 				0xFFC00638	/* Timer3 Period register */
    125. 

  125. #define TIMER3_WIDTH 				0xFFC0063C	/* Timer3 Width register */
    126. 

  126. 

  127. #define TIMER4_CONFIG 				0xFFC00640	/* Timer4 Configuration register */
    128. 

  128. #define TIMER4_COUNTER 				0xFFC00644	/* Timer4 Counter register */
    129. 

  129. #define TIMER4_PERIOD 				0xFFC00648	/* Timer4 Period register */
    130. 

  130. #define TIMER4_WIDTH 				0xFFC0064C	/* Timer4 Width register */
    131. 

  131. 

  132. #define TIMER5_CONFIG 				0xFFC00650	/* Timer5 Configuration register */
    133. 

  133. #define TIMER5_COUNTER 				0xFFC00654	/* Timer5 Counter register */
    134. 

  134. #define TIMER5_PERIOD 				0xFFC00658	/* Timer5 Period register */
    135. 

  135. #define TIMER5_WIDTH 				0xFFC0065C	/* Timer5 Width register */
    136. 

  136. 

  137. #define TIMER6_CONFIG 				0xFFC00660	/* Timer6 Configuration register */
    138. 

  138. #define TIMER6_COUNTER 				0xFFC00664	/* Timer6 Counter register */
    139. 

  139. #define TIMER6_PERIOD 				0xFFC00668	/* Timer6 Period register */
    140. 

  140. #define TIMER6_WIDTH 				0xFFC0066C	/* Timer6 Width register */
    141. 

  141. 

  142. #define TIMER7_CONFIG 				0xFFC00670	/* Timer7 Configuration register */
    143. 

  143. #define TIMER7_COUNTER 				0xFFC00674	/* Timer7 Counter register */
    144. 

  144. #define TIMER7_PERIOD 				0xFFC00678	/* Timer7 Period register */
    145. 

  145. #define TIMER7_WIDTH 				0xFFC0067C	/* Timer7 Width register */
    146. 

  146. 

  147. #define TMRS8_ENABLE 				0xFFC00680	/* Timer Enable Register */
    148. 

  148. #define TMRS8_DISABLE 				0xFFC00684	/* Timer Disable register */
    149. 

  149. #define TMRS8_STATUS 				0xFFC00688	/* Timer Status register */
    150. 

  150. 

  151. /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
    152. 

  152. #define TIMER8_CONFIG 				0xFFC01600	/* Timer8 Configuration register */
    153. 

  153. #define TIMER8_COUNTER 				0xFFC01604	/* Timer8 Counter register */
    154. 

  154. #define TIMER8_PERIOD 				0xFFC01608	/* Timer8 Period register */
    155. 

  155. #define TIMER8_WIDTH 				0xFFC0160C	/* Timer8 Width register */
    156. 

  156. 

  157. #define TIMER9_CONFIG 				0xFFC01610	/* Timer9 Configuration register */
    158. 

  158. #define TIMER9_COUNTER 				0xFFC01614	/* Timer9 Counter register */
    159. 

  159. #define TIMER9_PERIOD 				0xFFC01618	/* Timer9 Period register */
    160. 

  160. #define TIMER9_WIDTH 				0xFFC0161C	/* Timer9 Width register */
    161. 

  161. 

  162. #define TIMER10_CONFIG 				0xFFC01620	/* Timer10 Configuration register */
    163. 

  163. #define TIMER10_COUNTER 			0xFFC01624	/* Timer10 Counter register */
    164. 

  164. #define TIMER10_PERIOD 				0xFFC01628	/* Timer10 Period register */
    165. 

  165. #define TIMER10_WIDTH 				0xFFC0162C	/* Timer10 Width register */
    166. 

  166. 

  167. #define TIMER11_CONFIG 				0xFFC01630	/* Timer11 Configuration register */
    168. 

  168. #define TIMER11_COUNTER 			0xFFC01634	/* Timer11 Counter register */
    169. 

  169. #define TIMER11_PERIOD 				0xFFC01638	/* Timer11 Period register */
    170. 

  170. #define TIMER11_WIDTH 				0xFFC0163C	/* Timer11 Width register */
    171. 

  171. 

  172. #define TMRS4_ENABLE 				0xFFC01640	/* Timer Enable Register */
    173. 

  173. #define TMRS4_DISABLE 				0xFFC01644	/* Timer Disable register */
    174. 

  174. #define TMRS4_STATUS 				0xFFC01648	/* Timer Status register */
    175. 

  175. 

  176. /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
    177. 

  177. #define FIO0_FLAG_D 				0xFFC00700	/* Flag Data register */
    178. 

  178. #define FIO0_FLAG_C 				0xFFC00704	/* Flag Clear register */
    179. 

  179. #define FIO0_FLAG_S 				0xFFC00708	/* Flag Set register */
    180. 

  180. #define FIO0_FLAG_T 				0xFFC0070C	/* Flag Toggle register */
    181. 

  181. #define FIO0_MASKA_D 				0xFFC00710	/* Flag Mask Interrupt A Data register */
    182. 

  182. #define FIO0_MASKA_C 				0xFFC00714	/* Flag Mask Interrupt A Clear register */
    183. 

  183. #define FIO0_MASKA_S 				0xFFC00718	/* Flag Mask Interrupt A Set register */
    184. 

  184. #define FIO0_MASKA_T 				0xFFC0071C	/* Flag Mask Interrupt A Toggle register */
    185. 

  185. #define FIO0_MASKB_D 				0xFFC00720	/* Flag Mask Interrupt B Data register */
    186. 

  186. #define FIO0_MASKB_C 				0xFFC00724	/* Flag Mask Interrupt B Clear register */
    187. 

  187. #define FIO0_MASKB_S 				0xFFC00728	/* Flag Mask Interrupt B Set register */
    188. 

  188. #define FIO0_MASKB_T 				0xFFC0072C	/* Flag Mask Interrupt B Toggle register */
    189. 

  189. #define FIO0_DIR 					0xFFC00730	/* Flag Direction register */
    190. 

  190. #define FIO0_POLAR 					0xFFC00734	/* Flag Polarity register */
    191. 

  191. #define FIO0_EDGE 					0xFFC00738	/* Flag Interrupt Sensitivity register */
    192. 

  192. #define FIO0_BOTH 					0xFFC0073C	/* Flag Set on Both Edges register */
    193. 

  193. #define FIO0_INEN 					0xFFC00740	/* Flag Input Enable register */
    194. 

  194. 

  195. /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
    196. 

  196. #define FIO1_FLAG_D 				0xFFC01500	/* Flag Data register (mask used to directly */
    197. 

  197. #define FIO1_FLAG_C 				0xFFC01504	/* Flag Clear register */
    198. 

  198. #define FIO1_FLAG_S 				0xFFC01508	/* Flag Set register */
    199. 

  199. #define FIO1_FLAG_T 				0xFFC0150C	/* Flag Toggle register (mask used to */
    200. 

  200. #define FIO1_MASKA_D 				0xFFC01510	/* Flag Mask Interrupt A Data register */
    201. 

  201. #define FIO1_MASKA_C 				0xFFC01514	/* Flag Mask Interrupt A Clear register */
    202. 

  202. #define FIO1_MASKA_S 				0xFFC01518	/* Flag Mask Interrupt A Set register */
    203. 

  203. #define FIO1_MASKA_T 				0xFFC0151C	/* Flag Mask Interrupt A Toggle register */
    204. 

  204. #define FIO1_MASKB_D 				0xFFC01520	/* Flag Mask Interrupt B Data register */
    205. 

  205. #define FIO1_MASKB_C 				0xFFC01524	/* Flag Mask Interrupt B Clear register */
    206. 

  206. #define FIO1_MASKB_S 				0xFFC01528	/* Flag Mask Interrupt B Set register */
    207. 

  207. #define FIO1_MASKB_T 				0xFFC0152C	/* Flag Mask Interrupt B Toggle register */
    208. 

  208. #define FIO1_DIR 					0xFFC01530	/* Flag Direction register */
    209. 

  209. #define FIO1_POLAR 					0xFFC01534	/* Flag Polarity register */
    210. 

  210. #define FIO1_EDGE 					0xFFC01538	/* Flag Interrupt Sensitivity register */
    211. 

  211. #define FIO1_BOTH 					0xFFC0153C	/* Flag Set on Both Edges register */
    212. 

  212. #define FIO1_INEN 					0xFFC01540	/* Flag Input Enable register */
    213. 

  213. 

  214. /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
    215. 

  215. #define FIO2_FLAG_D 				0xFFC01700	/* Flag Data register (mask used to directly */
    216. 

  216. #define FIO2_FLAG_C 				0xFFC01704	/* Flag Clear register */
    217. 

  217. #define FIO2_FLAG_S 				0xFFC01708	/* Flag Set register */
    218. 

  218. #define FIO2_FLAG_T 				0xFFC0170C	/* Flag Toggle register (mask used to */
    219. 

  219. #define FIO2_MASKA_D 				0xFFC01710	/* Flag Mask Interrupt A Data register */
    220. 

  220. #define FIO2_MASKA_C 				0xFFC01714	/* Flag Mask Interrupt A Clear register */
    221. 

  221. #define FIO2_MASKA_S 				0xFFC01718	/* Flag Mask Interrupt A Set register */
    222. 

  222. #define FIO2_MASKA_T 				0xFFC0171C	/* Flag Mask Interrupt A Toggle register */
    223. 

  223. #define FIO2_MASKB_D 				0xFFC01720	/* Flag Mask Interrupt B Data register */
    224. 

  224. #define FIO2_MASKB_C 				0xFFC01724	/* Flag Mask Interrupt B Clear register */
    225. 

  225. #define FIO2_MASKB_S 				0xFFC01728	/* Flag Mask Interrupt B Set register */
    226. 

  226. #define FIO2_MASKB_T 				0xFFC0172C	/* Flag Mask Interrupt B Toggle register */
    227. 

  227. #define FIO2_DIR 					0xFFC01730	/* Flag Direction register */
    228. 

  228. #define FIO2_POLAR 					0xFFC01734	/* Flag Polarity register */
    229. 

  229. #define FIO2_EDGE 					0xFFC01738	/* Flag Interrupt Sensitivity register */
    230. 

  230. #define FIO2_BOTH 					0xFFC0173C	/* Flag Set on Both Edges register */
    231. 

  231. #define FIO2_INEN 					0xFFC01740	/* Flag Input Enable register */
    232. 

  232. 

  233. /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
    234. 

  234. #define SPORT0_TCR1     	 	0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
    235. 

  235. #define SPORT0_TCR2      	 	0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
    236. 

  236. #define SPORT0_TCLKDIV        		0xFFC00808	/* SPORT0 Transmit Clock Divider */
    237. 

  237. #define SPORT0_TFSDIV          		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
    238. 

  238. #define SPORT0_TX	             	0xFFC00810	/* SPORT0 TX Data Register */
    239. 

  239. #define SPORT0_RX	            	0xFFC00818	/* SPORT0 RX Data Register */
    240. 

  240. #define SPORT0_RCR1      	 		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
    241. 

  241. #define SPORT0_RCR2      	 		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
    242. 

  242. #define SPORT0_RCLKDIV        		0xFFC00828	/* SPORT0 Receive Clock Divider */
    243. 

  243. #define SPORT0_RFSDIV          		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
    244. 

  244. #define SPORT0_STAT            		0xFFC00830	/* SPORT0 Status Register */
    245. 

  245. #define SPORT0_CHNL            		0xFFC00834	/* SPORT0 Current Channel Register */
    246. 

  246. #define SPORT0_MCMC1           		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
    247. 

  247. #define SPORT0_MCMC2           		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
    248. 

  248. #define SPORT0_MTCS0           		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
    249. 

  249. #define SPORT0_MTCS1           		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
    250. 

  250. #define SPORT0_MTCS2           		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
    251. 

  251. #define SPORT0_MTCS3           		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
    252. 

  252. #define SPORT0_MRCS0           		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
    253. 

  253. #define SPORT0_MRCS1           		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
    254. 

  254. #define SPORT0_MRCS2           		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
    255. 

  255. #define SPORT0_MRCS3           		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
    256. 

  256. 

  257. /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
    258. 

  258. #define SPORT1_TCR1     	 		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
    259. 

  259. #define SPORT1_TCR2      	 		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
    260. 

  260. #define SPORT1_TCLKDIV        		0xFFC00908	/* SPORT1 Transmit Clock Divider */
    261. 

  261. #define SPORT1_TFSDIV          		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
    262. 

  262. #define SPORT1_TX	             	0xFFC00910	/* SPORT1 TX Data Register */
    263. 

  263. #define SPORT1_RX	            	0xFFC00918	/* SPORT1 RX Data Register */
    264. 

  264. #define SPORT1_RCR1      	 		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
    265. 

  265. #define SPORT1_RCR2      	 		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
    266. 

  266. #define SPORT1_RCLKDIV        		0xFFC00928	/* SPORT1 Receive Clock Divider */
    267. 

  267. #define SPORT1_RFSDIV          		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
    268. 

  268. #define SPORT1_STAT            		0xFFC00930	/* SPORT1 Status Register */
    269. 

  269. #define SPORT1_CHNL            		0xFFC00934	/* SPORT1 Current Channel Register */
    270. 

  270. #define SPORT1_MCMC1           		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
    271. 

  271. #define SPORT1_MCMC2           		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
    272. 

  272. #define SPORT1_MTCS0           		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
    273. 

  273. #define SPORT1_MTCS1           		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
    274. 

  274. #define SPORT1_MTCS2           		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
    275. 

  275. #define SPORT1_MTCS3           		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
    276. 

  276. #define SPORT1_MRCS0           		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
    277. 

  277. #define SPORT1_MRCS1           		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
    278. 

  278. #define SPORT1_MRCS2           		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
    279. 

  279. #define SPORT1_MRCS3           		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
    280. 

  280. 

  281. /* Asynchronous Memory Controller - External Bus Interface Unit  */
    282. 

  282. #define EBIU_AMGCTL					0xFFC00A00	/* Asynchronous Memory Global Control Register */
    283. 

  283. #define EBIU_AMBCTL0				0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
    284. 

  284. #define EBIU_AMBCTL1				0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
    285. 

  285. 

  286. /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
    287. 

  287. #define EBIU_SDGCTL					0xFFC00A10	/* SDRAM Global Control Register */
    288. 

  288. #define EBIU_SDBCTL					0xFFC00A14	/* SDRAM Bank Control Register */
    289. 

  289. #define EBIU_SDRRC 					0xFFC00A18	/* SDRAM Refresh Rate Control Register */
    290. 

  290. #define EBIU_SDSTAT					0xFFC00A1C	/* SDRAM Status Register */
    291. 

  291. 

  292. /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
    293. 

  293. #define PPI0_CONTROL 				0xFFC01000	/* PPI0 Control register */
    294. 

  294. #define PPI0_STATUS 				0xFFC01004	/* PPI0 Status register */
    295. 

  295. #define PPI0_COUNT 					0xFFC01008	/* PPI0 Transfer Count register */
    296. 

  296. #define PPI0_DELAY 					0xFFC0100C	/* PPI0 Delay Count register */
    297. 

  297. #define PPI0_FRAME 					0xFFC01010	/* PPI0 Frame Length register */
    298. 

  298. 

  299. /*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
    300. 

  300. #define PPI1_CONTROL 				0xFFC01300	/* PPI1 Control register */
    301. 

  301. #define PPI1_STATUS 				0xFFC01304	/* PPI1 Status register */
    302. 

  302. #define PPI1_COUNT 					0xFFC01308	/* PPI1 Transfer Count register */
    303. 

  303. #define PPI1_DELAY 					0xFFC0130C	/* PPI1 Delay Count register */
    304. 

  304. #define PPI1_FRAME 					0xFFC01310	/* PPI1 Frame Length register */
    305. 

  305. 

  306. /*DMA traffic control registers */
    307.