aiot/waterDataDiscreteRateMining/monitoringDataProcessing/connectionSignalSlot.h

/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
 *
 * Copyright (c) 2000-2001	Lineo Inc. <www.lineo.com>
 * Copyright (c) 2000-2001	Lineo Canada Corp. <www.lineo.ca>
 * Copyright (C) 1999		Vladimir Gurevich <vgurevic@cisco.com>
 * 				Bare & Hare Software, Inc.
 * Based on include/asm-m68knommu/MC68332.h
 * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
 *                     The Silver Hammer Group, Ltd.
 *
 * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
 * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
 */

#ifndef _MC68VZ328_H_
#define _MC68VZ328_H_

#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define LONG_REF(addr) (*((volatile unsigned long*)addr))

#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)

/********** 
 *
 * 0xFFFFF0xx -- System Control
 *
 **********/
 
/*
 * System Control Register (SCR)
 */
#define SCR_ADDR	0xfffff000
#define SCR		BYTE_REF(SCR_ADDR)

#define SCR_WDTH8	0x01	/* 8-Bit Width Select */
#define SCR_DMAP	0x04	/* Double Map */
#define SCR_SO		0x08	/* Supervisor Only */
#define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
#define SCR_PRV		0x20	/* Privilege Violation */
#define SCR_WPV		0x40	/* Write Protect Violation */
#define SCR_BETO	0x80	/* Bus-Error TimeOut */

/*
 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
 */
#define MRR_ADDR 0xfffff004
#define MRR	 LONG_REF(MRR_ADDR)

/********** 
 *
 * 0xFFFFF1xx -- Chip-Select logic
 *
 **********/
 
/*
 * Chip Select Group Base Registers 
 */
#define CSGBA_ADDR	0xfffff100
#define CSGBB_ADDR	0xfffff102

#define CSGBC_ADDR	0xfffff104
#define CSGBD_ADDR	0xfffff106

#define CSGBA		WORD_REF(CSGBA_ADDR)
#define CSGBB		WORD_REF(CSGBB_ADDR)
#define CSGBC		WORD_REF(CSGBC_ADDR)
#define CSGBD		WORD_REF(CSGBD_ADDR)

/*
 * Chip Select Registers 
 */
#define CSA_ADDR	0xfffff110
#define CSB_ADDR	0xfffff112
#define CSC_ADDR	0xfffff114
#define CSD_ADDR	0xfffff116

#define CSA		WORD_REF(CSA_ADDR)
#define CSB		WORD_REF(CSB_ADDR)
#define CSC		WORD_REF(CSC_ADDR)
#define CSD		WORD_REF(CSD_ADDR)

#define CSA_EN		0x0001		/* Chip-Select Enable */
#define CSA_SIZ_MASK	0x000e		/* Chip-Select Size */
#define CSA_SIZ_SHIFT   1
#define CSA_WS_MASK	0x0070		/* Wait State */
#define CSA_WS_SHIFT    4
#define CSA_BSW		0x0080		/* Data Bus Width */
#define CSA_FLASH	0x0100		/* FLASH Memory Support */
#define CSA_RO		0x8000		/* Read-Only */

#define CSB_EN		0x0001		/* Chip-Select Enable */
#define CSB_SIZ_MASK	0x000e		/* Chip-Select Size */
#define CSB_SIZ_SHIFT   1
#define CSB_WS_MASK	0x0070		/* Wait State */
#define CSB_WS_SHIFT    4
#define CSB_BSW		0x0080		/* Data Bus Width */
#define CSB_FLASH	0x0100		/* FLASH Memory Support */
#define CSB_UPSIZ_MASK	0x1800		/* Unprotected memory block size */
#define CSB_UPSIZ_SHIFT 11
#define CSB_ROP		0x2000		/* Readonly if protected */
#define CSB_SOP		0x4000		/* Supervisor only if protected */
#define CSB_RO		0x8000		/* Read-Only */

#define CSC_EN		0x0001		/* Chip-Select Enable */
#define CSC_SIZ_MASK	0x000e		/* Chip-Select Size */
#define CSC_SIZ_SHIFT   1
#define CSC_WS_MASK	0x0070		/* Wait State */
#define CSC_WS_SHIFT    4
#define CSC_BSW		0x0080		/* Data Bus Width */
#define CSC_FLASH	0x0100		/* FLASH Memory Support */
#define CSC_UPSIZ_MASK	0x1800		/* Unprotected memory block size */
#define CSC_UPSIZ_SHIFT 11
#define CSC_ROP		0x2000		/* Readonly if protected */
#define CSC_SOP		0x4000		/* Supervisor only if protected */
#define CSC_RO		0x8000		/* Read-Only */

#define CSD_EN		0x0001		/* Chip-Select Enable */
#define CSD_SIZ_MASK	0x000e		/* Chip-Select Size */
#define CSD_SIZ_SHIFT   1
#define CSD_WS_MASK	0x0070		/* Wait State */
#define CSD_WS_SHIFT    4