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- /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
- *
- * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
- * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- * Bare & Hare Software, Inc.
- * Based on include/asm-m68knommu/MC68332.h
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
- * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
- */
- #ifndef _MC68VZ328_H_
- #define _MC68VZ328_H_
- #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
- #define WORD_REF(addr) (*((volatile unsigned short*)addr))
- #define LONG_REF(addr) (*((volatile unsigned long*)addr))
- #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
- #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
- /**********
- *
- * 0xFFFFF0xx -- System Control
- *
- **********/
-
- /*
- * System Control Register (SCR)
- */
- #define SCR_ADDR 0xfffff000
- #define SCR BYTE_REF(SCR_ADDR)
- #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
- #define SCR_DMAP 0x04 /* Double Map */
- #define SCR_SO 0x08 /* Supervisor Only */
- #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
- #define SCR_PRV 0x20 /* Privilege Violation */
- #define SCR_WPV 0x40 /* Write Protect Violation */
- #define SCR_BETO 0x80 /* Bus-Error TimeOut */
- /*
- * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
- */
- #define MRR_ADDR 0xfffff004
- #define MRR LONG_REF(MRR_ADDR)
- /**********
- *
- * 0xFFFFF1xx -- Chip-Select logic
- *
- **********/
-
- /*
- * Chip Select Group Base Registers
- */
- #define CSGBA_ADDR 0xfffff100
- #define CSGBB_ADDR 0xfffff102
- #define CSGBC_ADDR 0xfffff104
- #define CSGBD_ADDR 0xfffff106
- #define CSGBA WORD_REF(CSGBA_ADDR)
- #define CSGBB WORD_REF(CSGBB_ADDR)
- #define CSGBC WORD_REF(CSGBC_ADDR)
- #define CSGBD WORD_REF(CSGBD_ADDR)
- /*
- * Chip Select Registers
- */
- #define CSA_ADDR 0xfffff110
- #define CSB_ADDR 0xfffff112
- #define CSC_ADDR 0xfffff114
- #define CSD_ADDR 0xfffff116
- #define CSA WORD_REF(CSA_ADDR)
- #define CSB WORD_REF(CSB_ADDR)
- #define CSC WORD_REF(CSC_ADDR)
- #define CSD WORD_REF(CSD_ADDR)
- #define CSA_EN 0x0001 /* Chip-Select Enable */
- #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
- #define CSA_SIZ_SHIFT 1
- #define CSA_WS_MASK 0x0070 /* Wait State */
- #define CSA_WS_SHIFT 4
- #define CSA_BSW 0x0080 /* Data Bus Width */
- #define CSA_FLASH 0x0100 /* FLASH Memory Support */
- #define CSA_RO 0x8000 /* Read-Only */
- #define CSB_EN 0x0001 /* Chip-Select Enable */
- #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
- #define CSB_SIZ_SHIFT 1
- #define CSB_WS_MASK 0x0070 /* Wait State */
- #define CSB_WS_SHIFT 4
- #define CSB_BSW 0x0080 /* Data Bus Width */
- #define CSB_FLASH 0x0100 /* FLASH Memory Support */
- #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
- #define CSB_UPSIZ_SHIFT 11
- #define CSB_ROP 0x2000 /* Readonly if protected */
- #define CSB_SOP 0x4000 /* Supervisor only if protected */
- #define CSB_RO 0x8000 /* Read-Only */
- #define CSC_EN 0x0001 /* Chip-Select Enable */
- #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
- #define CSC_SIZ_SHIFT 1
- #define CSC_WS_MASK 0x0070 /* Wait State */
- #define CSC_WS_SHIFT 4
- #define CSC_BSW 0x0080 /* Data Bus Width */
- #define CSC_FLASH 0x0100 /* FLASH Memory Support */
- #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
- #define CSC_UPSIZ_SHIFT 11
- #define CSC_ROP 0x2000 /* Readonly if protected */
- #define CSC_SOP 0x4000 /* Supervisor only if protected */
- #define CSC_RO 0x8000 /* Read-Only */
- #define CSD_EN 0x0001 /* Chip-Select Enable */
- #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
- #define CSD_SIZ_SHIFT 1
- #define CSD_WS_MASK 0x0070 /* Wait State */
- #define CSD_WS_SHIFT 4
- #define CSD_BSW 0x0080 /* Data Bus Width */
- #define CSD_FLASH 0x0100 /* FLASH Memory Support */
- #define CSD_DRAM 0x0200 /* Dram Selection */
- #define CSD_COMB 0x0400 /* Combining */
- #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
- #define CSD_UPSIZ_SHIFT 11
- #define CSD_ROP 0x2000 /* Readonly if protected */
- #define CSD_SOP 0x4000 /* Supervisor only if protected */
- #define CSD_RO 0x8000 /* Read-Only */
- /*
- * Emulation Chip-Select Register
- */
- #define EMUCS_ADDR 0xfffff118
- #define EMUCS WORD_REF(EMUCS_ADDR)
- #define EMUCS_WS_MASK 0x0070
- #define EMUCS_WS_SHIFT 4
- /**********
- *
- * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
- *
- **********/
- /*
- * PLL Control Register
- */
- #define PLLCR_ADDR 0xfffff200
- #define PLLCR WORD_REF(PLLCR_ADDR)
- #define PLLCR_DISPLL 0x0008 /* Disable PLL */
- #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
- #define PLLCR_PRESC 0x0020 /* VCO prescaler */
- #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
- #define PLLCR_SYSCLK_SEL_SHIFT 8
- #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
- #define PLLCR_LCDCLK_SEL_SHIFT 11
- /* '328-compatible definitions */
- #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
- #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
- /*
- * PLL Frequency Select Register
- */
- #define PLLFSR_ADDR 0xfffff202
- #define PLLFSR WORD_REF(PLLFSR_ADDR)
- #define PLLFSR_PC_MASK 0x00ff /* P Count */
- #define PLLFSR_PC_SHIFT 0
- #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
- #define PLLFSR_QC_SHIFT 8
- #define PLLFSR_PROT 0x4000 /* Protect P & Q */
- #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
- /*
- * Power Control Register
- */
- #define PCTRL_ADDR 0xfffff207
- #define PCTRL BYTE_REF(PCTRL_ADDR)
- #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
- #define PCTRL_WIDTH_SHIFT 0
- #define PCTRL_PCEN 0x80 /* Power Control Enable */
- /**********
- *
- * 0xFFFFF3xx -- Interrupt Controller
- *
- **********/
- /*
- * Interrupt Vector Register
- */
- #define IVR_ADDR 0xfffff300
- #define IVR BYTE_REF(IVR_ADDR)
- #define IVR_VECTOR_MASK 0xF8
- /*
- * Interrupt control Register
- */
- #define ICR_ADDR 0xfffff302
- #define ICR WORD_REF(ICR_ADDR)
- #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
- #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
- #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
- #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
- #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
- #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
- #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
- #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
- #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
- /*
- * Interrupt Mask Register
- */
- #define IMR_ADDR 0xfffff304
- #define IMR LONG_REF(IMR_ADDR)
- /*
- * Define the names for bit positions first. This is useful for
- * request_irq
- */
- #define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
- #define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
- #define UART1_IRQ_NUM 2 /* UART 1 interrupt */
- #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
- #define RTC_IRQ_NUM 4 /* RTC interrupt */
- #define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
- #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
- #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
- #define INT0_IRQ_NUM 8 /* External INT0 */
- #define INT1_IRQ_NUM 9 /* External INT1 */
- #define INT2_IRQ_NUM 10 /* External INT2 */
- #define INT3_IRQ_NUM 11 /* External INT3 */
- #define UART2_IRQ_NUM 12 /* UART 2 interrupt */
- #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
- #define IRQ1_IRQ_NUM 16 /* IRQ1 */
- #define IRQ2_IRQ_NUM 17 /* IRQ2 */
- #define IRQ3_IRQ_NUM 18 /* IRQ3 */
- #define IRQ6_IRQ_NUM 19 /* IRQ6 */
- #define IRQ5_IRQ_NUM 20 /* IRQ5 */
- #define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
- #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
- #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
- #define SPI_IRQ_NUM SPI2_IRQ_NUM
- /* '328-compatible definitions */
- #define SPIM_IRQ_NUM SPI_IRQ_NUM
- #define TMR1_IRQ_NUM TMR_IRQ_NUM
- #define UART_IRQ_NUM UART1_IRQ_NUM
- /*
- * Here go the bitmasks themselves
- */
- #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
- #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
- #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
- #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
- #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
- #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
- #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
- #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
- #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
- #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
- #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
- #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
- #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
- #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
- #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
- #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
- #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
- #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
- /* '328-compatible definitions */
- #define IMR_MSPIM IMR_MSPI
- #define IMR_MTMR1 IMR_MTMR
- /*
- * Interrupt Status Register
- */
- #define ISR_ADDR 0xfffff30c
- #define ISR LONG_REF(ISR_ADDR)
- #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
- #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
- #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
- #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
- #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
- #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
- #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
- #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
- #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
- #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
- #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
- #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
- #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
- #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
- #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
- #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
- #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
- #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
- /* '328-compatible definitions */
- #define ISR_SPIM ISR_SPI
- #define ISR_TMR1 ISR_TMR
- /*
- * Interrupt Pending Register
- */
- #define IPR_ADDR 0xfffff30c
- #define IPR LONG_REF(IPR_ADDR)
- #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
- #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
- #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
- #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
- #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
- #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
- #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
- #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
- #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
- #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
- #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
- #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
- #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
- #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
- #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
- #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
- #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
- #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
- /* '328-compatible definitions */
- #define IPR_SPIM IPR_SPI
- #define IPR_TMR1 IPR_TMR
- /**********
- *
- * 0xFFFFF4xx -- Parallel Ports
- *
- **********/
- /*
- * Port A
- */
- #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
- #define PADATA_ADDR 0xfffff401 /* Port A data register */
- #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
- #define PADIR BYTE_REF(PADIR_ADDR)
- #define PADATA BYTE_REF(PADATA_ADDR)
- #define PAPUEN BYTE_REF(PAPUEN_ADDR)
- #define PA(x) (1 << (x))
- /*
- * Port B
- */
- #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
- #define PBDATA_ADDR 0xfffff409 /* Port B data register */
- #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
- #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
- #define PBDIR BYTE_REF(PBDIR_ADDR)
- #define PBDATA BYTE_REF(PBDATA_ADDR)
- #define PBPUEN BYTE_REF(PBPUEN_ADDR)
- #define PBSEL BYTE_REF(PBSEL_ADDR)
- #define PB(x) (1 << (x))
- #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
- #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
- #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
- #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
- #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
- #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
- #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
- #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
- /*
- * Port C
- */
- #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
- #define PCDATA_ADDR 0xfffff411 /* Port C data register */
- #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
- #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
- #define PCDIR BYTE_REF(PCDIR_ADDR)
- #define PCDATA BYTE_REF(PCDATA_ADDR)
- #define PCPDEN BYTE_REF(PCPDEN_ADDR)
- #define PCSEL BYTE_REF(PCSEL_ADDR)
- #define PC(x) (1 << (x))
- #define PC_LD0 0x01 /* Use LD0 as PC[0] */
- #define PC_LD1 0x02 /* Use LD1 as PC[1] */
- #define PC_LD2 0x04 /* Use LD2 as PC[2] */
- #define PC_LD3 0x08 /* Use LD3 as PC[3] */
- #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
- #define PC_LLP 0x20 /* Use LLP as PC[5] */
- #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
- #define PC_LACD 0x80 /* Use LACD as PC[7] */
- /*
- * Port D
- */
- #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
- #define PDDATA_ADDR 0xfffff419 /* Port D data register */
- #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
- #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
- #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
- #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
- #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
- #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
- #define PDDIR BYTE_REF(PDDIR_ADDR)
- #define PDDATA BYTE_REF(PDDATA_ADDR)
- #define PDPUEN BYTE_REF(PDPUEN_ADDR)
- #define PDSEL BYTE_REF(PDSEL_ADDR)
- #define PDPOL BYTE_REF(PDPOL_ADDR)
- #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
- #define PDKBEN BYTE_REF(PDKBEN_ADDR)
- #define PDIQEG BYTE_REF(PDIQEG_ADDR)
- #define PD(x) (1 << (x))
- #define PD_INT0 0x01 /* Use INT0 as PD[0] */
- #define PD_INT1 0x02 /* Use INT1 as PD[1] */
- #define PD_INT2 0x04 /* Use INT2 as PD[2] */
- #define PD_INT3 0x08 /* Use INT3 as PD[3] */
- #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
- #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
- #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
- #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
- /*
- * Port E
- */
- #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
- #define PEDATA_ADDR 0xfffff421 /* Port E data register */
- #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
- #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
- #define PEDIR BYTE_REF(PEDIR_ADDR)
- #define PEDATA BYTE_REF(PEDATA_ADDR)
- #define PEPUEN BYTE_REF(PEPUEN_ADDR)
- #define PESEL BYTE_REF(PESEL_ADDR)
- #define PE(x) (1 << (x))
- #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
- #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
- #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
- #define PE_DWE 0x08 /* Use DWE as PE[3] */
- #define PE_RXD 0x10 /* Use RXD as PE[4] */
- #define PE_TXD 0x20 /* Use TXD as PE[5] */
- #define PE_RTS 0x40 /* Use RTS as PE[6] */
- #define PE_CTS 0x80 /* Use CTS as PE[7] */
- /*
- * Port F
- */
- #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
- #define PFDATA_ADDR 0xfffff429 /* Port F data register */
- #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
- #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
- #define PFDIR BYTE_REF(PFDIR_ADDR)
- #define PFDATA BYTE_REF(PFDATA_ADDR)
- #define PFPUEN BYTE_REF(PFPUEN_ADDR)
- #define PFSEL BYTE_REF(PFSEL_ADDR)
- #define PF(x) (1 << (x))
- #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
- #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
- #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
- #define PF_A20 0x08 /* Use A20 as PF[3] */
- #define PF_A21 0x10 /* Use A21 as PF[4] */
- #define PF_A22 0x20 /* Use A22 as PF[5] */
- #define PF_A23 0x40 /* Use A23 as PF[6] */
- #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
- /*
- * Port G
- */
- #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
- #define PGDATA_ADDR 0xfffff431 /* Port G data register */
- #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
- #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
- #define PGDIR BYTE_REF(PGDIR_ADDR)
- #define PGDATA BYTE_REF(PGDATA_ADDR)
- #define PGPUEN BYTE_REF(PGPUEN_ADDR)
- #define PGSEL BYTE_REF(PGSEL_ADDR)
- #define PG(x) (1 << (x))
- #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
- #define PG_A0 0x02 /* Use A0 as PG[1] */
- #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
- #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
- #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
- #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
- /*
- * Port J
- */
- #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
- #define PJDATA_ADDR 0xfffff439 /* Port J data register */
- #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
- #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
- #define PJDIR BYTE_REF(PJDIR_ADDR)
- #define PJDATA BYTE_REF(PJDATA_ADDR)
- #define PJPUEN BYTE_REF(PJPUEN_ADDR)
- #define PJSEL BYTE_REF(PJSEL_ADDR)
- #define PJ(x) (1 << (x))
- /*
- * Port K
- */
- #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
- #define PKDATA_ADDR 0xfffff441 /* Port K data register */
- #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
- #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
- #define PKDIR BYTE_REF(PKDIR_ADDR)
- #define PKDATA BYTE_REF(PKDATA_ADDR)
- #define PKPUEN BYTE_REF(PKPUEN_ADDR)
- #define PKSEL BYTE_REF(PKSEL_ADDR)
- #define PK(x) (1 << (x))
- #define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
- #define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
- #define PK_R_W 0x02 /* Use R/W as PK[1] */
- #define PK_LDS 0x04 /* Use /LDS as PK[2] */
- #define PK_UDS 0x08 /* Use /UDS as PK[3] */
- #define PK_LD4 0x10 /* Use LD4 as PK[4] */
- #define PK_LD5 0x20 /* Use LD5 as PK[5] */
- #define PK_LD6 0x40 /* Use LD6 as PK[6] */
- #define PK_LD7 0x80 /* Use LD7 as PK[7] */
- #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
- #define PJDATA_ADDR 0xfffff439 /* Port J data register */
- #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
- #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
- #define PJDIR BYTE_REF(PJDIR_ADDR)
- #define PJDATA BYTE_REF(PJDATA_ADDR)
- #define PJPUEN BYTE_REF(PJPUEN_ADDR)
- #define PJSEL BYTE_REF(PJSEL_ADDR)
- #define PJ(x) (1 << (x))
- #define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
- #define PJ_MISO 0x02 /* Use MISO as PJ[1] */
- #define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
- #define PJ_SS 0x08 /* Use SS as PJ[3] */
- #define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
- #define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
- #define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
- #define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
- /*
- * Port M
- */
- #define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
- #define PMDATA_ADDR 0xfffff449 /* Port M data register */
- #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
- #define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
- #define PMDIR BYTE_REF(PMDIR_ADDR)
- #define PMDATA BYTE_REF(PMDATA_ADDR)
- #define PMPUEN BYTE_REF(PMPUEN_ADDR)
- #define PMSEL BYTE_REF(PMSEL_ADDR)
- #define PM(x) (1 << (x))
- #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
- #define PM_SDCE 0x02 /* Use SDCE as PM[1] */
- #define PM_DQMH 0x04 /* Use DQMH as PM[2] */
- #define PM_DQML 0x08 /* Use DQML as PM[3] */
- #define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
- #define PM_DMOE 0x20 /* Use DMOE as PM[5] */
- /**********
- *
- * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
- *
- **********/
- /*
- * PWM Control Register
- */
- #define PWMC_ADDR 0xfffff500
- #define PWMC WORD_REF(PWMC_ADDR)
- #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
- #define PWMC_CLKSEL_SHIFT 0
- #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
- #define PWMC_REPEAT_SHIFT 2
- #define PWMC_EN 0x0010 /* Enable PWM */
- #define PMNC_FIFOAV 0x0020 /* FIFO Available */
- #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
- #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
- #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
- #define PWMC_PRESCALER_SHIFT 8
- #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
- /* '328-compatible definitions */
- #define PWMC_PWMEN PWMC_EN
- /*
- * PWM Sample Register
- */
- #define PWMS_ADDR 0xfffff502
- #define PWMS WORD_REF(PWMS_ADDR)
- /*
- * PWM Period Register
- */
- #define PWMP_ADDR 0xfffff504
- #define PWMP BYTE_REF(PWMP_ADDR)
- /*
- * PWM Counter Register
- */
- #define PWMCNT_ADDR 0xfffff505
- #define PWMCNT BYTE_REF(PWMCNT_ADDR)
- /**********
- *
- * 0xFFFFF6xx -- General-Purpose Timer
- *
- **********/
- /*
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