aiot/waterDataDiscreteRateMining/averageCalculation/synchronousMemoryDatabase.c

/*
 * sh73a0 processor support - PFC hardware block
 *
 * Copyright (C) 2010 Renesas Solutions Corp.
 * Copyright (C) 2010 NISHIMOTO Hiroki
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sh_pfc.h>
#include <mach/sh73a0.h>
#include <mach/irqs.h>

#define CPU_ALL_PORT(fn, pfx, sfx)				\
	PORT_10(fn, pfx,    sfx), PORT_10(fn, pfx##1, sfx),	\
	PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx),	\
	PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx),	\
	PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx),	\
	PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx),	\
	PORT_10(fn, pfx##10, sfx),				\
	PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),	\
	PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),	\
	PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),	\
	PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),	\
	PORT_1(fn, pfx##118, sfx),				\
	PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),	\
	PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),	\
	PORT_10(fn, pfx##15, sfx),				\
	PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),	\
	PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),	\
	PORT_1(fn, pfx##164, sfx),				\
	PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),	\
	PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),	\
	PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),	\
	PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),	\
	PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),	\
	PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),	\
	PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),	\
	PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx),	\
	PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx),	\
	PORT_1(fn, pfx##282, sfx),				\
	PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx),	\
	PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)

enum {
	PINMUX_RESERVED = 0,

	PINMUX_DATA_BEGIN,
	PORT_ALL(DATA),			/* PORT0_DATA -> PORT309_DATA */
	PINMUX_DATA_END,

	PINMUX_INPUT_BEGIN,
	PORT_ALL(IN),			/* PORT0_IN -> PORT309_IN */
	PINMUX_INPUT_END,

	PINMUX_INPUT_PULLUP_BEGIN,
	PORT_ALL(IN_PU),		/* PORT0_IN_PU -> PORT309_IN_PU */
	PINMUX_INPUT_PULLUP_END,

	PINMUX_INPUT_PULLDOWN_BEGIN,
	PORT_ALL(IN_PD),		/* PORT0_IN_PD -> PORT309_IN_PD */
	PINMUX_INPUT_PULLDOWN_END,

	PINMUX_OUTPUT_BEGIN,
	PORT_ALL(OUT),			/* PORT0_OUT -> PORT309_OUT */
	PINMUX_OUTPUT_END,

	PINMUX_FUNCTION_BEGIN,
	PORT_ALL(FN_IN),		/* PORT0_FN_IN -> PORT309_FN_IN */
	PORT_ALL(FN_OUT),		/* PORT0_FN_OUT -> PORT309_FN_OUT */
	PORT_ALL(FN0),			/* PORT0_FN0 -> PORT309_FN0 */
	PORT_ALL(FN1),			/* PORT0_FN1 -> PORT309_FN1 */
	PORT_ALL(FN2),			/* PORT0_FN2 -> PORT309_FN2 */
	PORT_ALL(FN3),			/* PORT0_FN3 -> PORT309_FN3 */
	PORT_ALL(FN4),			/* PORT0_FN4 -> PORT309_FN4 */
	PORT_ALL(FN5),			/* PORT0_FN5 -> PORT309_FN5 */
	PORT_ALL(FN6),			/* PORT0_FN6 -> PORT309_FN6 */
	PORT_ALL(FN7),			/* PORT0_FN7 -> PORT309_FN7 */

	MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
	MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
	MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
	MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
	MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
	MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
	MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
	MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
	MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
	MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
	MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
	MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
	MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
	MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
	MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
	MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
	MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
	MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
	MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
	MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
	MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
	MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
	MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
	MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
	MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
	MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
	MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
	MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
	MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
	MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
	MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
	MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
	MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
	MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
	MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
	MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
	MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
	MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
	MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
	MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
	MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
	MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
	PINMUX_FUNCTION_END,

	PINMUX_MARK_BEGIN,
	/* Hardware manual Table 25-1 (Function 0-7) */
	VBUS_0_MARK,
	GPI0_MARK,
	GPI1_MARK,
	GPI2_MARK,
	GPI3_MARK,
	GPI4_MARK,
	GPI5_MARK,
	GPI6_MARK,
	GPI7_MARK,
	SCIFA7_RXD_MARK,
	SCIFA7_CTS__MARK,
	GPO7_MARK, MFG0_OUT2_MARK,
	GPO6_MARK, MFG1_OUT2_MARK,
	GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
	SCIFA0_TXD_MARK,
	SCIFA7_TXD_MARK,
	SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
	GPO0_MARK,
	GPO1_MARK,
	GPO2_MARK, STATUS0_MARK,
	GPO3_MARK, STATUS1_MARK,
	GPO4_MARK, STATUS2_MARK,
	VINT_MARK,
	TCKON_MARK,
	XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
	MFG0_OUT1_MARK, PORT27_IROUT_MARK,
	XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
	PORT28_TPU1TO1_MARK,
	SIM_RST_MARK, PORT29_TPU1TO1_MARK,
	SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
	SIM_D_MARK, PORT31_IROUT_MARK,
	SCIFA4_TXD_MARK,
	SCIFA4_RXD_MARK, XWUP_MARK,
	SCIFA4_RTS__MARK,
	SCIFA4_CTS__MARK,
	FSIBOBT_MARK, FSIBIBT_MARK,
	FSIBOLR_MARK, FSIBILR_MARK,
	FSIBOSLD_MARK,
	FSIBISLD_MARK,
	VACK_MARK,
	XTAL1L_MARK,
	SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
	SCIFA0_RXD_MARK,
	SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
	FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
	FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
	FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
	FSICISLD_MARK, FSIDISLD_MARK,
	FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
	FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,

	FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
	FSIAOSLD_MARK, BBIF2_TXD2_MARK,
	FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
	PORT53_FSICSPDIF_MARK,