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main.c

main.c 6.7 KB
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  1. /* linux/arch/arm/mach-msm/board-trout-mddi.c
    2. 

  2. ** Author: Brian Swetland <swetland@google.com>
    3. 

  3. */
    4. 

  4. #include <linux/gpio.h>
    5. 

  5. #include <linux/kernel.h>
    6. 

  6. #include <linux/init.h>
    7. 

  7. #include <linux/platform_device.h>
    8. 

  8. #include <linux/delay.h>
    9. 

  9. #include <linux/leds.h>
    10. 

  10. #include <linux/clk.h>
    11. 

  11. #include <linux/err.h>
    12. 

  12. 

  13. #include <asm/io.h>
    14. 

  14. #include <asm/mach-types.h>
    15. 

  15. #include <asm/system_info.h>
    16. 

  16. 

  17. #include <linux/platform_data/video-msm_fb.h>
    18. 

  18. #include <mach/vreg.h>
    19. 

  19. 

  20. #include "board-trout.h"
    21. 

  21. #include "proc_comm.h"
    22. 

  22. #include "devices.h"
    23. 

  23. 

  24. #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
    25. 

  25. 

  26. #define MDDI_CLIENT_CORE_BASE  0x108000
    27. 

  27. #define LCD_CONTROL_BLOCK_BASE 0x110000
    28. 

  28. #define SPI_BLOCK_BASE         0x120000
    29. 

  29. #define I2C_BLOCK_BASE         0x130000
    30. 

  30. #define PWM_BLOCK_BASE         0x140000
    31. 

  31. #define GPIO_BLOCK_BASE        0x150000
    32. 

  32. #define SYSTEM_BLOCK1_BASE     0x160000
    33. 

  33. #define SYSTEM_BLOCK2_BASE     0x170000
    34. 

  34. 

  35. 

  36. #define	DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
    37. 

  37. #define	SYSCLKENA   (MDDI_CLIENT_CORE_BASE|0x2C)
    38. 

  38. #define	PWM0OFF	      (PWM_BLOCK_BASE|0x1C)
    39. 

  39. 

  40. #define V_VDDE2E_VDD2_GPIO 0
    41. 

  41. #define MDDI_RST_N 82
    42. 

  42. 

  43. #define	MDDICAP0    (MDDI_CLIENT_CORE_BASE|0x00)
    44. 

  44. #define	MDDICAP1    (MDDI_CLIENT_CORE_BASE|0x04)
    45. 

  45. #define	MDDICAP2    (MDDI_CLIENT_CORE_BASE|0x08)
    46. 

  46. #define	MDDICAP3    (MDDI_CLIENT_CORE_BASE|0x0C)
    47. 

  47. #define	MDCAPCHG    (MDDI_CLIENT_CORE_BASE|0x10)
    48. 

  48. #define	MDCRCERC    (MDDI_CLIENT_CORE_BASE|0x14)
    49. 

  49. #define	TTBUSSEL    (MDDI_CLIENT_CORE_BASE|0x18)
    50. 

  50. #define	DPSET0      (MDDI_CLIENT_CORE_BASE|0x1C)
    51. 

  51. #define	DPSET1      (MDDI_CLIENT_CORE_BASE|0x20)
    52. 

  52. #define	DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
    53. 

  53. #define	DPRUN       (MDDI_CLIENT_CORE_BASE|0x28)
    54. 

  54. #define	SYSCKENA    (MDDI_CLIENT_CORE_BASE|0x2C)
    55. 

  55. #define	TESTMODE    (MDDI_CLIENT_CORE_BASE|0x30)
    56. 

  56. #define	FIFOMONI    (MDDI_CLIENT_CORE_BASE|0x34)
    57. 

  57. #define	INTMONI     (MDDI_CLIENT_CORE_BASE|0x38)
    58. 

  58. #define	MDIOBIST    (MDDI_CLIENT_CORE_BASE|0x3C)
    59. 

  59. #define	MDIOPSET    (MDDI_CLIENT_CORE_BASE|0x40)
    60. 

  60. #define	BITMAP0     (MDDI_CLIENT_CORE_BASE|0x44)
    61. 

  61. #define	BITMAP1     (MDDI_CLIENT_CORE_BASE|0x48)
    62. 

  62. #define	BITMAP2     (MDDI_CLIENT_CORE_BASE|0x4C)
    63. 

  63. #define	BITMAP3     (MDDI_CLIENT_CORE_BASE|0x50)
    64. 

  64. #define	BITMAP4     (MDDI_CLIENT_CORE_BASE|0x54)
    65. 

  65. 

  66. #define	SRST        (LCD_CONTROL_BLOCK_BASE|0x00)
    67. 

  67. #define	PORT_ENB    (LCD_CONTROL_BLOCK_BASE|0x04)
    68. 

  68. #define	START       (LCD_CONTROL_BLOCK_BASE|0x08)
    69. 

  69. #define	PORT        (LCD_CONTROL_BLOCK_BASE|0x0C)
    70. 

  70. #define	CMN         (LCD_CONTROL_BLOCK_BASE|0x10)
    71. 

  71. #define	GAMMA       (LCD_CONTROL_BLOCK_BASE|0x14)
    72. 

  72. #define	INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
    73. 

  73. #define	INTMSK      (LCD_CONTROL_BLOCK_BASE|0x1C)
    74. 

  74. #define	MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
    75. 

  75. #define	HDE_LEFT    (LCD_CONTROL_BLOCK_BASE|0x24)
    76. 

  76. #define	VDE_TOP     (LCD_CONTROL_BLOCK_BASE|0x28)
    77. 

  77. #define	PXL         (LCD_CONTROL_BLOCK_BASE|0x30)
    78. 

  78. #define	HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
    79. 

  79. #define	HSW         (LCD_CONTROL_BLOCK_BASE|0x38)
    80. 

  80. #define	HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
    81. 

  81. #define	HDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x40)
    82. 

  82. #define	VCYCLE      (LCD_CONTROL_BLOCK_BASE|0x44)
    83. 

  83. #define	VSW         (LCD_CONTROL_BLOCK_BASE|0x48)
    84. 

  84. #define	VDE_START   (LCD_CONTROL_BLOCK_BASE|0x4C)
    85. 

  85. #define	VDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x50)
    86. 

  86. #define	WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
    87. 

  87. #define	WSYN_DLY    (LCD_CONTROL_BLOCK_BASE|0x58)
    88. 

  88. #define	REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
    89. 

  89. #define	VSYNIF      (LCD_CONTROL_BLOCK_BASE|0x60)
    90. 

  90. #define	WRSTB       (LCD_CONTROL_BLOCK_BASE|0x64)
    91. 

  91. #define	RDSTB       (LCD_CONTROL_BLOCK_BASE|0x68)
    92. 

  92. #define	ASY_DATA    (LCD_CONTROL_BLOCK_BASE|0x6C)
    93. 

  93. #define	ASY_DATB    (LCD_CONTROL_BLOCK_BASE|0x70)
    94. 

  94. #define	ASY_DATC    (LCD_CONTROL_BLOCK_BASE|0x74)
    95. 

  95. #define	ASY_DATD    (LCD_CONTROL_BLOCK_BASE|0x78)
    96. 

  96. #define	ASY_DATE    (LCD_CONTROL_BLOCK_BASE|0x7C)
    97. 

  97. #define	ASY_DATF    (LCD_CONTROL_BLOCK_BASE|0x80)
    98. 

  98. #define	ASY_DATG    (LCD_CONTROL_BLOCK_BASE|0x84)
    99. 

  99. #define	ASY_DATH    (LCD_CONTROL_BLOCK_BASE|0x88)
    100. 

  100. #define	ASY_CMDSET  (LCD_CONTROL_BLOCK_BASE|0x8C)
    101. 

  101. 

  102. #define	SSICTL      (SPI_BLOCK_BASE|0x00)
    103. 

  103. #define	SSITIME     (SPI_BLOCK_BASE|0x04)
    104. 

  104. #define	SSITX       (SPI_BLOCK_BASE|0x08)
    105. 

  105. #define	SSIRX       (SPI_BLOCK_BASE|0x0C)
    106. 

  106. #define	SSIINTC     (SPI_BLOCK_BASE|0x10)
    107. 

  107. #define	SSIINTS     (SPI_BLOCK_BASE|0x14)
    108. 

  108. #define	SSIDBG1     (SPI_BLOCK_BASE|0x18)
    109. 

  109. #define	SSIDBG2     (SPI_BLOCK_BASE|0x1C)
    110. 

  110. #define	SSIID       (SPI_BLOCK_BASE|0x20)
    111. 

  111. 

  112. #define	WKREQ       (SYSTEM_BLOCK1_BASE|0x00)
    113. 

  113. #define	CLKENB      (SYSTEM_BLOCK1_BASE|0x04)
    114. 

  114. #define	DRAMPWR     (SYSTEM_BLOCK1_BASE|0x08)
    115. 

  115. #define	INTMASK     (SYSTEM_BLOCK1_BASE|0x0C)
    116. 

  116. #define	GPIOSEL     (SYSTEM_BLOCK2_BASE|0x00)
    117. 

  117. 

  118. #define	GPIODATA    (GPIO_BLOCK_BASE|0x00)
    119. 

  119. #define	GPIODIR     (GPIO_BLOCK_BASE|0x04)
    120. 

  120. #define	GPIOIS      (GPIO_BLOCK_BASE|0x08)
    121. 

  121. #define	GPIOIBE     (GPIO_BLOCK_BASE|0x0C)
    122. 

  122. #define	GPIOIEV     (GPIO_BLOCK_BASE|0x10)
    123. 

  123. #define	GPIOIE      (GPIO_BLOCK_BASE|0x14)
    124. 

  124. #define	GPIORIS     (GPIO_BLOCK_BASE|0x18)
    125. 

  125. #define	GPIOMIS     (GPIO_BLOCK_BASE|0x1C)
    126. 

  126. #define	GPIOIC      (GPIO_BLOCK_BASE|0x20)
    127. 

  127. #define	GPIOOMS     (GPIO_BLOCK_BASE|0x24)
    128. 

  128. #define	GPIOPC      (GPIO_BLOCK_BASE|0x28)
    129. 

  129. #define	GPIOID      (GPIO_BLOCK_BASE|0x30)
    130. 

  130. 

  131. #define SPI_WRITE(reg, val) \
    132. 

  132. 	{ SSITX,        0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
    133. 

  133. 	{ 0, 5 },
    134. 

  134. 

  135. #define SPI_WRITE1(reg) \
    136. 

  136. 	{ SSITX,        (reg) & 0xff }, \
    137. 

  137. 	{ 0, 5 },
    138. 

  138. 

  139. struct mddi_table {
    140. 

  140. 	uint32_t reg;
    141. 

  141. 	uint32_t value;
    142. 

  142. };
    143. 

  143. static struct mddi_table mddi_toshiba_init_table[] = {
    144. 

  144. 	{ DPSET0,       0x09e90046 },
    145. 

  145. 	{ DPSET1,       0x00000118 },
    146. 

  146. 	{ DPSUS,        0x00000000 },
    147. 

  147. 	{ DPRUN,        0x00000001 },
    148. 

  148. 	{ 1,            14         }, /* msleep 14 */
    149. 

  149. 	{ SYSCKENA,     0x00000001 },
    150. 

  150. 	{ CLKENB,       0x0000A1EF },  /*    # SYS.CLKENB  # Enable clocks for each module (without DCLK , i2cCLK) */
    151. 

  151. 

  152. 	{ GPIODATA,     0x02000200 },  /*   # GPI .GPIODATA  # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
    153. 

  153. 	{ GPIODIR,      0x000030D  },  /* 24D   # GPI .GPIODIR  # Select direction of GPIO port (0,2,3,6,9 output) */
    154. 

  154. 	{ GPIOSEL,      0/*0x00000173*/},  /*   # SYS.GPIOSEL  # GPIO port multiplexing control */
    155. 

  155. 	{ GPIOPC,       0x03C300C0 },  /*   # GPI .GPIOPC  # GPIO2,3 PD cut */
    156. 

  156. 	{ WKREQ,        0x00000000 },  /*   # SYS.WKREQ  # Wake-up request event is VSYNC alignment */
    157. 

  157. 

  158. 	{ GPIOIBE,      0x000003FF },
    159. 

  159. 	{ GPIOIS,       0x00000000 },
    160. 

  160. 	{ GPIOIC,       0x000003FF },
    161. 

  161. 	{ GPIOIE,       0x00000000 },
    162. 

  162. 

  163. 	{ GPIODATA,     0x00040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
    164. 

  164. 	{ 1,            1          }, /* msleep 1 */
    165. 

  165. 	{ GPIODATA,     0x02040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
    166. 

  166. 	{ DRAMPWR,      0x00000001 }, /* eDRAM power */
    167. 

  167. };
    168. 

  168. 

  169. #define GPIOSEL_VWAKEINT (1U << 0)
    170. 

  170. #define INTMASK_VWAKEOUT (1U << 0)
    171. 

  171. 

  172. 

  173. static struct clk *gp_clk;
    174. 

  174. static int trout_new_backlight = 1;
    175. 

  175. static struct vreg *vreg_mddi_1v5;
    176. 

  176. static struct vreg *vreg_lcm_2v85;
    177. 

  177. 

  178. static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
    179. 

  179. 				     struct mddi_table *table, size_t count)
    180. 

  180. {
    181. 

  181. 	int i;
    182.