aiot/efDataStatistics/monitoringDataProcessing/connectTheSignalSlot.h

/*
 * arch/arm/mach-lpc32xx/include/mach/platform.h
 *
 * Author: Kevin Wells <kevin.wells@nxp.com>
 *
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __ASM_ARCH_PLATFORM_H
#define __ASM_ARCH_PLATFORM_H

#define _SBF(f, v)				((v) << (f))
#define _BIT(n)					_SBF(n, 1)

/*
 * AHB 0 physical base addresses
 */
#define LPC32XX_SLC_BASE			0x20020000
#define LPC32XX_SSP0_BASE			0x20084000
#define LPC32XX_SPI1_BASE			0x20088000
#define LPC32XX_SSP1_BASE			0x2008C000
#define LPC32XX_SPI2_BASE			0x20090000
#define LPC32XX_I2S0_BASE			0x20094000
#define LPC32XX_SD_BASE				0x20098000
#define LPC32XX_I2S1_BASE			0x2009C000
#define LPC32XX_MLC_BASE			0x200A8000
#define LPC32XX_AHB0_START			LPC32XX_SLC_BASE
#define LPC32XX_AHB0_SIZE			0x00089000

/*
 * AHB 1 physical base addresses
 */
#define LPC32XX_DMA_BASE			0x31000000
#define LPC32XX_USB_BASE			0x31020000
#define LPC32XX_USBH_BASE			0x31020000
#define LPC32XX_USB_OTG_BASE			0x31020000
#define LPC32XX_OTG_I2C_BASE			0x31020300
#define LPC32XX_LCD_BASE			0x31040000
#define LPC32XX_ETHERNET_BASE			0x31060000
#define LPC32XX_EMC_BASE			0x31080000
#define LPC32XX_ETB_CFG_BASE			0x310C0000
#define LPC32XX_ETB_DATA_BASE			0x310E0000
#define LPC32XX_AHB1_START			LPC32XX_DMA_BASE
#define LPC32XX_AHB1_SIZE			0x000E1000

/*
 * FAB physical base addresses
 */
#define LPC32XX_CLK_PM_BASE			0x40004000
#define LPC32XX_MIC_BASE			0x40008000
#define LPC32XX_SIC1_BASE			0x4000C000
#define LPC32XX_SIC2_BASE			0x40010000
#define LPC32XX_HS_UART1_BASE			0x40014000
#define LPC32XX_HS_UART2_BASE			0x40018000
#define LPC32XX_HS_UART7_BASE			0x4001C000
#define LPC32XX_RTC_BASE			0x40024000
#define LPC32XX_RTC_RAM_BASE			0x40024080
#define LPC32XX_GPIO_BASE			0x40028000
#define LPC32XX_PWM3_BASE			0x4002C000
#define LPC32XX_PWM4_BASE			0x40030000
#define LPC32XX_MSTIM_BASE			0x40034000
#define LPC32XX_HSTIM_BASE			0x40038000
#define LPC32XX_WDTIM_BASE			0x4003C000
#define LPC32XX_DEBUG_CTRL_BASE			0x40040000
#define LPC32XX_TIMER0_BASE			0x40044000
#define LPC32XX_ADC_BASE			0x40048000
#define LPC32XX_TIMER1_BASE			0x4004C000
#define LPC32XX_KSCAN_BASE			0x40050000
#define LPC32XX_UART_CTRL_BASE			0x40054000
#define LPC32XX_TIMER2_BASE			0x40058000
#define LPC32XX_PWM1_BASE			0x4005C000
#define LPC32XX_PWM2_BASE			0x4005C004
#define LPC32XX_TIMER3_BASE			0x40060000

/*
 * APB physical base addresses
 */
#define LPC32XX_UART3_BASE			0x40080000
#define LPC32XX_UART4_BASE			0x40088000
#define LPC32XX_UART5_BASE			0x40090000
#define LPC32XX_UART6_BASE			0x40098000
#define LPC32XX_I2C1_BASE			0x400A0000
#define LPC32XX_I2C2_BASE			0x400A8000

/*
 * FAB and APB base and sizing
 */
#define LPC32XX_FABAPB_START			LPC32XX_CLK_PM_BASE
#define LPC32XX_FABAPB_SIZE			0x000A5000

/*
 * Internal memory bases and sizes
 */
#define LPC32XX_IRAM_BASE			0x08000000
#define LPC32XX_IROM_BASE			0x0C000000

/*
 * External Static Memory Bank Address Space Bases
 */
#define LPC32XX_EMC_CS0_BASE			0xE0000000
#define LPC32XX_EMC_CS1_BASE			0xE1000000
#define LPC32XX_EMC_CS2_BASE			0xE2000000
#define LPC32XX_EMC_CS3_BASE			0xE3000000

/*
 * External SDRAM Memory Bank Address Space Bases
 */
#define LPC32XX_EMC_DYCS0_BASE			0x80000000
#define LPC32XX_EMC_DYCS1_BASE			0xA0000000

/*
 * Clock and crystal information
 */
#define LPC32XX_MAIN_OSC_FREQ			13000000
#define LPC32XX_CLOCK_OSC_FREQ			32768

/*
 * Clock and Power control register offsets
 */
#define _PMREG(x)				io_p2v(LPC32XX_CLK_PM_BASE +\
						(x))
#define LPC32XX_CLKPWR_DEBUG_CTRL		_PMREG(0x000)
#define LPC32XX_CLKPWR_BOOTMAP			_PMREG(0x014)
#define LPC32XX_CLKPWR_P01_ER			_PMREG(0x018)
#define LPC32XX_CLKPWR_USBCLK_PDIV		_PMREG(0x01C)
#define LPC32XX_CLKPWR_INT_ER			_PMREG(0x020)
#define LPC32XX_CLKPWR_INT_RS			_PMREG(0x024)
#define LPC32XX_CLKPWR_INT_SR			_PMREG(0x028)
#define LPC32XX_CLKPWR_INT_AP			_PMREG(0x02C)
#define LPC32XX_CLKPWR_PIN_ER			_PMREG(0x030)
#define LPC32XX_CLKPWR_PIN_RS			_PMREG(0x034)
#define LPC32XX_CLKPWR_PIN_SR			_PMREG(0x038)
#define LPC32XX_CLKPWR_PIN_AP			_PMREG(0x03C)
#define LPC32XX_CLKPWR_HCLK_DIV			_PMREG(0x040)
#define LPC32XX_CLKPWR_PWR_CTRL			_PMREG(0x044)
#define LPC32XX_CLKPWR_PLL397_CTRL		_PMREG(0x048)
#define LPC32XX_CLKPWR_MAIN_OSC_CTRL		_PMREG(0x04C)
#define LPC32XX_CLKPWR_SYSCLK_CTRL		_PMREG(0x050)
#define LPC32XX_CLKPWR_LCDCLK_CTRL		_PMREG(0x054)
#define LPC32XX_CLKPWR_HCLKPLL_CTRL		_PMREG(0x058)
#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1		_PMREG(0x060)
#define LPC32XX_CLKPWR_USB_CTRL			_PMREG(0x064)
#define LPC32XX_CLKPWR_SDRAMCLK_CTRL		_PMREG(0x068)
#define LPC32XX_CLKPWR_DDR_LAP_NOM		_PMREG(0x06C)
#define LPC32XX_CLKPWR_DDR_LAP_COUNT		_PMREG(0x070)
#define LPC32XX_CLKPWR_DDR_LAP_DELAY		_PMREG(0x074)
#define LPC32XX_CLKPWR_SSP_CLK_CTRL		_PMREG(0x078)
#define LPC32XX_CLKPWR_I2S_CLK_CTRL		_PMREG(0x07C)
#define LPC32XX_CLKPWR_MS_CTRL			_PMREG(0x080)
#define LPC32XX_CLKPWR_MACCLK_CTRL		_PMREG(0x090)
#define LPC32XX_CLKPWR_TEST_CLK_SEL		_PMREG(0x0A4)
#define LPC32XX_CLKPWR_SFW_INT			_PMREG(0x0A8)
#define LPC32XX_CLKPWR_I2C_CLK_CTRL		_PMREG(0x0AC)