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- /*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF525_H
- #define _DEF_BF525_H
- /* BF525 is BF522 + USB */
- #include "defBF522.h"
- /* USB Control Registers */
- #define USB_FADDR 0xffc03800 /* Function address register */
- #define USB_POWER 0xffc03804 /* Power management register */
- #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
- #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
- #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
- #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
- #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
- #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
- #define USB_FRAME 0xffc03820 /* USB frame number */
- #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
- #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
- #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
- #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
- /* USB Packet Control Registers */
- #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
- #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
- #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
- #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
- #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
- #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
- #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
- #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
- #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
- #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
- #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
- #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
- #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
- /* USB Endpoint FIFO Registers */
- #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
- #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
- #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
- #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
- #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
- #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
- #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
- #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
- /* USB OTG Control Registers */
- #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
- #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
- #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
- /* USB Phy Control Registers */
- #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
- #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
- #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
- #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
- #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
- /* (APHY_CNTRL is for ADI usage only) */
- #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
- /* (APHY_CALIB is for ADI usage only) */
- #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
- #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
- /* (PHY_TEST is for ADI usage only) */
- #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
- #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
- #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
- /* USB Endpoint 0 Control Registers */
- #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
- #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
- #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
- #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
- #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
- #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
- #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
- #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
- #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
- #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
- /* USB Endpoint 1 Control Registers */
- #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
- #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
- #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
- #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
- #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
- #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
- #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
- #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
- #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
- #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
- /* USB Endpoint 2 Control Registers */
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