lixinru
/
aiot


			
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							/*
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef _CDEF_BF60X_H
#define _CDEF_BF60X_H

/* ************************************************************** */
/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
/* ************************************************************** */

/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */

#define bfin_read_CHIPID()		bfin_read32(CHIPID)
#define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)

/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */

/* SEC0 Registers */
#define bfin_read_SEC0_CCTL()		bfin_read32(SEC0_CCTL)
#define bfin_write_SEC0_CCTL(val)	bfin_write32(SEC0_CCTL, val)
#define bfin_read_SEC0_CSID()		bfin_read32(SEC0_CSID)
#define bfin_write_SEC0_CSID(val)	bfin_write32(SEC0_CSID, val)
#define bfin_read_SEC_GCTL()		bfin_read32(SEC_GCTL)
#define bfin_write_SEC_GCTL(val)	bfin_write32(SEC_GCTL, val)

#define bfin_read_SEC_FCTL()		bfin_read32(SEC_FCTL)
#define bfin_write_SEC_FCTL(val)	bfin_write32(SEC_FCTL, val)

#define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC_SCTL0 + (sid) * 8))
#define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC_SCTL0 + (sid) * 8), val)

#define bfin_read_SEC_SSTAT(sid)	bfin_read32((SEC_SSTAT0 + (sid) * 8))
#define bfin_write_SEC_SSTAT(sid, val)	bfin_write32((SEC_SSTAT0 + (sid) * 8), val)

/* RCU0 Registers */
#define bfin_read_RCU0_CTL()		bfin_read32(RCU0_CTL)
#define bfin_write_RCU0_CTL(val)	bfin_write32(RCU0_CTL, val)

/* Watchdog Timer Registers */
#define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
#define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
#define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)

/* RTC Registers */

/* UART0 Registers */

#define bfin_read_UART0_REVID()		bfin_read32(UART0_REVID)
#define bfin_write_UART0_REVID(val)	bfin_write32(UART0_REVID, val)
#define bfin_read_UART0_GCTL()		bfin_read32(UART0_GCTL)
#define bfin_write_UART0_GCTL(val)	bfin_write32(UART0_GCTL, val)
#define bfin_read_UART0_STAT()		bfin_read32(UART0_STAT)
#define bfin_write_UART0_STAT(val)	bfin_write32(UART0_STAT, val)
#define bfin_read_UART0_SCR()		bfin_read32(UART0_SCR)
#define bfin_write_UART0_SCR(val)	bfin_write32(UART0_SCR, val)
#define bfin_read_UART0_CLK()		bfin_read32(UART0_CLK)
#define bfin_write_UART0_CLK(val)	bfin_write32(UART0_CLK, val)
#define bfin_read_UART0_IER()		bfin_read32(UART0_IER)
#define bfin_write_UART0_IER(val)	bfin_write32(UART0_IER, val)
#define bfin_read_UART0_IER_SET()	bfin_read32(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val)	bfin_write32(UART0_IER_SET, val)
#define bfin_read_UART0_IER_CLEAR()	bfin_read32(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val)	bfin_write32(UART0_IER_CLEAR, val)
#define bfin_read_UART0_RBR()		bfin_read32(UART0_RBR)
#define bfin_write_UART0_RBR(val)	bfin_write32(UART0_RBR, val)
#define bfin_read_UART0_THR()		bfin_read32(UART0_THR)
#define bfin_write_UART0_THR(val)	bfin_write32(UART0_THR, val)
#define bfin_read_UART0_TAIP()		bfin_read32(UART0_TAIP)
#define bfin_write_UART0_TAIP(val)	bfin_write32(UART0_TAIP, val)
#define bfin_read_UART0_TSR()		bfin_read32(UART0_TSR)
#define bfin_write_UART0_TSR(val)	bfin_write32(UART0_TSR, val)
#define bfin_read_UART0_RSR()		bfin_read32(UART0_RSR)
#define bfin_write_UART0_RSR(val)	bfin_write32(UART0_RSR, val)
#define bfin_read_UART0_TXCNT()		bfin_read32(UART0_TXCNT)
#define bfin_write_UART0_TXCNT(val)	bfin_write32(UART0_TXCNT, val)
#define bfin_read_UART0_RXCNT()		bfin_read32(UART0_RXCNT)
#define bfin_write_UART0_RXCNT(val)	bfin_write32(UART0_RXCNT, val)

/* UART1 Registers */

#define bfin_read_UART1_REVID()		bfin_read32(UART1_REVID)
#define bfin_write_UART1_REVID(val)	bfin_write32(UART1_REVID, val)
#define bfin_read_UART1_GCTL()		bfin_read32(UART1_GCTL)
#define bfin_write_UART1_GCTL(val)	bfin_write32(UART1_GCTL, val)
#define bfin_read_UART1_STAT()		bfin_read32(UART1_STAT)
#define bfin_write_UART1_STAT(val)	bfin_write32(UART1_STAT, val)
#define bfin_read_UART1_SCR()		bfin_read32(UART1_SCR)
#define bfin_write_UART1_SCR(val)	bfin_write32(UART1_SCR, val)
#define bfin_read_UART1_CLK()		bfin_read32(UART1_CLK)
#define bfin_write_UART1_CLK(val)	bfin_write32(UART1_CLK, val)
#define bfin_read_UART1_IER()		bfin_read32(UART1_IER)
#define bfin_write_UART1_IER(val)	bfin_write32(UART1_IER, val)
#define bfin_read_UART1_IER_SET()	bfin_read32(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val)	bfin_write32(UART1_IER_SET, val)
#define bfin_read_UART1_IER_CLEAR()	bfin_read32(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val)	bfin_write32(UART1_IER_CLEAR, val)
#define bfin_read_UART1_RBR()		bfin_read32(UART1_RBR)
#define bfin_write_UART1_RBR(val)	bfin_write32(UART1_RBR, val)
#define bfin_read_UART1_THR()		bfin_read32(UART1_THR)
#define bfin_write_UART1_THR(val)	bfin_write32(UART1_THR, val)
#define bfin_read_UART1_TAIP()		bfin_read32(UART1_TAIP)
#define bfin_write_UART1_TAIP(val)	bfin_write32(UART1_TAIP, val)
#define bfin_read_UART1_TSR()		bfin_read32(UART1_TSR)
#define bfin_write_UART1_TSR(val)	bfin_write32(UART1_TSR, val)
#define bfin_read_UART1_RSR()		bfin_read32(UART1_RSR)
#define bfin_write_UART1_RSR(val)	bfin_write32(UART1_RSR, val)
#define bfin_read_UART1_TXCNT()		bfin_read32(UART1_TXCNT)
#define bfin_write_UART1_TXCNT(val)	bfin_write32(UART1_TXCNT, val)
#define bfin_read_UART1_RXCNT()		bfin_read32(UART1_RXCNT)
#define bfin_write_UART1_RXCNT(val)	bfin_write32(UART1_RXCNT, val)


/* SPI0 Registers */

#define bfin_read_SPI0_CTL()		bfin_read32(SPI0_CTL)
#define bfin_write_SPI0_CTL(val)	bfin_write32(SPI0_CTL, val)
#define bfin_read_SPI0_RXCTL()		bfin_read32(SPI0_RXCTL)
#define bfin_write_SPI0_RXCTL(val)	bfin_write32(SPI0_RXCTL, val)
#define bfin_read_SPI0_TXCTL()		bfin_read32(SPI0_TXCTL)
#define bfin_write_SPI0_TXCTL(val)	bfin_write32(SPI0_TXCTL, val)
#define bfin_read_SPI0_CLK()		bfin_read32(SPI0_CLK)
#define bfin_write_SPI0_CLK(val)	bfin_write32(SPI0_CLK, val)
#define bfin_read_SPI0_DLY()		bfin_read32(SPI0_DLY)
#define bfin_write_SPI0_DLY(val)	bfin_write32(SPI0_DLY, val)
#define bfin_read_SPI0_SLVSEL()		bfin_read32(SPI0_SLVSEL)