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aiot
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waterDataStatisticsCrossAssociation
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monitoringDataProcessing
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connectionSignalSlot.h

connectionSignalSlot.h 32 KB
文件歷史 原始文件

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  1. /*
    2. 

  2.  * Copyright 2007-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF522_H
    8. 

  8. #define _DEF_BF522_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* ==== begin from defBF534.h ==== */
    15. 

  15. 

  16. /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
    17. 

  17. #define PLL_CTL				0xFFC00000	/* PLL Control Register						*/
    18. 

  18. #define PLL_DIV				0xFFC00004	/* PLL Divide Register						*/
    19. 

  19. #define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register		*/
    20. 

  20. #define PLL_STAT			0xFFC0000C	/* PLL Status Register						*/
    21. 

  21. #define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register					*/
    22. 

  22. #define CHIPID        0xFFC00014  /* Device ID Register */
    23. 

  23. 

  24. 

  25. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
    26. 

  26. #define SWRST				0xFFC00100	/* Software Reset Register					*/
    27. 

  27. #define SYSCR				0xFFC00104	/* System Configuration Register			*/
    28. 

  28. #define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register	*/
    29. 

  29. 

  30. #define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register					*/
    31. 

  31. #define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0			*/
    32. 

  32. #define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1			*/
    33. 

  33. #define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2			*/
    34. 

  34. #define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3			*/
    35. 

  35. #define SIC_ISR0				0xFFC00120	/* Interrupt Status Register				*/
    36. 

  36. #define SIC_IWR0				0xFFC00124	/* Interrupt Wakeup Register				*/
    37. 

  37. 

  38. /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
    39. 

  39. #define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
    40. 

  40. #define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
    41. 

  41. #define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
    42. 

  42. #define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
    43. 

  43. #define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
    44. 

  44. #define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
    45. 

  45. #define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
    46. 

  46. 

  47. 

  48. /* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
    49. 

  49. #define WDOG_CTL			0xFFC00200	/* Watchdog Control Register				*/
    50. 

  50. #define WDOG_CNT			0xFFC00204	/* Watchdog Count Register					*/
    51. 

  51. #define WDOG_STAT			0xFFC00208	/* Watchdog Status Register					*/
    52. 

  52. 

  53. 

  54. /* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
    55. 

  55. #define RTC_STAT			0xFFC00300	/* RTC Status Register						*/
    56. 

  56. #define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register			*/
    57. 

  57. #define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register			*/
    58. 

  58. #define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register				*/
    59. 

  59. #define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register					*/
    60. 

  60. #define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register			*/
    61. 

  61. #define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro		*/
    62. 

  62. 

  63. 

  64. /* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
    65. 

  65. #define UART0_THR			0xFFC00400	/* Transmit Holding register				*/
    66. 

  66. #define UART0_RBR			0xFFC00400	/* Receive Buffer register					*/
    67. 

  67. #define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)					*/
    68. 

  68. #define UART0_IER			0xFFC00404	/* Interrupt Enable Register				*/
    69. 

  69. #define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)				*/
    70. 

  70. #define UART0_IIR			0xFFC00408	/* Interrupt Identification Register		*/
    71. 

  71. #define UART0_LCR			0xFFC0040C	/* Line Control Register					*/
    72. 

  72. #define UART0_MCR			0xFFC00410	/* Modem Control Register					*/
    73. 

  73. #define UART0_LSR			0xFFC00414	/* Line Status Register						*/
    74. 

  74. #define UART0_MSR			0xFFC00418	/* Modem Status Register					*/
    75. 

  75. #define UART0_SCR			0xFFC0041C	/* SCR Scratch Register						*/
    76. 

  76. #define UART0_GCTL			0xFFC00424	/* Global Control Register					*/
    77. 

  77. 

  78. 

  79. /* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/
    80. 

  80. #define SPI0_REGBASE			0xFFC00500
    81. 

  81. #define SPI_CTL				0xFFC00500	/* SPI Control Register						*/
    82. 

  82. #define SPI_FLG				0xFFC00504	/* SPI Flag register						*/
    83. 

  83. #define SPI_STAT			0xFFC00508	/* SPI Status register						*/
    84. 

  84. #define SPI_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register		*/
    85. 

  85. #define SPI_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register			*/
    86. 

  86. #define SPI_BAUD			0xFFC00514	/* SPI Baud rate Register					*/
    87. 

  87. #define SPI_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register					*/
    88. 

  88. 

  89. 

  90. /* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
    91. 

  91. #define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register			*/
    92. 

  92. #define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register					*/
    93. 

  93. #define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register					*/
    94. 

  94. #define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register					*/
    95. 

  95. 

  96. #define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register  			*/
    97. 

  97. #define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register        			*/
    98. 

  98. #define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register         			*/
    99. 

  99. #define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register          			*/
    100. 

  100. 

  101. #define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register  			*/
    102. 

  102. #define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register        			*/
    103. 

  103. #define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register         			*/
    104. 

  104. #define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register          			*/
    105. 

  105. 

  106. #define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register			*/
    107. 

  107. #define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register					*/
    108. 

  108. #define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register					*/
    109. 

  109. #define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register					*/
    110. 

  110. 

  111. #define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register  			*/
    112. 

  112. #define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register        			*/
    113. 

  113. #define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register         			*/
    114. 

  114. #define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register          			*/
    115. 

  115. 

  116. #define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register  			*/
    117. 

  117. #define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register        			*/
    118. 

  118. #define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register         			*/
    119. 

  119. #define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register          			*/
    120. 

  120. 

  121. #define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register  			*/
    122. 

  122. #define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register        			*/
    123. 

  123. #define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register         			*/
    124. 

  124. #define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register          			*/
    125. 

  125. 

  126. #define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register  			*/
    127. 

  127. #define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register        			*/
    128. 

  128. #define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register         			*/
    129. 

  129. #define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/
    130. 

  130. 

  131. #define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register					*/
    132. 

  132. #define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register					*/
    133. 

  133. #define TIMER_STATUS		0xFFC00688	/* Timer Status Register					*/
    134. 

  134. 

  135. 

  136. /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)												*/
    137. 

  137. #define PORTFIO					0xFFC00700	/* Port F I/O Pin State Specify Register				*/
    138. 

  138. #define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register		*/
    139. 

  139. #define PORTFIO_SET				0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register			*/
    140. 

  140. #define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
    141. 

  141. #define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register	*/
    142. 

  142. #define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register			*/
    143. 

  143. #define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register			*/
    144. 

  144. #define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register	*/
    145. 

  145. #define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register	*/
    146. 

  146. #define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register			*/
    147. 

  147. #define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register			*/
    148. 

  148. #define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register	*/
    149. 

  149. #define PORTFIO_DIR				0xFFC00730	/* Port F I/O Direction Register						*/
    150. 

  150. #define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
    151. 

  151. #define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register				*/
    152. 

  152. #define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register				*/
    153. 

  153. #define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
    154. 

  154. 

  155. 

  156. /* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)										*/
    157. 

  157. #define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register			*/
    158. 

  158. #define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register			*/
    159. 

  159. #define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider					*/
    160. 

  160. #define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider				*/
    161. 

  161. #define SPORT0_TX			0xFFC00810	/* SPORT0 TX Data Register							*/
    162. 

  162. #define SPORT0_RX			0xFFC00818	/* SPORT0 RX Data Register							*/
    163. 

  163. #define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register			*/
    164. 

  164. #define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register			*/
    165. 

  165. #define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider						*/
    166. 

  166. #define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider				*/
    167. 

  167. #define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
    168. 

  168. #define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register					*/
    169. 

  169. #define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1	*/
    170. 

  170. #define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2	*/
    171. 

  171. #define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0	*/
    172. 

  172. #define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1	*/
    173. 

  173. #define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2	*/
    174. 

  174. #define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3	*/
    175. 

  175. #define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0	*/
    176. 

  176. #define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1	*/
    177. 

  177. #define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2	*/
    178. 

  178. #define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3	*/
    179. 

  179. 

  180. 

  181. /* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)										*/
    182. 

  182. #define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register			*/
    183. 

  183. #define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register			*/
    184. 

  184. #define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider					*/
    185. 

  185. #define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider				*/
    186. 

  186. #define SPORT1_TX			0xFFC00910	/* SPORT1 TX Data Register							*/
    187. 

  187. #define SPORT1_RX			0xFFC00918	/* SPORT1 RX Data Register							*/
    188. 

  188. #define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register			*/
    189. 

  189. #define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register			*/
    190. 

  190. #define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider						*/
    191. 

  191. #define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider				*/
    192. 

  192. #define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
    193. 

  193. #define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register					*/
    194. 

  194. #define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1	*/
    195. 

  195. #define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2	*/
    196. 

  196. #define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0	*/
    197. 

  197. #define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1	*/
    198. 

  198. #define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2	*/
    199. 

  199. #define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3	*/
    200. 

  200. #define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0	*/
    201. 

  201. #define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1	*/
    202. 

  202. #define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2	*/
    203. 

  203. #define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3	*/
    204. 

  204. 

  205. 

  206. /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)								*/
    207. 

  207. #define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register	*/
    208. 

  208. #define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0	*/
    209. 

  209. #define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1	*/
    210. 

  210. #define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register				*/
    211. 

  211. #define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register					*/
    212. 

  212. #define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register			*/
    213. 

  213. #define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register						*/
    214. 

  214. 

  215. 

  216. /* DMA Traffic Control Registers													*/
    217. 

  217. #define DMAC_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
    218. 

  218. #define DMAC_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
    219. 

  219. 

  220. /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/
    221. 

  221. #define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/
    222. 

  222. #define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
    223. 

  223. #define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
    224. 

  224. #define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
    225. 

  225. #define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
    226. 

  226. #define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
    227. 

  227. #define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
    228. 

  228. #define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register	*/
    229. 

  229. #define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register				*/
    230. 

  230. #define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
    231. 

  231. #define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register				*/
    232. 

  232. #define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register				*/
    233. 

  233. #define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register				*/
    234. 

  234. 

  235. #define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register		*/
    236. 

  236. #define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
    237. 

  237. #define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
    238. 

  238. #define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
    239. 

  239. #define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
    240. 

  240. #define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
    241. 

  241. #define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
    242. 

  242. #define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register	*/
    243. 

  243. #define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register				*/
    244. 

  244. #define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
    245. 

  245. #define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register				*/
    246. 

  246. #define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register				*/
    247. 

  247. #define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register				*/
    248. 

  248. 

  249. #define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register		*/
    250. 

  250. #define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
    251. 

  251. #define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
    252. 

  252. #define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
    253. 

  253. #define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
    254. 

  254. #define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
    255. 

  255. #define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
    256. 

  256. #define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register	*/
    257. 

  257. #define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register				*/
    258. 

  258. #define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
    259. 

  259. #define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register				*/
    260. 

  260. #define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register				*/
    261. 

  261. #define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register				*/
    262. 

  262. 

  263. #define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register		*/
    264. 

  264. #define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
    265. 

  265. #define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
    266. 

  266. #define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
    267. 

  267. #define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
    268. 

  268. #define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
    269. 

  269. #define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
    270. 

  270. #define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register	*/
    271. 

  271. #define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register				*/
    272. 

  272. #define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
    273. 

  273. #define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register				*/
    274. 

  274. #define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register				*/
    275. 

  275. #define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register				*/
    276. 

  276. 

  277. #define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register		*/
    278. 

  278. #define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
    279. 

  279. #define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
    280. 

  280. #define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
    281. 

  281. #define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
    282. 

  282. #define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
    283. 

  283. #define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
    284. 

  284. #define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register	*/
    285. 

  285. #define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register				*/
    286. 

  286. #define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
    287. 

  287. #define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register				*/
    288. 

  288. #define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register				*/
    289. 

  289. #define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register				*/
    290. 

  290. 

  291. #define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register		*/
    292. 

  292. #define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
    293. 

  293. #define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
    294. 

  294. #define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
    295. 

  295. #define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
    296. 

  296. #define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
    297. 

  297. #define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
    298. 

  298. #define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register	*/
    299. 

  299. #define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register				*/
    300. 

  300. #define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
    301. 

  301. #define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register				*/
    302. 

  302. #define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register				*/
    303. 

  303. #define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register				*/
    304. 

  304. 

  305. #define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register		*/
    306. 

  306. #define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
    307. 

  307. #define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
    308. 

  308. #define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
    309. 

  309. #define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
    310. 

  310. #define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
    311. 

  311. #define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
    312. 

  312. #define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register	*/
    313. 

  313. #define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register				*/
    314. 

  314. #define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
    315. 

  315. #define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register				*/
    316. 

  316. #define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register				*/
    317. 

  317. #define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register				*/
    318. 

  318. 

  319. #define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register		*/
    320. 

  320. #define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
    321. 

  321. #define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
    322. 

  322. #define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
    323. 

  323. #define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
    324. 

  324. #define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
    325. 

  325. #define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
    326. 

  326. #define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register	*/
    327. 

  327. #define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register				*/
    328. 

  328. #define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
    329. 

  329. #define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register				*/
    330. 

  330. #define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register				*/
    331. 

  331. #define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register				*/
    332. 

  332. 

  333. #define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
    334. 

  334. #define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
    335. 

  335. #define DMA8_CONFIG				0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
    336. 

  336. #define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
    337. 

  337. #define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
    338. 

  338. #define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
    339. 

  339. #define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
    340. 

  340. #define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
    341. 

  341. #define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register				*/
    342. 

  342. #define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
    343. 

  343. #define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register				*/
    344. 

  344. #define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register				*/
    345. 

  345. #define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register				*/
    346. 

  346. 

  347. #define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
    348. 

  348. #define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register					*/
    349. 

  349. #define DMA9_CONFIG				0xFFC00E48	/* DMA Channel 9 Configuration Register					*/
    350. 

  350. #define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register						*/
    351. 

  351. #define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register						*/
    352. 

  352. #define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register						*/
    353. 

  353. #define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register						*/
    354. 

  354. #define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
    355. 

  355. #define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register				*/
    356. 

  356. #define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register				*/
    357. 

  357. #define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register				*/
    358. 

  358. #define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register				*/
    359. 

  359. #define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register				*/
    360. 

  360. 

  361. #define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
    362. 

  362. #define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register				*/
    363. 

  363. #define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register				*/
    364. 

  364. #define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register						*/
    365. 

  365. #define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register						*/
    366. 

  366. #define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register						*/
    367. 

  367. #define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register						*/
    368. 

  368. #define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
    369. 

  369. #define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register				*/
    370. 

  370. #define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register				*/
    371. 

  371. #define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register				*/
    372. 

  372. #define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register				*/
    373. 

  373. #define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register				*/
    374. 

  374. 

  375. #define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
    376. 

  376. #define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register				*/
    377. 

  377. #define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register				*/
    378. 

  378. #define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register						*/
    379. 

  379. #define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register						*/
    380. 

  380. #define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register						*/
    381. 

  381. #define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register						*/
    382. 

  382. #define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
    383. 

  383. #define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register				*/
    384. 

  384. #define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register				*/
    385. 

  385. #define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register				*/
    386. 

  386. #define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register				*/
    387. 

  387. #define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register				*/
    388. 

  388. 

  389. #define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register		*/
    390. 

  390. #define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register				*/
    391. 

  391. #define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register				*/
    392. 

  392. #define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register						*/
    393. 

  393. #define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register					*/
    394. 

  394. #define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register						*/
    395. 

  395. #define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register					*/
    396. 

  396. #define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register	*/
    397. 

  397. #define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register				*/
    398. 

  398. #define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register			*/
    399. 

  399. #define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register				*/
    400. 

  400. #define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register				*/
    401. 

  401. #define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register				*/
    402. 

  402. 

  403. #define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register			*/
    404. 

  404. #define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register					*/
    405. 

  405. #define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register					*/
    406. 

  406. #define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register							*/
    407. 

  407. #define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register							*/
    408. 

  408. #define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register							*/
    409. 

  409. #define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register							*/
    410. 

  410. #define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register		*/
    411. 

  411. #define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register					*/
    412. 

  412. #define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register					*/
    413. 

  413. #define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register					*/
    414. 

  414. #define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register					*/
    415. 

  415. #define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register					*/
    416. 

  416. 

  417. #define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register		*/
    418. 

  418. #define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register				*/
    419. 

  419. #define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register				*/
    420. 

  420. #define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register						*/
    421. 

  421. #define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register					*/
    422. 

  422. #define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register						*/
    423. 

  423. #define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register					*/
    424. 

  424. #define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register	*/
    425. 

  425. #define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register				*/
    426. 

  426. #define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register			*/
    427. 

  427. #define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register				*/
    428. 

  428. #define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register				*/
    429. 

  429. #define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register				*/
    430. 

  430. 

  431. #define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register			*/
    432. 

  432. #define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register					*/
    433. 

  433. #define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register					*/
    434. 

  434. #define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register							*/
    435. 

  435. #define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register							*/
    436. 

  436. #define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register							*/
    437. 

  437. #define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register							*/
    438. 

  438. #define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register		*/
    439. 

  439. #define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register					*/
    440. 

  440. #define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register					*/
    441. 

  441. #define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register					*/
    442. 

  442. #define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register					*/
    443. 

  443. #define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register					*/
    444. 

  444. 

  445. 

  446. /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)				*/
    447. 

  447. #define PPI_CONTROL			0xFFC01000	/* PPI Control Register			*/
    448. 

  448. #define PPI_STATUS			0xFFC01004	/* PPI Status Register			*/
    449. 

  449. #define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register	*/
    450. 

  450. #define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register		*/
    451. 

  451. #define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register	*/
    452. 

  452. 

  453. 

  454. /* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
    455. 

  455. #define TWI0_REGBASE			0xFFC01400
    456. 

  456. #define TWI0_CLKDIV			0xFFC01400	/* Serial Clock Divider Register			*/
    457. 

  457. #define TWI0_CONTROL			0xFFC01404	/* TWI Control Register						*/
    458. 

  458. #define TWI0_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register				*/
    459. 

  459. #define TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register				*/
    460. 

  460. #define TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register				*/
    461. 

  461. #define TWI0_MASTER_CTL		0xFFC01414	/* Master Mode Control Register				*/
    462. 

  462. #define TWI0_MASTER_STAT		0xFFC01418	/* Master Mode Status Register				*/
    463. 

  463. #define TWI0_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register				*/
    464. 

  464. #define TWI0_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register			*/
    465. 

  465. #define TWI0_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register		*/
    466. 

  466. #define TWI0_FIFO_CTL		0xFFC01428	/* FIFO Control Register					*/
    467.