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- /*
- * arch/arm/include/asm/hardware/sa1111.h
- *
- * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
- *
- * This file contains definitions for the SA-1111 Companion Chip.
- * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
- *
- * Macro that calculates real address for registers in the SA-1111
- */
- #ifndef _ASM_ARCH_SA1111
- #define _ASM_ARCH_SA1111
- #include <mach/bitfield.h>
- /*
- * The SA1111 is always located at virtual 0xf4000000, and is always
- * "native" endian.
- */
- #define SA1111_VBASE 0xf4000000
- /* Don't use these! */
- #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
- #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
- #ifndef __ASSEMBLY__
- #define _SA1111(x) ((x) + sa1111->resource.start)
- #endif
- #define sa1111_writel(val,addr) __raw_writel(val, addr)
- #define sa1111_readl(addr) __raw_readl(addr)
- /*
- * 26 bits of the SA-1110 address bus are available to the SA-1111.
- * Use these when feeding target addresses to the DMA engines.
- */
- #define SA1111_ADDR_WIDTH (26)
- #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
- #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
- /*
- * Don't ask the (SAC) DMA engines to move less than this amount.
- */
- #define SA1111_SAC_DMA_MIN_XFER (0x800)
- /*
- * System Bus Interface (SBI)
- *
- * Registers
- * SKCR Control Register
- * SMCR Shared Memory Controller Register
- * SKID ID Register
- */
- #define SA1111_SKCR 0x0000
- #define SA1111_SMCR 0x0004
- #define SA1111_SKID 0x0008
- #define SKCR_PLL_BYPASS (1<<0)
- #define SKCR_RCLKEN (1<<1)
- #define SKCR_SLEEP (1<<2)
- #define SKCR_DOZE (1<<3)
- #define SKCR_VCO_OFF (1<<4)
- #define SKCR_SCANTSTEN (1<<5)
- #define SKCR_CLKTSTEN (1<<6)
- #define SKCR_RDYEN (1<<7)
- #define SKCR_SELAC (1<<8)
- #define SKCR_OPPC (1<<9)
- #define SKCR_PLLTSTEN (1<<10)
- #define SKCR_USBIOTSTEN (1<<11)
- /*
- * Don't believe the specs! Take them, throw them outside. Leave them
- * there for a week. Spit on them. Walk on them. Stamp on them.
- * Pour gasoline over them and finally burn them. Now think about coding.
- * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
- * - The Feb 2001 errata (278260-010) says that the previous errata
- * (278260-009) is wrong, and its bit actually 12, fixed in spec
- * 278242-003.
- * - The SA1111 manual (278242) says bit 12, but 0 to enable.
- * - Reality is bit 13, 1 to enable.
- * -- rmk
- */
- #define SKCR_OE_EN (1<<13)
- #define SMCR_DTIM (1<<0)
- #define SMCR_MBGE (1<<1)
- #define SMCR_DRAC_0 (1<<2)
- #define SMCR_DRAC_1 (1<<3)
- #define SMCR_DRAC_2 (1<<4)
- #define SMCR_DRAC Fld(3, 2)
- #define SMCR_CLAT (1<<5)
- #define SKID_SIREV_MASK (0x000000f0)
- #define SKID_MTREV_MASK (0x0000000f)
- #define SKID_ID_MASK (0xffffff00)
- #define SKID_SA1111_ID (0x690cc200)
- /*
- * System Controller
- *
- * Registers
- * SKPCR Power Control Register
- * SKCDR Clock Divider Register
- * SKAUD Audio Clock Divider Register
- * SKPMC PS/2 Mouse Clock Divider Register
- * SKPTC PS/2 Track Pad Clock Divider Register
- * SKPEN0 PWM0 Enable Register
- * SKPWM0 PWM0 Clock Register
- * SKPEN1 PWM1 Enable Register
- * SKPWM1 PWM1 Clock Register
- */
- #define SA1111_SKPCR 0x0200
- #define SA1111_SKCDR 0x0204
- #define SA1111_SKAUD 0x0208
- #define SA1111_SKPMC 0x020c
- #define SA1111_SKPTC 0x0210
- #define SA1111_SKPEN0 0x0214
- #define SA1111_SKPWM0 0x0218
- #define SA1111_SKPEN1 0x021c
- #define SA1111_SKPWM1 0x0220
- #define SKPCR_UCLKEN (1<<0)
- #define SKPCR_ACCLKEN (1<<1)
- #define SKPCR_I2SCLKEN (1<<2)
- #define SKPCR_L3CLKEN (1<<3)
- #define SKPCR_SCLKEN (1<<4)
- #define SKPCR_PMCLKEN (1<<5)
- #define SKPCR_PTCLKEN (1<<6)
- #define SKPCR_DCLKEN (1<<7)
- #define SKPCR_PWMCLKEN (1<<8)
- /* USB Host controller */
- #define SA1111_USB 0x0400
- /*
- * Serial Audio Controller
- *
- * Registers
- * SACR0 Serial Audio Common Control Register
- * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
- * SACR2 Serial Audio AC-link Control Register
- * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
- * SASR1 Serial Audio AC-link Interface & FIFO Status Register
- * SASCR Serial Audio Status Clear Register
- * L3_CAR L3 Control Bus Address Register
- * L3_CDR L3 Control Bus Data Register
- * ACCAR AC-link Command Address Register
- * ACCDR AC-link Command Data Register
- * ACSAR AC-link Status Address Register
- * ACSDR AC-link Status Data Register
- * SADTCS Serial Audio DMA Transmit Control/Status Register
- * SADTSA Serial Audio DMA Transmit Buffer Start Address A
- * SADTCA Serial Audio DMA Transmit Buffer Count Register A
- * SADTSB Serial Audio DMA Transmit Buffer Start Address B
- * SADTCB Serial Audio DMA Transmit Buffer Count Register B
- * SADRCS Serial Audio DMA Receive Control/Status Register
- * SADRSA Serial Audio DMA Receive Buffer Start Address A
- * SADRCA Serial Audio DMA Receive Buffer Count Register A
- * SADRSB Serial Audio DMA Receive Buffer Start Address B
- * SADRCB Serial Audio DMA Receive Buffer Count Register B
- * SAITR Serial Audio Interrupt Test Register
- * SADR Serial Audio Data Register (16 x 32-bit)
- */
- #define SA1111_SERAUDIO 0x0600
- /*
- * These are offsets from the above base.
- */
- #define SA1111_SACR0 0x00
- #define SA1111_SACR1 0x04
- #define SA1111_SACR2 0x08
- #define SA1111_SASR0 0x0c
- #define SA1111_SASR1 0x10
- #define SA1111_SASCR 0x18
- #define SA1111_L3_CAR 0x1c
- #define SA1111_L3_CDR 0x20
- #define SA1111_ACCAR 0x24
- #define SA1111_ACCDR 0x28
- #define SA1111_ACSAR 0x2c
- #define SA1111_ACSDR 0x30
- #define SA1111_SADTCS 0x34
- #define SA1111_SADTSA 0x38
- #define SA1111_SADTCA 0x3c
- #define SA1111_SADTSB 0x40
- #define SA1111_SADTCB 0x44
- #define SA1111_SADRCS 0x48
- #define SA1111_SADRSA 0x4c
- #define SA1111_SADRCA 0x50
- #define SA1111_SADRSB 0x54
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