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efDataDiscreteRateMining
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dataSharedMemory
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averageDataMemoryDefinition.h

averageDataMemoryDefinition.h 7.3 KB
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  1. /*
    2. 

  2.  * OMAP44xx CM1 instance offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009-2011 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2009-2010 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Paul Walmsley (paul@pwsan.com)
    8. 

  8.  * Rajendra Nayak (rnayak@ti.com)
    9. 

  9.  * Benoit Cousson (b-cousson@ti.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  *
    21. 

  21.  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
    22. 

  22.  *     or "OMAP4430".
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
    26. 

  26. #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
    27. 

  27. 

  28. /* CM1 base address */
    29. 

  29. #define OMAP4430_CM1_BASE		0x4a004000
    30. 

  30. 

  31. #define OMAP44XX_CM1_REGADDR(inst, reg)				\
    32. 

  32. 	OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
    33. 

  33. 

  34. /* CM1 instances */
    35. 

  35. #define OMAP4430_CM1_OCP_SOCKET_INST	0x0000
    36. 

  36. #define OMAP4430_CM1_CKGEN_INST		0x0100
    37. 

  37. #define OMAP4430_CM1_MPU_INST		0x0300
    38. 

  38. #define OMAP4430_CM1_TESLA_INST		0x0400
    39. 

  39. #define OMAP4430_CM1_ABE_INST		0x0500
    40. 

  40. #define OMAP4430_CM1_RESTORE_INST	0x0e00
    41. 

  41. #define OMAP4430_CM1_INSTR_INST		0x0f00
    42. 

  42. 

  43. /* CM1 clockdomain register offsets (from instance start) */
    44. 

  44. #define OMAP4430_CM1_MPU_MPU_CDOFFS	0x0000
    45. 

  45. #define OMAP4430_CM1_TESLA_TESLA_CDOFFS	0x0000
    46. 

  46. #define OMAP4430_CM1_ABE_ABE_CDOFFS	0x0000
    47. 

  47. 

  48. /* CM1 */
    49. 

  49. 

  50. /* CM1.OCP_SOCKET_CM1 register offsets */
    51. 

  51. #define OMAP4_REVISION_CM1_OFFSET			0x0000
    52. 

  52. #define OMAP4430_REVISION_CM1				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
    53. 

  53. #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET		0x0040
    54. 

  54. #define OMAP4430_CM_CM1_PROFILING_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
    55. 

  55. 

  56. /* CM1.CKGEN_CM1 register offsets */
    57. 

  57. #define OMAP4_CM_CLKSEL_CORE_OFFSET			0x0000
    58. 

  58. #define OMAP4430_CM_CLKSEL_CORE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
    59. 

  59. #define OMAP4_CM_CLKSEL_ABE_OFFSET			0x0008
    60. 

  60. #define OMAP4430_CM_CLKSEL_ABE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
    61. 

  61. #define OMAP4_CM_DLL_CTRL_OFFSET			0x0010
    62. 

  62. #define OMAP4430_CM_DLL_CTRL				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
    63. 

  63. #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
    64. 

  64. #define OMAP4430_CM_CLKMODE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
    65. 

  65. #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
    66. 

  66. #define OMAP4430_CM_IDLEST_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
    67. 

  67. #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028
    68. 

  68. #define OMAP4430_CM_AUTOIDLE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
    69. 

  69. #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c
    70. 

  70. #define OMAP4430_CM_CLKSEL_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
    71. 

  71. #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030
    72. 

  72. #define OMAP4430_CM_DIV_M2_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
    73. 

  73. #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034
    74. 

  74. #define OMAP4430_CM_DIV_M3_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
    75. 

  75. #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET		0x0038
    76. 

  76. #define OMAP4430_CM_DIV_M4_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
    77. 

  77. #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET		0x003c
    78. 

  78. #define OMAP4430_CM_DIV_M5_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
    79. 

  79. #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET		0x0040
    80. 

  80. #define OMAP4430_CM_DIV_M6_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
    81. 

  81. #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET		0x0044
    82. 

  82. #define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
    83. 

  83. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
    84. 

  84. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
    85. 

  85. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c
    86. 

  86. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
    87. 

  87. #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050
    88. 

  88. #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
    89. 

  89. #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
    90. 

  90. #define OMAP4430_CM_CLKMODE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
    91. 

  91. #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET			0x0064
    92. 

  92. #define OMAP4430_CM_IDLEST_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
    93. 

  93. #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068
    94. 

  94. #define OMAP4430_CM_AUTOIDLE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
    95. 

  95. #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET			0x006c
    96. 

  96. #define OMAP4430_CM_CLKSEL_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
    97. 

  97. #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070
    98. 

  98. #define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
    99. 

  99. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088
    100. 

  100. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
    101. 

  101. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c
    102. 

  102. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
    103. 

  103. #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c
    104. 

  104. #define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
    105. 

  105. #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
    106. 

  106. #define OMAP4430_CM_CLKMODE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
    107. 

  107. #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET			0x00a4
    108. 

  108. #define OMAP4430_CM_IDLEST_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
    109. 

  109. #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8
    110. 

  110. #define OMAP4430_CM_AUTOIDLE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
    111. 

  111. #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET			0x00ac
    112. 

  112. #define OMAP4430_CM_CLKSEL_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
    113. 

  113. #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET			0x00b8
    114. 

  114. #define OMAP4430_CM_DIV_M4_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
    115. 

  115. #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET			0x00bc
    116. 

  116. #define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
    117. 

  117. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8
    118. 

  118. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
    119. 

  119. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc
    120. 

  120. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
    121. 

  121. #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc
    122. 

  122. #define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
    123. 

  123. #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
    124. 

  124. #define OMAP4430_CM_CLKMODE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
    125. 

  125. #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET			0x00e4
    126. 

  126. #define OMAP4430_CM_IDLEST_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
    127. 

  127. #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8
    128. 

  128. #define OMAP4430_CM_AUTOIDLE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
    129. 

  129. #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET			0x00ec
    130. 

  130. #define OMAP4430_CM_CLKSEL_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
    131. 

  131. #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET			0x00f0
    132. 

  132. #define OMAP4430_CM_DIV_M2_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
    133.