aiot/waterInvestigationHiddenDanger/databaseOperation/analysisDataOperation.h

/* spr-regs.h: special-purpose registers on the FRV
 *
 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _ASM_SPR_REGS_H
#define _ASM_SPR_REGS_H

/*
 * PSR - Processor Status Register
 */
#define PSR_ET			0x00000001	/* enable interrupts/exceptions flag */
#define PSR_PS			0x00000002	/* previous supervisor mode flag */
#define PSR_S			0x00000004	/* supervisor mode flag */
#define PSR_PIL			0x00000078	/* processor external interrupt level */
#define PSR_PIL_0		0x00000000	/* - no interrupt in progress */
#define PSR_PIL_13		0x00000068	/* - debugging only */
#define PSR_PIL_14		0x00000070	/* - debugging in progress */
#define PSR_PIL_15		0x00000078	/* - NMI in progress */
#define PSR_EM			0x00000080	/* enable media operation */
#define PSR_EF			0x00000100	/* enable FPU operation */
#define PSR_BE			0x00001000	/* endianness mode */
#define PSR_BE_LE		0x00000000	/* - little endian mode */
#define PSR_BE_BE		0x00001000	/* - big endian mode */
#define PSR_CM			0x00002000	/* conditional mode */
#define PSR_NEM			0x00004000	/* non-excepting mode */
#define PSR_ICE			0x00010000	/* in-circuit emulation mode */
#define PSR_VERSION_SHIFT	24		/* CPU silicon ID */
#define PSR_IMPLE_SHIFT		28		/* CPU core ID */

#define PSR_VERSION(psr)	(((psr) >> PSR_VERSION_SHIFT) & 0xf)
#define PSR_IMPLE(psr)		(((psr) >> PSR_IMPLE_SHIFT) & 0xf)

#define PSR_IMPLE_FR401		0x2
#define PSR_VERSION_FR401_MB93401	0x0
#define PSR_VERSION_FR401_MB93401A	0x1
#define PSR_VERSION_FR401_MB93403	0x2

#define PSR_IMPLE_FR405		0x4
#define PSR_VERSION_FR405_MB93405	0x0

#define PSR_IMPLE_FR451		0x5
#define PSR_VERSION_FR451_MB93451	0x0

#define PSR_IMPLE_FR501		0x1
#define PSR_VERSION_FR501_MB93501	0x1
#define PSR_VERSION_FR501_MB93501A	0x2

#define PSR_IMPLE_FR551		0x3
#define PSR_VERSION_FR551_MB93555	0x1

#define __get_PSR()	({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; })
#define __set_PSR(V)	do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0)

/*
 * TBR - Trap Base Register
 */
#define TBR_TT			0x00000ff0
#define TBR_TT_INSTR_MMU_MISS	(0x01 << 4)
#define TBR_TT_INSTR_ACC_ERROR	(0x02 << 4)
#define TBR_TT_INSTR_ACC_EXCEP	(0x03 << 4)
#define TBR_TT_PRIV_INSTR	(0x06 << 4)
#define TBR_TT_ILLEGAL_INSTR	(0x07 << 4)
#define TBR_TT_FP_EXCEPTION	(0x0d << 4)
#define TBR_TT_MP_EXCEPTION	(0x0e << 4)
#define TBR_TT_DATA_ACC_ERROR	(0x11 << 4)
#define TBR_TT_DATA_MMU_MISS	(0x12 << 4)
#define TBR_TT_DATA_ACC_EXCEP	(0x13 << 4)
#define TBR_TT_DATA_STR_ERROR	(0x14 << 4)
#define TBR_TT_DIVISION_EXCEP	(0x17 << 4)
#define TBR_TT_COMMIT_EXCEP	(0x19 << 4)
#define TBR_TT_INSTR_TLB_MISS	(0x1a << 4)
#define TBR_TT_DATA_TLB_MISS	(0x1b << 4)
#define TBR_TT_DATA_DAT_EXCEP	(0x1d << 4)
#define TBR_TT_DECREMENT_TIMER	(0x1f << 4)
#define TBR_TT_COMPOUND_EXCEP	(0x20 << 4)
#define TBR_TT_INTERRUPT_1	(0x21 << 4)
#define TBR_TT_INTERRUPT_2	(0x22 << 4)
#define TBR_TT_INTERRUPT_3	(0x23 << 4)
#define TBR_TT_INTERRUPT_4	(0x24 << 4)
#define TBR_TT_INTERRUPT_5	(0x25 << 4)
#define TBR_TT_INTERRUPT_6	(0x26 << 4)
#define TBR_TT_INTERRUPT_7	(0x27 << 4)
#define TBR_TT_INTERRUPT_8	(0x28 << 4)
#define TBR_TT_INTERRUPT_9	(0x29 << 4)
#define TBR_TT_INTERRUPT_10	(0x2a << 4)
#define TBR_TT_INTERRUPT_11	(0x2b << 4)
#define TBR_TT_INTERRUPT_12	(0x2c << 4)
#define TBR_TT_INTERRUPT_13	(0x2d << 4)
#define TBR_TT_INTERRUPT_14	(0x2e << 4)
#define TBR_TT_INTERRUPT_15	(0x2f << 4)
#define TBR_TT_TRAP0		(0x80 << 4)
#define TBR_TT_TRAP1		(0x81 << 4)
#define TBR_TT_TRAP2		(0x82 << 4)
#define TBR_TT_TRAP3		(0x83 << 4)
#define TBR_TT_TRAP120		(0xf8 << 4)
#define TBR_TT_TRAP121		(0xf9 << 4)
#define TBR_TT_TRAP122		(0xfa << 4)
#define TBR_TT_TRAP123		(0xfb << 4)
#define TBR_TT_TRAP124		(0xfc << 4)
#define TBR_TT_TRAP125		(0xfd << 4)
#define TBR_TT_TRAP126		(0xfe << 4)
#define TBR_TT_BREAK		(0xff << 4)

#define TBR_TT_ATOMIC_CMPXCHG32	TBR_TT_TRAP120
#define TBR_TT_ATOMIC_XCHG32	TBR_TT_TRAP121
#define TBR_TT_ATOMIC_XOR	TBR_TT_TRAP122
#define TBR_TT_ATOMIC_OR	TBR_TT_TRAP123
#define TBR_TT_ATOMIC_AND	TBR_TT_TRAP124
#define TBR_TT_ATOMIC_SUB	TBR_TT_TRAP125
#define TBR_TT_ATOMIC_ADD	TBR_TT_TRAP126

#define __get_TBR()	({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; })

/*
 * HSR0 - Hardware Status Register 0
 */
#define HSR0_PDM		0x00000007	/* power down mode */
#define HSR0_PDM_NORMAL		0x00000000	/* - normal mode */
#define HSR0_PDM_CORE_SLEEP	0x00000001	/* - CPU core sleep mode */
#define HSR0_PDM_BUS_SLEEP	0x00000003	/* - bus sleep mode */
#define HSR0_PDM_PLL_RUN	0x00000005	/* - PLL run */
#define HSR0_PDM_PLL_STOP	0x00000007	/* - PLL stop */
#define HSR0_GRLE		0x00000040	/* GR lower register set enable */
#define HSR0_GRHE		0x00000080	/* GR higher register set enable */
#define HSR0_FRLE		0x00000100	/* FR lower register set enable */
#define HSR0_FRHE		0x00000200	/* FR higher register set enable */
#define HSR0_GRN		0x00000400	/* GR quantity */
#define HSR0_GRN_64		0x00000000	/* - 64 GR registers */
#define HSR0_GRN_32		0x00000400	/* - 32 GR registers */
#define HSR0_FRN		0x00000800	/* FR quantity */
#define HSR0_FRN_64		0x00000000	/* - 64 FR registers */
#define HSR0_FRN_32		0x00000800	/* - 32 FR registers */
#define HSR0_SA			0x00001000	/* start address (RAMBOOT#) */
#define HSR0_ETMI		0x00008000	/* enable TIMERI (64-bit up timer) */
#define HSR0_ETMD		0x00004000	/* enable TIMERD (32-bit down timer) */
#define HSR0_PEDAT		0x00010000	/* previous DAT mode */
#define HSR0_XEDAT		0x00020000	/* exception DAT mode */
#define HSR0_EDAT		0x00080000	/* enable DAT mode */
#define HSR0_RME		0x00400000	/* enable RAM mode */
#define HSR0_EMEM		0x00800000	/* enable MMU_Miss mask */
#define HSR0_EXMMU		0x01000000	/* enable extended MMU mode */
#define HSR0_EDMMU		0x02000000	/* enable data MMU */
#define HSR0_EIMMU		0x04000000	/* enable instruction MMU */
#define HSR0_CBM		0x08000000	/* copy back mode */
#define HSR0_CBM_WRITE_THRU	0x00000000	/* - write through */
#define HSR0_CBM_COPY_BACK	0x08000000	/* - copy back */
#define HSR0_NWA		0x10000000	/* no write allocate */
#define HSR0_DCE		0x40000000	/* data cache enable */
#define HSR0_ICE		0x80000000	/* instruction cache enable */

#define __get_HSR(R)	({ unsigned long x; asm volatile("movsg hsr"#R",%0" : "=r"(x)); x; })
#define __set_HSR(R,V)	do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0)

/*
 * CCR - Condition Codes Register
 */
#define CCR_FCC0		0x0000000f	/* FP/Media condition 0 (fcc0 reg) */
#define CCR_FCC1		0x000000f0	/* FP/Media condition 1 (fcc1 reg) */
#define CCR_FCC2		0x00000f00	/* FP/Media condition 2 (fcc2 reg) */
#define CCR_FCC3		0x0000f000	/* FP/Media condition 3 (fcc3 reg) */
#define CCR_ICC0		0x000f0000	/* Integer condition 0 (icc0 reg) */
#define CCR_ICC0_C		0x00010000	/* - Carry flag */
#define CCR_ICC0_V		0x00020000	/* - Overflow flag */
#define CCR_ICC0_Z		0x00040000	/* - Zero flag */
#define CCR_ICC0_N		0x00080000	/* - Negative flag */
#define CCR_ICC1		0x00f00000	/* Integer condition 1 (icc1 reg) */
#define CCR_ICC2		0x0f000000	/* Integer condition 2 (icc2 reg) */
#define CCR_ICC3		0xf0000000	/* Integer condition 3 (icc3 reg) */

/*
 * CCCR - Condition Codes for Conditional Instructions Register
 */
#define CCCR_CC0		0x00000003	/* condition 0 (cc0 reg) */
#define CCCR_CC0_FALSE		0x00000002	/* - condition is false */
#define CCCR_CC0_TRUE		0x00000003	/* - condition is true */
#define CCCR_CC1		0x0000000c	/* condition 1 (cc1 reg) */
#define CCCR_CC2		0x00000030	/* condition 2 (cc2 reg) */
#define CCCR_CC3		0x000000c0	/* condition 3 (cc3 reg) */
#define CCCR_CC4		0x00000300	/* condition 4 (cc4 reg) */
#define CCCR_CC5		0x00000c00	/* condition 5 (cc5 reg) */
#define CCCR_CC6		0x00003000	/* condition 6 (cc6 reg) */
#define CCCR_CC7		0x0000c000	/* condition 7 (cc7 reg) */

/*
 * ISR - Integer Status Register
 */
#define ISR_EMAM		0x00000001	/* memory misaligned access handling */
#define ISR_EMAM_EXCEPTION	0x00000000	/* - generate exception */
#define ISR_EMAM_FUDGE		0x00000001	/* - mask out invalid address bits */
#define ISR_AEXC		0x00000004	/* accrued [overflow] exception */
#define ISR_DTT			0x00000018	/* division type trap */
#define ISR_DTT_IGNORE		0x00000000	/* - ignore division error */
#define ISR_DTT_DIVBYZERO	0x00000008	/* - generate exception */
#define ISR_DTT_OVERFLOW	0x00000010	/* - record overflow */
#define ISR_EDE			0x00000020	/* enable division exception */
#define ISR_PLI			0x20000000	/* pre-load instruction information */
#define ISR_QI			0x80000000	/* quad data implementation information */

/*
 * EPCR0 - Exception PC Register
 */
#define EPCR0_V			0x00000001	/* register content validity indicator */
#define EPCR0_PC		0xfffffffc	/* faulting instruction address */

/*
 * ESR0/14/15 - Exception Status Register
 */
#define ESRx_VALID		0x00000001	/* register content validity indicator */
#define ESRx_EC			0x0000003e	/* exception type */
#define ESRx_EC_DATA_STORE	0x00000000	/* - data_store_error */
#define ESRx_EC_INSN_ACCESS	0x00000006	/* - instruction_access_error */
#define ESRx_EC_PRIV_INSN	0x00000008	/* - privileged_instruction */
#define ESRx_EC_ILL_INSN	0x0000000a	/* - illegal_instruction */
#define ESRx_EC_MP_EXCEP	0x0000001c	/* - mp_exception */
#define ESRx_EC_DATA_ACCESS	0x00000020	/* - data_access_error */
#define ESRx_EC_DIVISION	0x00000026	/* - division_exception */