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memoryCall.h

memoryCall.h 135 KB
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
  1. /*
    2. 

  2.  * Copyright 2011 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF60X_H
    8. 

  8. #define _CDEF_BF60X_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
    15. 

  15. 

  16. #define bfin_read_CHIPID()		bfin_read32(CHIPID)
    17. 

  17. #define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
    18. 

  18. 

  19. /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
    20. 

  20. 

  21. /* SEC0 Registers */
    22. 

  22. #define bfin_read_SEC0_CCTL()		bfin_read32(SEC0_CCTL)
    23. 

  23. #define bfin_write_SEC0_CCTL(val)	bfin_write32(SEC0_CCTL, val)
    24. 

  24. #define bfin_read_SEC0_CSID()		bfin_read32(SEC0_CSID)
    25. 

  25. #define bfin_write_SEC0_CSID(val)	bfin_write32(SEC0_CSID, val)
    26. 

  26. #define bfin_read_SEC_GCTL()		bfin_read32(SEC_GCTL)
    27. 

  27. #define bfin_write_SEC_GCTL(val)	bfin_write32(SEC_GCTL, val)
    28. 

  28. 

  29. #define bfin_read_SEC_FCTL()		bfin_read32(SEC_FCTL)
    30. 

  30. #define bfin_write_SEC_FCTL(val)	bfin_write32(SEC_FCTL, val)
    31. 

  31. 

  32. #define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC_SCTL0 + (sid) * 8))
    33. 

  33. #define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC_SCTL0 + (sid) * 8), val)
    34. 

  34. 

  35. #define bfin_read_SEC_SSTAT(sid)	bfin_read32((SEC_SSTAT0 + (sid) * 8))
    36. 

  36. #define bfin_write_SEC_SSTAT(sid, val)	bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
    37. 

  37. 

  38. /* RCU0 Registers */
    39. 

  39. #define bfin_read_RCU0_CTL()		bfin_read32(RCU0_CTL)
    40. 

  40. #define bfin_write_RCU0_CTL(val)	bfin_write32(RCU0_CTL, val)
    41. 

  41. 

  42. /* Watchdog Timer Registers */
    43. 

  43. #define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
    44. 

  44. #define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
    45. 

  45. #define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
    46. 

  46. #define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
    47. 

  47. #define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
    48. 

  48. #define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)
    49. 

  49. 

  50. /* RTC Registers */
    51. 

  51. 

  52. /* UART0 Registers */
    53. 

  53. 

  54. #define bfin_read_UART0_REVID()		bfin_read32(UART0_REVID)
    55. 

  55. #define bfin_write_UART0_REVID(val)	bfin_write32(UART0_REVID, val)
    56. 

  56. #define bfin_read_UART0_GCTL()		bfin_read32(UART0_GCTL)
    57. 

  57. #define bfin_write_UART0_GCTL(val)	bfin_write32(UART0_GCTL, val)
    58. 

  58. #define bfin_read_UART0_STAT()		bfin_read32(UART0_STAT)
    59. 

  59. #define bfin_write_UART0_STAT(val)	bfin_write32(UART0_STAT, val)
    60. 

  60. #define bfin_read_UART0_SCR()		bfin_read32(UART0_SCR)
    61. 

  61. #define bfin_write_UART0_SCR(val)	bfin_write32(UART0_SCR, val)
    62. 

  62. #define bfin_read_UART0_CLK()		bfin_read32(UART0_CLK)
    63. 

  63. #define bfin_write_UART0_CLK(val)	bfin_write32(UART0_CLK, val)
    64. 

  64. #define bfin_read_UART0_IER()		bfin_read32(UART0_IER)
    65. 

  65. #define bfin_write_UART0_IER(val)	bfin_write32(UART0_IER, val)
    66. 

  66. #define bfin_read_UART0_IER_SET()	bfin_read32(UART0_IER_SET)
    67. 

  67. #define bfin_write_UART0_IER_SET(val)	bfin_write32(UART0_IER_SET, val)
    68. 

  68. #define bfin_read_UART0_IER_CLEAR()	bfin_read32(UART0_IER_CLEAR)
    69. 

  69. #define bfin_write_UART0_IER_CLEAR(val)	bfin_write32(UART0_IER_CLEAR, val)
    70. 

  70. #define bfin_read_UART0_RBR()		bfin_read32(UART0_RBR)
    71. 

  71. #define bfin_write_UART0_RBR(val)	bfin_write32(UART0_RBR, val)
    72. 

  72. #define bfin_read_UART0_THR()		bfin_read32(UART0_THR)
    73. 

  73. #define bfin_write_UART0_THR(val)	bfin_write32(UART0_THR, val)
    74. 

  74. #define bfin_read_UART0_TAIP()		bfin_read32(UART0_TAIP)
    75. 

  75. #define bfin_write_UART0_TAIP(val)	bfin_write32(UART0_TAIP, val)
    76. 

  76. #define bfin_read_UART0_TSR()		bfin_read32(UART0_TSR)
    77. 

  77. #define bfin_write_UART0_TSR(val)	bfin_write32(UART0_TSR, val)
    78. 

  78. #define bfin_read_UART0_RSR()		bfin_read32(UART0_RSR)
    79. 

  79. #define bfin_write_UART0_RSR(val)	bfin_write32(UART0_RSR, val)
    80. 

  80. #define bfin_read_UART0_TXCNT()		bfin_read32(UART0_TXCNT)
    81. 

  81. #define bfin_write_UART0_TXCNT(val)	bfin_write32(UART0_TXCNT, val)
    82. 

  82. #define bfin_read_UART0_RXCNT()		bfin_read32(UART0_RXCNT)
    83. 

  83. #define bfin_write_UART0_RXCNT(val)	bfin_write32(UART0_RXCNT, val)
    84. 

  84. 

  85. /* UART1 Registers */
    86. 

  86. 

  87. #define bfin_read_UART1_REVID()		bfin_read32(UART1_REVID)
    88. 

  88. #define bfin_write_UART1_REVID(val)	bfin_write32(UART1_REVID, val)
    89. 

  89. #define bfin_read_UART1_GCTL()		bfin_read32(UART1_GCTL)
    90. 

  90. #define bfin_write_UART1_GCTL(val)	bfin_write32(UART1_GCTL, val)
    91. 

  91. #define bfin_read_UART1_STAT()		bfin_read32(UART1_STAT)
    92. 

  92. #define bfin_write_UART1_STAT(val)	bfin_write32(UART1_STAT, val)
    93. 

  93. #define bfin_read_UART1_SCR()		bfin_read32(UART1_SCR)
    94. 

  94. #define bfin_write_UART1_SCR(val)	bfin_write32(UART1_SCR, val)
    95. 

  95. #define bfin_read_UART1_CLK()		bfin_read32(UART1_CLK)
    96. 

  96. #define bfin_write_UART1_CLK(val)	bfin_write32(UART1_CLK, val)
    97. 

  97. #define bfin_read_UART1_IER()		bfin_read32(UART1_IER)
    98. 

  98. #define bfin_write_UART1_IER(val)	bfin_write32(UART1_IER, val)
    99. 

  99. #define bfin_read_UART1_IER_SET()	bfin_read32(UART1_IER_SET)
    100. 

  100. #define bfin_write_UART1_IER_SET(val)	bfin_write32(UART1_IER_SET, val)
    101. 

  101. #define bfin_read_UART1_IER_CLEAR()	bfin_read32(UART1_IER_CLEAR)
    102. 

  102. #define bfin_write_UART1_IER_CLEAR(val)	bfin_write32(UART1_IER_CLEAR, val)
    103. 

  103. #define bfin_read_UART1_RBR()		bfin_read32(UART1_RBR)
    104. 

  104. #define bfin_write_UART1_RBR(val)	bfin_write32(UART1_RBR, val)
    105. 

  105. #define bfin_read_UART1_THR()		bfin_read32(UART1_THR)
    106. 

  106. #define bfin_write_UART1_THR(val)	bfin_write32(UART1_THR, val)
    107. 

  107. #define bfin_read_UART1_TAIP()		bfin_read32(UART1_TAIP)
    108. 

  108. #define bfin_write_UART1_TAIP(val)	bfin_write32(UART1_TAIP, val)
    109. 

  109. #define bfin_read_UART1_TSR()		bfin_read32(UART1_TSR)
    110. 

  110. #define bfin_write_UART1_TSR(val)	bfin_write32(UART1_TSR, val)
    111. 

  111. #define bfin_read_UART1_RSR()		bfin_read32(UART1_RSR)
    112. 

  112. #define bfin_write_UART1_RSR(val)	bfin_write32(UART1_RSR, val)
    113. 

  113. #define bfin_read_UART1_TXCNT()		bfin_read32(UART1_TXCNT)
    114. 

  114. #define bfin_write_UART1_TXCNT(val)	bfin_write32(UART1_TXCNT, val)
    115. 

  115. #define bfin_read_UART1_RXCNT()		bfin_read32(UART1_RXCNT)
    116. 

  116. #define bfin_write_UART1_RXCNT(val)	bfin_write32(UART1_RXCNT, val)
    117. 

  117. 

  118. 

  119. /* SPI0 Registers */
    120. 

  120. 

  121. #define bfin_read_SPI0_CTL()		bfin_read32(SPI0_CTL)
    122. 

  122. #define bfin_write_SPI0_CTL(val)	bfin_write32(SPI0_CTL, val)
    123. 

  123. #define bfin_read_SPI0_RXCTL()		bfin_read32(SPI0_RXCTL)
    124. 

  124. #define bfin_write_SPI0_RXCTL(val)	bfin_write32(SPI0_RXCTL, val)
    125. 

  125. #define bfin_read_SPI0_TXCTL()		bfin_read32(SPI0_TXCTL)
    126. 

  126. #define bfin_write_SPI0_TXCTL(val)	bfin_write32(SPI0_TXCTL, val)
    127. 

  127. #define bfin_read_SPI0_CLK()		bfin_read32(SPI0_CLK)
    128. 

  128. #define bfin_write_SPI0_CLK(val)	bfin_write32(SPI0_CLK, val)
    129. 

  129. #define bfin_read_SPI0_DLY()		bfin_read32(SPI0_DLY)
    130. 

  130. #define bfin_write_SPI0_DLY(val)	bfin_write32(SPI0_DLY, val)
    131. 

  131. #define bfin_read_SPI0_SLVSEL()		bfin_read32(SPI0_SLVSEL)
    132. 

  132. #define bfin_write_SPI0_SLVSEL(val)	bfin_write32(SPI0_SLVSEL, val)
    133. 

  133. #define bfin_read_SPI0_RWC()		bfin_read32(SPI0_RWC)
    134. 

  134. #define bfin_write_SPI0_RWC(val)	bfin_write32(SPI0_RWC, val)
    135. 

  135. #define bfin_read_SPI0_RWCR()		bfin_read32(SPI0_RWCR)
    136. 

  136. #define bfin_write_SPI0_RWCR(val)	bfin_write32(SPI0_RWCR, val)
    137. 

  137. #define bfin_read_SPI0_TWC()		bfin_read32(SPI0_TWC)
    138. 

  138. #define bfin_write_SPI0_TWC(val)	bfin_write32(SPI0_TWC, val)
    139. 

  139. #define bfin_read_SPI0_TWCR()		bfin_read32(SPI0_TWCR)
    140. 

  140. #define bfin_write_SPI0_TWCR(val)	bfin_write32(SPI0_TWCR, val)
    141. 

  141. #define bfin_read_SPI0_IMSK()		bfin_read32(SPI0_IMSK)
    142. 

  142. #define bfin_write_SPI0_IMSK(val)	bfin_write32(SPI0_IMSK, val)
    143. 

  143. #define bfin_read_SPI0_IMSK_CLR()	bfin_read32(SPI0_IMSK_CLR)
    144. 

  144. #define bfin_write_SPI0_IMSK_CLR(val)	bfin_write32(SPI0_IMSK_CLR, val)
    145. 

  145. #define bfin_read_SPI0_IMSK_SET()	bfin_read32(SPI0_IMSK_SET)
    146. 

  146. #define bfin_write_SPI0_IMSK_SET(val)	bfin_write32(SPI0_IMSK_SET, val)
    147. 

  147. #define bfin_read_SPI0_STAT()		bfin_read32(SPI0_STAT)
    148. 

  148. #define bfin_write_SPI0_STAT(val)	bfin_write32(SPI0_STAT, val)
    149. 

  149. #define bfin_read_SPI0_ILAT()		bfin_read32(SPI0_ILAT)
    150. 

  150. #define bfin_write_SPI0_ILAT(val)	bfin_write32(SPI0_ILAT, val)
    151. 

  151. #define bfin_read_SPI0_ILAT_CLR()	bfin_read32(SPI0_ILAT_CLR)
    152. 

  152. #define bfin_write_SPI0_ILAT_CLR(val)	bfin_write32(SPI0_ILAT_CLR, val)
    153. 

  153. #define bfin_read_SPI0_RFIFO()		bfin_read32(SPI0_RFIFO)
    154. 

  154. #define bfin_write_SPI0_RFIFO(val)	bfin_write32(SPI0_RFIFO, val)
    155. 

  155. #define bfin_read_SPI0_TFIFO()		bfin_read32(SPI0_TFIFO)
    156. 

  156. #define bfin_write_SPI0_TFIFO(val)	bfin_write32(SPI0_TFIFO, val)
    157. 

  157. 

  158. /* SPI1 Registers */
    159. 

  159. 

  160. #define bfin_read_SPI1_CTL()		bfin_read32(SPI1_CTL)
    161. 

  161. #define bfin_write_SPI1_CTL(val)	bfin_write32(SPI1_CTL, val)
    162. 

  162. #define bfin_read_SPI1_RXCTL()		bfin_read32(SPI1_RXCTL)
    163. 

  163. #define bfin_write_SPI1_RXCTL(val)	bfin_write32(SPI1_RXCTL, val)
    164. 

  164. #define bfin_read_SPI1_TXCTL()		bfin_read32(SPI1_TXCTL)
    165. 

  165. #define bfin_write_SPI1_TXCTL(val)	bfin_write32(SPI1_TXCTL, val)
    166. 

  166. #define bfin_read_SPI1_CLK()		bfin_read32(SPI1_CLK)
    167. 

  167. #define bfin_write_SPI1_CLK(val)	bfin_write32(SPI1_CLK, val)
    168. 

  168. #define bfin_read_SPI1_DLY()		bfin_read32(SPI1_DLY)
    169. 

  169. #define bfin_write_SPI1_DLY(val)	bfin_write32(SPI1_DLY, val)
    170. 

  170. #define bfin_read_SPI1_SLVSEL()		bfin_read32(SPI1_SLVSEL)
    171. 

  171. #define bfin_write_SPI1_SLVSEL(val)	bfin_write32(SPI1_SLVSEL, val)
    172. 

  172. #define bfin_read_SPI1_RWC()		bfin_read32(SPI1_RWC)
    173. 

  173. #define bfin_write_SPI1_RWC(val)	bfin_write32(SPI1_RWC, val)
    174. 

  174. #define bfin_read_SPI1_RWCR()		bfin_read32(SPI1_RWCR)
    175. 

  175. #define bfin_write_SPI1_RWCR(val)	bfin_write32(SPI1_RWCR, val)
    176. 

  176. #define bfin_read_SPI1_TWC()		bfin_read32(SPI1_TWC)
    177. 

  177. #define bfin_write_SPI1_TWC(val)	bfin_write32(SPI1_TWC, val)
    178. 

  178. #define bfin_read_SPI1_TWCR()		bfin_read32(SPI1_TWCR)
    179. 

  179. #define bfin_write_SPI1_TWCR(val)	bfin_write32(SPI1_TWCR, val)
    180. 

  180. #define bfin_read_SPI1_IMSK()		bfin_read32(SPI1_IMSK)
    181. 

  181. #define bfin_write_SPI1_IMSK(val)	bfin_write32(SPI1_IMSK, val)
    182. 

  182. #define bfin_read_SPI1_IMSK_CLR()	bfin_read32(SPI1_IMSK_CLR)
    183. 

  183. #define bfin_write_SPI1_IMSK_CLR(val)	bfin_write32(SPI1_IMSK_CLR, val)
    184. 

  184. #define bfin_read_SPI1_IMSK_SET()	bfin_read32(SPI1_IMSK_SET)
    185. 

  185. #define bfin_write_SPI1_IMSK_SET(val)	bfin_write32(SPI1_IMSK_SET, val)
    186. 

  186. #define bfin_read_SPI1_STAT()		bfin_read32(SPI1_STAT)
    187. 

  187. #define bfin_write_SPI1_STAT(val)	bfin_write32(SPI1_STAT, val)
    188. 

  188. #define bfin_read_SPI1_ILAT()		bfin_read32(SPI1_ILAT)
    189. 

  189. #define bfin_write_SPI1_ILAT(val)	bfin_write32(SPI1_ILAT, val)
    190. 

  190. #define bfin_read_SPI1_ILAT_CLR()	bfin_read32(SPI1_ILAT_CLR)
    191. 

  191. #define bfin_write_SPI1_ILAT_CLR(val)	bfin_write32(SPI1_ILAT_CLR, val)
    192. 

  192. #define bfin_read_SPI1_RFIFO()		bfin_read32(SPI1_RFIFO)
    193. 

  193. #define bfin_write_SPI1_RFIFO(val)	bfin_write32(SPI1_RFIFO, val)
    194. 

  194. #define bfin_read_SPI1_TFIFO()		bfin_read32(SPI1_TFIFO)
    195. 

  195. #define bfin_write_SPI1_TFIFO(val)	bfin_write32(SPI1_TFIFO, val)
    196. 

  196. 

  197. /* Timer 0-7 registers */
    198. 

  198. #define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
    199. 

  199. #define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG, val)
    200. 

  200. #define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
    201. 

  201. #define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER, val)
    202. 

  202. #define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
    203. 

  203. #define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD, val)
    204. 

  204. #define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
    205. 

  205. #define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH, val)
    206. 

  206. #define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
    207. 

  207. #define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG, val)
    208. 

  208. #define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
    209. 

  209. #define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER, val)
    210. 

  210. #define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
    211. 

  211. #define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD, val)
    212. 

  212. #define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
    213. 

  213. #define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH, val)
    214. 

  214. #define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
    215. 

  215. #define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG, val)
    216. 

  216. #define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
    217. 

  217. #define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER, val)
    218. 

  218. #define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
    219. 

  219. #define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD, val)
    220. 

  220. #define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
    221. 

  221. #define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH, val)
    222. 

  222. #define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
    223. 

  223. #define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG, val)
    224. 

  224. #define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
    225. 

  225. #define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER, val)
    226. 

  226. #define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
    227. 

  227. #define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD, val)
    228. 

  228. #define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
    229. 

  229. #define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH, val)
    230. 

  230. #define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
    231. 

  231. #define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG, val)
    232. 

  232. #define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
    233. 

  233. #define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER, val)
    234. 

  234. #define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
    235. 

  235. #define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD, val)
    236. 

  236. #define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
    237. 

  237. #define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH, val)
    238. 

  238. #define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
    239. 

  239. #define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG, val)
    240. 

  240. #define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
    241. 

  241. #define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER, val)
    242. 

  242. #define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
    243. 

  243. #define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD, val)
    244. 

  244. #define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
    245. 

  245. #define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH, val)
    246. 

  246. #define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
    247. 

  247. #define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG, val)
    248. 

  248. #define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
    249. 

  249. #define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER, val)
    250. 

  250. #define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
    251. 

  251. #define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD, val)
    252. 

  252. #define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
    253. 

  253. #define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH, val)
    254. 

  254. #define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
    255. 

  255. #define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG, val)
    256. 

  256. #define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
    257. 

  257. #define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER, val)
    258. 

  258. #define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
    259. 

  259. #define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD, val)
    260. 

  260. #define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
    261. 

  261. #define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH, val)
    262. 

  262. 

  263. 

  264. 

  265. 

  266. /* Two Wire Interface Registers (TWI0) */
    267. 

  267. 

  268. /* SPORT1 Registers */
    269. 

  269. 

  270. 

  271. /* SMC Registers */
    272. 

  272. #define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
    273. 

  273. #define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
    274. 

  274. #define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
    275. 

  275. #define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
    276. 

  276. #define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
    277. 

  277. #define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
    278. 

  278. #define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
    279. 

  279. #define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
    280. 

  280. #define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
    281. 

  281. #define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
    282. 

  282. #define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
    283. 

  283. #define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
    284. 

  284. #define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
    285. 

  285. #define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
    286. 

  286. #define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
    287. 

  287. #define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
    288. 

  288. #define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
    289. 

  289. #define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
    290. 

  290. #define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
    291. 

  291. #define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
    292. 

  292. #define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
    293. 

  293. #define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
    294. 

  294. #define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
    295. 

  295. #define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
    296. 

  296. #define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
    297. 

  297. #define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
    298. 

  298. #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
    299. 

  299. 

  300. /* DDR2 Memory Control Registers */
    301. 

  301. #define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
    302. 

  302. #define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
    303. 

  303. #define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
    304. 

  304. #define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
    305. 

  305. #define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
    306. 

  306. #define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
    307. 

  307. #define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
    308. 

  308. #define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
    309. 

  309. #define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
    310. 

  310. #define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
    311. 

  311. #define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
    312. 

  312. #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
    313. 

  313. #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
    314. 

  314. #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
    315. 

  315. #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
    316. 

  316. #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
    317. 

  317. #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
    318. 

  318. #define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
    319. 

  319. 

  320. /* DDR BankRead and Write Count Registers */
    321. 

  321. 

  322. 

  323. /* DMA Channel 0 Registers */
    324. 

  324. 

  325. #define bfin_read_DMA0_NEXT_DESC_PTR() 		bfin_read32(DMA0_NEXT_DESC_PTR)
    326. 

  326. #define bfin_write_DMA0_NEXT_DESC_PTR(val) 	bfin_write32(DMA0_NEXT_DESC_PTR, val)
    327. 

  327. #define bfin_read_DMA0_START_ADDR() 		bfin_read32(DMA0_START_ADDR)
    328. 

  328. #define bfin_write_DMA0_START_ADDR(val) 	bfin_write32(DMA0_START_ADDR, val)
    329. 

  329. #define bfin_read_DMA0_CONFIG()			bfin_read32(DMA0_CONFIG)
    330. 

  330. #define bfin_write_DMA0_CONFIG(val)		bfin_write32(DMA0_CONFIG, val)
    331. 

  331. #define bfin_read_DMA0_X_COUNT()		bfin_read32(DMA0_X_COUNT)
    332. 

  332. #define bfin_write_DMA0_X_COUNT(val)		bfin_write32(DMA0_X_COUNT, val)
    333. 

  333. #define bfin_read_DMA0_X_MODIFY()		bfin_read32(DMA0_X_MODIFY)
    334. 

  334. #define bfin_write_DMA0_X_MODIFY(val) 		bfin_write32(DMA0_X_MODIFY, val)
    335. 

  335. #define bfin_read_DMA0_Y_COUNT()		bfin_read32(DMA0_Y_COUNT)
    336. 

  336. #define bfin_write_DMA0_Y_COUNT(val)		bfin_write32(DMA0_Y_COUNT, val)
    337. 

  337. #define bfin_read_DMA0_Y_MODIFY()		bfin_read32(DMA0_Y_MODIFY)
    338. 

  338. #define bfin_write_DMA0_Y_MODIFY(val) 		bfin_write32(DMA0_Y_MODIFY, val)
    339. 

  339. #define bfin_read_DMA0_CURR_DESC_PTR() 		bfin_read32(DMA0_CURR_DESC_PTR)
    340. 

  340. #define bfin_write_DMA0_CURR_DESC_PTR(val) 	bfin_write32(DMA0_CURR_DESC_PTR, val)
    341. 

  341. #define bfin_read_DMA0_PREV_DESC_PTR() 		bfin_read32(DMA0_PREV_DESC_PTR)
    342. 

  342. #define bfin_write_DMA0_PREV_DESC_PTR(val) 	bfin_write32(DMA0_PREV_DESC_PTR, val)
    343. 

  343. #define bfin_read_DMA0_CURR_ADDR() 		bfin_read32(DMA0_CURR_ADDR)
    344. 

  344. #define bfin_write_DMA0_CURR_ADDR(val) 		bfin_write32(DMA0_CURR_ADDR, val)
    345. 

  345. #define bfin_read_DMA0_IRQ_STATUS()		bfin_read32(DMA0_IRQ_STATUS)
    346. 

  346. #define bfin_write_DMA0_IRQ_STATUS(val)		bfin_write32(DMA0_IRQ_STATUS, val)
    347. 

  347. #define bfin_read_DMA0_CURR_X_COUNT()		bfin_read32(DMA0_CURR_X_COUNT)
    348. 

  348. #define bfin_write_DMA0_CURR_X_COUNT(val)	bfin_write32(DMA0_CURR_X_COUNT, val)
    349. 

  349. #define bfin_read_DMA0_CURR_Y_COUNT()		bfin_read32(DMA0_CURR_Y_COUNT)
    350. 

  350. #define bfin_write_DMA0_CURR_Y_COUNT(val)	bfin_write32(DMA0_CURR_Y_COUNT, val)
    351. 

  351. #define bfin_read_DMA0_BWL_COUNT()		bfin_read32(DMA0_BWL_COUNT)
    352. 

  352. #define bfin_write_DMA0_BWL_COUNT(val)		bfin_write32(DMA0_BWL_COUNT, val)
    353. 

  353. #define bfin_read_DMA0_CURR_BWL_COUNT()		bfin_read32(DMA0_CURR_BWL_COUNT)
    354. 

  354. #define bfin_write_DMA0_CURR_BWL_COUNT(val)	bfin_write32(DMA0_CURR_BWL_COUNT, val)
    355. 

  355. #define bfin_read_DMA0_BWM_COUNT()		bfin_read32(DMA0_BWM_COUNT)
    356. 

  356. #define bfin_write_DMA0_BWM_COUNT(val)		bfin_write32(DMA0_BWM_COUNT, val)
    357. 

  357. #define bfin_read_DMA0_CURR_BWM_COUNT()		bfin_read32(DMA0_CURR_BWM_COUNT)
    358. 

  358. #define bfin_write_DMA0_CURR_BWM_COUNT(val)	bfin_write32(DMA0_CURR_BWM_COUNT, val)
    359. 

  359. 

  360. /* DMA Channel 1 Registers */
    361. 

  361. 

  362. #define bfin_read_DMA1_NEXT_DESC_PTR() 		bfin_read32(DMA1_NEXT_DESC_PTR)
    363. 

  363. #define bfin_write_DMA1_NEXT_DESC_PTR(val) 	bfin_write32(DMA1_NEXT_DESC_PTR, val)
    364. 

  364. #define bfin_read_DMA1_START_ADDR() 		bfin_read32(DMA1_START_ADDR)
    365. 

  365. #define bfin_write_DMA1_START_ADDR(val) 	bfin_write32(DMA1_START_ADDR, val)
    366. 

  366. #define bfin_read_DMA1_CONFIG()			bfin_read32(DMA1_CONFIG)
    367. 

  367. #define bfin_write_DMA1_CONFIG(val)		bfin_write32(DMA1_CONFIG, val)
    368. 

  368. #define bfin_read_DMA1_X_COUNT()		bfin_read32(DMA1_X_COUNT)
    369. 

  369. #define bfin_write_DMA1_X_COUNT(val)		bfin_write32(DMA1_X_COUNT, val)
    370. 

  370. #define bfin_read_DMA1_X_MODIFY()		bfin_read32(DMA1_X_MODIFY)
    371. 

  371. #define bfin_write_DMA1_X_MODIFY(val) 		bfin_write32(DMA1_X_MODIFY, val)
    372. 

  372. #define bfin_read_DMA1_Y_COUNT()		bfin_read32(DMA1_Y_COUNT)
    373. 

  373. #define bfin_write_DMA1_Y_COUNT(val)		bfin_write32(DMA1_Y_COUNT, val)
    374. 

  374. #define bfin_read_DMA1_Y_MODIFY()		bfin_read32(DMA1_Y_MODIFY)
    375. 

  375. #define bfin_write_DMA1_Y_MODIFY(val) 		bfin_write32(DMA1_Y_MODIFY, val)
    376. 

  376. #define bfin_read_DMA1_CURR_DESC_PTR() 		bfin_read32(DMA1_CURR_DESC_PTR)
    377. 

  377. #define bfin_write_DMA1_CURR_DESC_PTR(val) 	bfin_write32(DMA1_CURR_DESC_PTR, val)
    378. 

  378. #define bfin_read_DMA1_PREV_DESC_PTR() 		bfin_read32(DMA1_PREV_DESC_PTR)
    379. 

  379. #define bfin_write_DMA1_PREV_DESC_PTR(val) 	bfin_write32(DMA1_PREV_DESC_PTR, val)
    380. 

  380. #define bfin_read_DMA1_CURR_ADDR() 		bfin_read32(DMA1_CURR_ADDR)
    381. 

  381. #define bfin_write_DMA1_CURR_ADDR(val) 		bfin_write32(DMA1_CURR_ADDR, val)
    382. 

  382. #define bfin_read_DMA1_IRQ_STATUS()		bfin_read32(DMA1_IRQ_STATUS)
    383. 

  383. #define bfin_write_DMA1_IRQ_STATUS(val)		bfin_write32(DMA1_IRQ_STATUS, val)
    384. 

  384. #define bfin_read_DMA1_CURR_X_COUNT()		bfin_read32(DMA1_CURR_X_COUNT)
    385. 

  385. #define bfin_write_DMA1_CURR_X_COUNT(val)	bfin_write32(DMA1_CURR_X_COUNT, val)
    386. 

  386. #define bfin_read_DMA1_CURR_Y_COUNT()		bfin_read32(DMA1_CURR_Y_COUNT)
    387. 

  387. #define bfin_write_DMA1_CURR_Y_COUNT(val)	bfin_write32(DMA1_CURR_Y_COUNT, val)
    388. 

  388. #define bfin_read_DMA1_BWL_COUNT()		bfin_read32(DMA1_BWL_COUNT)
    389. 

  389. #define bfin_write_DMA1_BWL_COUNT(val)		bfin_write32(DMA1_BWL_COUNT, val)
    390. 

  390. #define bfin_read_DMA1_CURR_BWL_COUNT()		bfin_read32(DMA1_CURR_BWL_COUNT)
    391. 

  391. #define bfin_write_DMA1_CURR_BWL_COUNT(val)	bfin_write32(DMA1_CURR_BWL_COUNT, val)
    392. 

  392. #define bfin_read_DMA1_BWM_COUNT()		bfin_read32(DMA1_BWM_COUNT)
    393. 

  393. #define bfin_write_DMA1_BWM_COUNT(val)		bfin_write32(DMA1_BWM_COUNT, val)
    394. 

  394. #define bfin_read_DMA1_CURR_BWM_COUNT()		bfin_read32(DMA1_CURR_BWM_COUNT)
    395. 

  395. #define bfin_write_DMA1_CURR_BWM_COUNT(val)	bfin_write32(DMA1_CURR_BWM_COUNT, val)
    396. 

  396. 

  397. /* DMA Channel 2 Registers */
    398. 

  398. 

  399. #define bfin_read_DMA2_NEXT_DESC_PTR() 		bfin_read32(DMA2_NEXT_DESC_PTR)
    400. 

  400. #define bfin_write_DMA2_NEXT_DESC_PTR(val) 	bfin_write32(DMA2_NEXT_DESC_PTR, val)
    401. 

  401. #define bfin_read_DMA2_START_ADDR() 		bfin_read32(DMA2_START_ADDR)
    402. 

  402. #define bfin_write_DMA2_START_ADDR(val) 	bfin_write32(DMA2_START_ADDR, val)
    403. 

  403. #define bfin_read_DMA2_CONFIG()			bfin_read32(DMA2_CONFIG)
    404. 

  404. #define bfin_write_DMA2_CONFIG(val)		bfin_write32(DMA2_CONFIG, val)
    405. 

  405. #define bfin_read_DMA2_X_COUNT()		bfin_read32(DMA2_X_COUNT)
    406. 

  406. #define bfin_write_DMA2_X_COUNT(val)		bfin_write32(DMA2_X_COUNT, val)
    407. 

  407. #define bfin_read_DMA2_X_MODIFY()		bfin_read32(DMA2_X_MODIFY)
    408. 

  408. #define bfin_write_DMA2_X_MODIFY(val) 		bfin_write32(DMA2_X_MODIFY, val)
    409. 

  409. #define bfin_read_DMA2_Y_COUNT()		bfin_read32(DMA2_Y_COUNT)
    410. 

  410. #define bfin_write_DMA2_Y_COUNT(val)		bfin_write32(DMA2_Y_COUNT, val)
    411. 

  411. #define bfin_read_DMA2_Y_MODIFY()		bfin_read32(DMA2_Y_MODIFY)
    412. 

  412. #define bfin_write_DMA2_Y_MODIFY(val) 		bfin_write32(DMA2_Y_MODIFY, val)
    413. 

  413. #define bfin_read_DMA2_CURR_DESC_PTR() 		bfin_read32(DMA2_CURR_DESC_PTR)
    414. 

  414. #define bfin_write_DMA2_CURR_DESC_PTR(val) 	bfin_write32(DMA2_CURR_DESC_PTR, val)
    415. 

  415. #define bfin_read_DMA2_PREV_DESC_PTR() 		bfin_read32(DMA2_PREV_DESC_PTR)
    416. 

  416. #define bfin_write_DMA2_PREV_DESC_PTR(val) 	bfin_write32(DMA2_PREV_DESC_PTR, val)
    417. 

  417. #define bfin_read_DMA2_CURR_ADDR() 		bfin_read32(DMA2_CURR_ADDR)
    418. 

  418. #define bfin_write_DMA2_CURR_ADDR(val) 		bfin_write32(DMA2_CURR_ADDR, val)
    419. 

  419. #define bfin_read_DMA2_IRQ_STATUS()		bfin_read32(DMA2_IRQ_STATUS)
    420. 

  420. #define bfin_write_DMA2_IRQ_STATUS(val)		bfin_write32(DMA2_IRQ_STATUS, val)
    421. 

  421. #define bfin_read_DMA2_CURR_X_COUNT()		bfin_read32(DMA2_CURR_X_COUNT)
    422. 

  422. #define bfin_write_DMA2_CURR_X_COUNT(val)	bfin_write32(DMA2_CURR_X_COUNT, val)
    423. 

  423. #define bfin_read_DMA2_CURR_Y_COUNT()		bfin_read32(DMA2_CURR_Y_COUNT)
    424. 

  424. #define bfin_write_DMA2_CURR_Y_COUNT(val)	bfin_write32(DMA2_CURR_Y_COUNT, val)
    425. 

  425. #define bfin_read_DMA2_BWL_COUNT()		bfin_read32(DMA2_BWL_COUNT)
    426. 

  426. #define bfin_write_DMA2_BWL_COUNT(val)		bfin_write32(DMA2_BWL_COUNT, val)
    427. 

  427. #define bfin_read_DMA2_CURR_BWL_COUNT()		bfin_read32(DMA2_CURR_BWL_COUNT)
    428. 

  428. #define bfin_write_DMA2_CURR_BWL_COUNT(val)	bfin_write32(DMA2_CURR_BWL_COUNT, val)
    429. 

  429. #define bfin_read_DMA2_BWM_COUNT()		bfin_read32(DMA2_BWM_COUNT)
    430. 

  430. #define bfin_write_DMA2_BWM_COUNT(val)		bfin_write32(DMA2_BWM_COUNT, val)
    431. 

  431. #define bfin_read_DMA2_CURR_BWM_COUNT()		bfin_read32(DMA2_CURR_BWM_COUNT)
    432. 

  432. #define bfin_write_DMA2_CURR_BWM_COUNT(val)	bfin_write32(DMA2_CURR_BWM_COUNT, val)
    433. 

  433. 

  434. /* DMA Channel 3 Registers */
    435. 

  435. 

  436. #define bfin_read_DMA3_NEXT_DESC_PTR() 		bfin_read32(DMA3_NEXT_DESC_PTR)
    437. 

  437. #define bfin_write_DMA3_NEXT_DESC_PTR(val) 	bfin_write32(DMA3_NEXT_DESC_PTR, val)
    438. 

  438. #define bfin_read_DMA3_START_ADDR() 		bfin_read32(DMA3_START_ADDR)
    439. 

  439. #define bfin_write_DMA3_START_ADDR(val) 	bfin_write32(DMA3_START_ADDR, val)
    440. 

  440. #define bfin_read_DMA3_CONFIG()			bfin_read32(DMA3_CONFIG)
    441. 

  441. #define bfin_write_DMA3_CONFIG(val)		bfin_write32(DMA3_CONFIG, val)
    442. 

  442. #define bfin_read_DMA3_X_COUNT()		bfin_read32(DMA3_X_COUNT)
    443. 

  443. #define bfin_write_DMA3_X_COUNT(val)		bfin_write32(DMA3_X_COUNT, val)
    444. 

  444. #define bfin_read_DMA3_X_MODIFY()		bfin_read32(DMA3_X_MODIFY)
    445. 

  445. #define bfin_write_DMA3_X_MODIFY(val) 		bfin_write32(DMA3_X_MODIFY, val)
    446. 

  446. #define bfin_read_DMA3_Y_COUNT()		bfin_read32(DMA3_Y_COUNT)
    447. 

  447. #define bfin_write_DMA3_Y_COUNT(val)		bfin_write32(DMA3_Y_COUNT, val)
    448. 

  448. #define bfin_read_DMA3_Y_MODIFY()		bfin_read32(DMA3_Y_MODIFY)
    449. 

  449. #define bfin_write_DMA3_Y_MODIFY(val) 		bfin_write32(DMA3_Y_MODIFY, val)
    450. 

  450. #define bfin_read_DMA3_CURR_DESC_PTR() 		bfin_read32(DMA3_CURR_DESC_PTR)
    451. 

  451. #define bfin_write_DMA3_CURR_DESC_PTR(val) 	bfin_write32(DMA3_CURR_DESC_PTR, val)
    452. 

  452. #define bfin_read_DMA3_PREV_DESC_PTR() 		bfin_read32(DMA3_PREV_DESC_PTR)
    453. 

  453. #define bfin_write_DMA3_PREV_DESC_PTR(val) 	bfin_write32(DMA3_PREV_DESC_PTR, val)
    454. 

  454. #define bfin_read_DMA3_CURR_ADDR() 		bfin_read32(DMA3_CURR_ADDR)
    455. 

  455. #define bfin_write_DMA3_CURR_ADDR(val) 		bfin_write32(DMA3_CURR_ADDR, val)
    456. 

  456. #define bfin_read_DMA3_IRQ_STATUS()		bfin_read32(DMA3_IRQ_STATUS)
    457. 

  457. #define bfin_write_DMA3_IRQ_STATUS(val)		bfin_write32(DMA3_IRQ_STATUS, val)
    458. 

  458. #define bfin_read_DMA3_CURR_X_COUNT()		bfin_read32(DMA3_CURR_X_COUNT)
    459. 

  459. #define bfin_write_DMA3_CURR_X_COUNT(val)	bfin_write32(DMA3_CURR_X_COUNT, val)
    460. 

  460. #define bfin_read_DMA3_CURR_Y_COUNT()		bfin_read32(DMA3_CURR_Y_COUNT)
    461. 

  461. #define bfin_write_DMA3_CURR_Y_COUNT(val)	bfin_write32(DMA3_CURR_Y_COUNT, val)
    462. 

  462. #define bfin_read_DMA3_BWL_COUNT()		bfin_read32(DMA3_BWL_COUNT)
    463. 

  463. #define bfin_write_DMA3_BWL_COUNT(val)		bfin_write32(DMA3_BWL_COUNT, val)
    464. 

  464. #define bfin_read_DMA3_CURR_BWL_COUNT()		bfin_read32(DMA3_CURR_BWL_COUNT)
    465. 

  465. #define bfin_write_DMA3_CURR_BWL_COUNT(val)	bfin_write32(DMA3_CURR_BWL_COUNT, val)
    466. 

  466. #define bfin_read_DMA3_BWM_COUNT()		bfin_read32(DMA3_BWM_COUNT)
    467. 

  467. #define bfin_write_DMA3_BWM_COUNT(val)		bfin_write32(DMA3_BWM_COUNT, val)
    468. 

  468. #define bfin_read_DMA3_CURR_BWM_COUNT()		bfin_read32(DMA3_CURR_BWM_COUNT)
    469. 

  469. #define bfin_write_DMA3_CURR_BWM_COUNT(val)	bfin_write32(DMA3_CURR_BWM_COUNT, val)
    470. 

  470. 

  471. /* DMA Channel 4 Registers */
    472. 

  472. 

  473. #define bfin_read_DMA4_NEXT_DESC_PTR() 		bfin_read32(DMA4_NEXT_DESC_PTR)
    474. 

  474. #define bfin_write_DMA4_NEXT_DESC_PTR(val) 	bfin_write32(DMA4_NEXT_DESC_PTR, val)
    475. 

  475. #define bfin_read_DMA4_START_ADDR() 		bfin_read32(DMA4_START_ADDR)
    476. 

  476. #define bfin_write_DMA4_START_ADDR(val) 	bfin_write32(DMA4_START_ADDR, val)
    477. 

  477. #define bfin_read_DMA4_CONFIG()			bfin_read32(DMA4_CONFIG)
    478. 

  478. #define bfin_write_DMA4_CONFIG(val)		bfin_write32(DMA4_CONFIG, val)
    479. 

  479. #define bfin_read_DMA4_X_COUNT()		bfin_read32(DMA4_X_COUNT)
    480. 

  480. #define bfin_write_DMA4_X_COUNT(val)		bfin_write32(DMA4_X_COUNT, val)
    481. 

  481. #define bfin_read_DMA4_X_MODIFY()		bfin_read32(DMA4_X_MODIFY)
    482. 

  482. #define bfin_write_DMA4_X_MODIFY(val) 		bfin_write32(DMA4_X_MODIFY, val)
    483. 

  483. #define bfin_read_DMA4_Y_COUNT()		bfin_read32(DMA4_Y_COUNT)
    484. 

  484. #define bfin_write_DMA4_Y_COUNT(val)		bfin_write32(DMA4_Y_COUNT, val)
    485. 

  485. #define bfin_read_DMA4_Y_MODIFY()		bfin_read32(DMA4_Y_MODIFY)
    486. 

  486. #define bfin_write_DMA4_Y_MODIFY(val) 		bfin_write32(DMA4_Y_MODIFY, val)
    487. 

  487. #define bfin_read_DMA4_CURR_DESC_PTR() 		bfin_read32(DMA4_CURR_DESC_PTR)
    488. 

  488. #define bfin_write_DMA4_CURR_DESC_PTR(val) 	bfin_write32(DMA4_CURR_DESC_PTR, val)
    489. 

  489. #define bfin_read_DMA4_PREV_DESC_PTR() 		bfin_read32(DMA4_PREV_DESC_PTR)
    490. 

  490. #define bfin_write_DMA4_PREV_DESC_PTR(val) 	bfin_write32(DMA4_PREV_DESC_PTR, val)
    491. 

  491. #define bfin_read_DMA4_CURR_ADDR() 		bfin_read32(DMA4_CURR_ADDR)
    492. 

  492. #define bfin_write_DMA4_CURR_ADDR(val) 		bfin_write32(DMA4_CURR_ADDR, val)
    493. 

  493. #define bfin_read_DMA4_IRQ_STATUS()		bfin_read32(DMA4_IRQ_STATUS)
    494. 

  494. #define bfin_write_DMA4_IRQ_STATUS(val)		bfin_write32(DMA4_IRQ_STATUS, val)
    495. 

  495. #define bfin_read_DMA4_CURR_X_COUNT()		bfin_read32(DMA4_CURR_X_COUNT)
    496. 

  496. #define bfin_write_DMA4_CURR_X_COUNT(val)	bfin_write32(DMA4_CURR_X_COUNT, val)
    497. 

  497. #define bfin_read_DMA4_CURR_Y_COUNT()		bfin_read32(DMA4_CURR_Y_COUNT)
    498. 

  498. #define bfin_write_DMA4_CURR_Y_COUNT(val)	bfin_write32(DMA4_CURR_Y_COUNT, val)
    499. 

  499. #define bfin_read_DMA4_BWL_COUNT()		bfin_read32(DMA4_BWL_COUNT)
    500. 

  500. #define bfin_write_DMA4_BWL_COUNT(val)		bfin_write32(DMA4_BWL_COUNT, val)
    501. 

  501. #define bfin_read_DMA4_CURR_BWL_COUNT()		bfin_read32(DMA4_CURR_BWL_COUNT)
    502. 

  502. #define bfin_write_DMA4_CURR_BWL_COUNT(val)	bfin_write32(DMA4_CURR_BWL_COUNT, val)
    503. 

  503. #define bfin_read_DMA4_BWM_COUNT()		bfin_read32(DMA4_BWM_COUNT)
    504. 

  504. #define bfin_write_DMA4_BWM_COUNT(val)		bfin_write32(DMA4_BWM_COUNT, val)
    505. 

  505. #define bfin_read_DMA4_CURR_BWM_COUNT()		bfin_read32(DMA4_CURR_BWM_COUNT)
    506. 

  506. #define bfin_write_DMA4_CURR_BWM_COUNT(val)	bfin_write32(DMA4_CURR_BWM_COUNT, val)
    507. 

  507. 

  508. /* DMA Channel 5 Registers */
    509. 

  509. 

  510. #define bfin_read_DMA5_NEXT_DESC_PTR() 		bfin_read32(DMA5_NEXT_DESC_PTR)
    511. 

  511. #define bfin_write_DMA5_NEXT_DESC_PTR(val) 	bfin_write32(DMA5_NEXT_DESC_PTR, val)
    512. 

  512. #define bfin_read_DMA5_START_ADDR() 		bfin_read32(DMA5_START_ADDR)
    513. 

  513. #define bfin_write_DMA5_START_ADDR(val) 	bfin_write32(DMA5_START_ADDR, val)
    514. 

  514. #define bfin_read_DMA5_CONFIG()			bfin_read32(DMA5_CONFIG)
    515. 

  515. #define bfin_write_DMA5_CONFIG(val)		bfin_write32(DMA5_CONFIG, val)
    516. 

  516. #define bfin_read_DMA5_X_COUNT()		bfin_read32(DMA5_X_COUNT)
    517. 

  517. #define bfin_write_DMA5_X_COUNT(val)		bfin_write32(DMA5_X_COUNT, val)
    518. 

  518. #define bfin_read_DMA5_X_MODIFY()		bfin_read32(DMA5_X_MODIFY)
    519. 

  519. #define bfin_write_DMA5_X_MODIFY(val) 		bfin_write32(DMA5_X_MODIFY, val)
    520. 

  520. #define bfin_read_DMA5_Y_COUNT()		bfin_read32(DMA5_Y_COUNT)
    521. 

  521. #define bfin_write_DMA5_Y_COUNT(val)		bfin_write32(DMA5_Y_COUNT, val)
    522. 

  522. #define bfin_read_DMA5_Y_MODIFY()		bfin_read32(DMA5_Y_MODIFY)
    523. 

  523. #define bfin_write_DMA5_Y_MODIFY(val) 		bfin_write32(DMA5_Y_MODIFY, val)
    524. 

  524. #define bfin_read_DMA5_CURR_DESC_PTR() 		bfin_read32(DMA5_CURR_DESC_PTR)
    525. 

  525. #define bfin_write_DMA5_CURR_DESC_PTR(val) 	bfin_write32(DMA5_CURR_DESC_PTR, val)
    526. 

  526. #define bfin_read_DMA5_PREV_DESC_PTR() 		bfin_read32(DMA5_PREV_DESC_PTR)
    527. 

  527. #define bfin_write_DMA5_PREV_DESC_PTR(val) 	bfin_write32(DMA5_PREV_DESC_PTR, val)
    528. 

  528. #define bfin_read_DMA5_CURR_ADDR() 		bfin_read32(DMA5_CURR_ADDR)
    529. 

  529. #define bfin_write_DMA5_CURR_ADDR(val) 		bfin_write32(DMA5_CURR_ADDR, val)
    530. 

  530. #define bfin_read_DMA5_IRQ_STATUS()		bfin_read32(DMA5_IRQ_STATUS)
    531. 

  531. #define bfin_write_DMA5_IRQ_STATUS(val)		bfin_write32(DMA5_IRQ_STATUS, val)
    532. 

  532. #define bfin_read_DMA5_CURR_X_COUNT()		bfin_read32(DMA5_CURR_X_COUNT)
    533. 

  533. #define bfin_write_DMA5_CURR_X_COUNT(val)	bfin_write32(DMA5_CURR_X_COUNT, val)
    534. 

  534. #define bfin_read_DMA5_CURR_Y_COUNT()		bfin_read32(DMA5_CURR_Y_COUNT)
    535. 

  535. #define bfin_write_DMA5_CURR_Y_COUNT(val)	bfin_write32(DMA5_CURR_Y_COUNT, val)
    536. 

  536. #define bfin_read_DMA5_BWL_COUNT()		bfin_read32(DMA5_BWL_COUNT)
    537. 

  537. #define bfin_write_DMA5_BWL_COUNT(val)		bfin_write32(DMA5_BWL_COUNT, val)
    538. 

  538. #define bfin_read_DMA5_CURR_BWL_COUNT()		bfin_read32(DMA5_CURR_BWL_COUNT)
    539. 

  539. #define bfin_write_DMA5_CURR_BWL_COUNT(val)	bfin_write32(DMA5_CURR_BWL_COUNT, val)
    540. 

  540. #define bfin_read_DMA5_BWM_COUNT()		bfin_read32(DMA5_BWM_COUNT)
    541. 

  541. #define bfin_write_DMA5_BWM_COUNT(val)		bfin_write32(DMA5_BWM_COUNT, val)
    542. 

  542. #define bfin_read_DMA5_CURR_BWM_COUNT()		bfin_read32(DMA5_CURR_BWM_COUNT)
    543. 

  543. #define bfin_write_DMA5_CURR_BWM_COUNT(val)	bfin_write32(DMA5_CURR_BWM_COUNT, val)
    544. 

  544. 

  545. /* DMA Channel 6 Registers */
    546. 

  546. 

  547. #define bfin_read_DMA6_NEXT_DESC_PTR() 		bfin_read32(DMA6_NEXT_DESC_PTR)
    548. 

  548. #define bfin_write_DMA6_NEXT_DESC_PTR(val) 	bfin_write32(DMA6_NEXT_DESC_PTR, val)
    549. 

  549. #define bfin_read_DMA6_START_ADDR() 		bfin_read32(DMA6_START_ADDR)
    550. 

  550. #define bfin_write_DMA6_START_ADDR(val) 	bfin_write32(DMA6_START_ADDR, val)
    551. 

  551. #define bfin_read_DMA6_CONFIG()			bfin_read32(DMA6_CONFIG)
    552. 

  552. #define bfin_write_DMA6_CONFIG(val)		bfin_write32(DMA6_CONFIG, val)
    553. 

  553. #define bfin_read_DMA6_X_COUNT()		bfin_read32(DMA6_X_COUNT)
    554. 

  554. #define bfin_write_DMA6_X_COUNT(val)		bfin_write32(DMA6_X_COUNT, val)
    555. 

  555. #define bfin_read_DMA6_X_MODIFY()		bfin_read32(DMA6_X_MODIFY)
    556. 

  556. #define bfin_write_DMA6_X_MODIFY(val) 		bfin_write32(DMA6_X_MODIFY, val)
    557. 

  557. #define bfin_read_DMA6_Y_COUNT()		bfin_read32(DMA6_Y_COUNT)
    558. 

  558. #define bfin_write_DMA6_Y_COUNT(val)		bfin_write32(DMA6_Y_COUNT, val)
    559. 

  559. #define bfin_read_DMA6_Y_MODIFY()		bfin_read32(DMA6_Y_MODIFY)
    560. 

  560. #define bfin_write_DMA6_Y_MODIFY(val) 		bfin_write32(DMA6_Y_MODIFY, val)
    561. 

  561. #define bfin_read_DMA6_CURR_DESC_PTR() 		bfin_read32(DMA6_CURR_DESC_PTR)
    562. 

  562. #define bfin_write_DMA6_CURR_DESC_PTR(val) 	bfin_write32(DMA6_CURR_DESC_PTR, val)
    563. 

  563. #define bfin_read_DMA6_PREV_DESC_PTR() 		bfin_read32(DMA6_PREV_DESC_PTR)
    564. 

  564. #define bfin_write_DMA6_PREV_DESC_PTR(val) 	bfin_write32(DMA6_PREV_DESC_PTR, val)
    565. 

  565. #define bfin_read_DMA6_CURR_ADDR() 		bfin_read32(DMA6_CURR_ADDR)
    566. 

  566. #define bfin_write_DMA6_CURR_ADDR(val) 		bfin_write32(DMA6_CURR_ADDR, val)
    567. 

  567. #define bfin_read_DMA6_IRQ_STATUS()		bfin_read32(DMA6_IRQ_STATUS)
    568. 

  568. #define bfin_write_DMA6_IRQ_STATUS(val)		bfin_write32(DMA6_IRQ_STATUS, val)
    569. 

  569. #define bfin_read_DMA6_CURR_X_COUNT()		bfin_read32(DMA6_CURR_X_COUNT)
    570. 

  570. #define bfin_write_DMA6_CURR_X_COUNT(val)	bfin_write32(DMA6_CURR_X_COUNT, val)
    571. 

  571. #define bfin_read_DMA6_CURR_Y_COUNT()		bfin_read32(DMA6_CURR_Y_COUNT)
    572. 

  572. #define bfin_write_DMA6_CURR_Y_COUNT(val)	bfin_write32(DMA6_CURR_Y_COUNT, val)
    573. 

  573. #define bfin_read_DMA6_BWL_COUNT()		bfin_read32(DMA6_BWL_COUNT)
    574. 

  574. #define bfin_write_DMA6_BWL_COUNT(val)		bfin_write32(DMA6_BWL_COUNT, val)
    575. 

  575. #define bfin_read_DMA6_CURR_BWL_COUNT()		bfin_read32(DMA6_CURR_BWL_COUNT)
    576. 

  576. #define bfin_write_DMA6_CURR_BWL_COUNT(val)	bfin_write32(DMA6_CURR_BWL_COUNT, val)
    577. 

  577. #define bfin_read_DMA6_BWM_COUNT()		bfin_read32(DMA6_BWM_COUNT)
    578. 

  578. #define bfin_write_DMA6_BWM_COUNT(val)		bfin_write32(DMA6_BWM_COUNT, val)
    579. 

  579. #define bfin_read_DMA6_CURR_BWM_COUNT()		bfin_read32(DMA6_CURR_BWM_COUNT)
    580. 

  580. #define bfin_write_DMA6_CURR_BWM_COUNT(val)	bfin_write32(DMA6_CURR_BWM_COUNT, val)
    581. 

  581. 

  582. /* DMA Channel 7 Registers */
    583. 

  583. 

  584. #define bfin_read_DMA7_NEXT_DESC_PTR() 		bfin_read32(DMA7_NEXT_DESC_PTR)
    585. 

  585. #define bfin_write_DMA7_NEXT_DESC_PTR(val) 	bfin_write32(DMA7_NEXT_DESC_PTR, val)
    586. 

  586. #define bfin_read_DMA7_START_ADDR() 		bfin_read32(DMA7_START_ADDR)
    587. 

  587. #define bfin_write_DMA7_START_ADDR(val) 	bfin_write32(DMA7_START_ADDR, val)
    588. 

  588. #define bfin_read_DMA7_CONFIG()			bfin_read32(DMA7_CONFIG)
    589. 

  589. #define bfin_write_DMA7_CONFIG(val)		bfin_write32(DMA7_CONFIG, val)
    590. 

  590. #define bfin_read_DMA7_X_COUNT()		bfin_read32(DMA7_X_COUNT)
    591. 

  591. #define bfin_write_DMA7_X_COUNT(val)		bfin_write32(DMA7_X_COUNT, val)
    592. 

  592. #define bfin_read_DMA7_X_MODIFY()		bfin_read32(DMA7_X_MODIFY)
    593. 

  593. #define bfin_write_DMA7_X_MODIFY(val) 		bfin_write32(DMA7_X_MODIFY, val)
    594. 

  594. #define bfin_read_DMA7_Y_COUNT()		bfin_read32(DMA7_Y_COUNT)
    595. 

  595. #define bfin_write_DMA7_Y_COUNT(val)		bfin_write32(DMA7_Y_COUNT, val)
    596. 

  596. #define bfin_read_DMA7_Y_MODIFY()		bfin_read32(DMA7_Y_MODIFY)
    597. 

  597. #define bfin_write_DMA7_Y_MODIFY(val) 		bfin_write32(DMA7_Y_MODIFY, val)
    598. 

  598. #define bfin_read_DMA7_CURR_DESC_PTR() 		bfin_read32(DMA7_CURR_DESC_PTR)
    599. 

  599. #define bfin_write_DMA7_CURR_DESC_PTR(val) 	bfin_write32(DMA7_CURR_DESC_PTR, val)
    600. 

  600. #define bfin_read_DMA7_PREV_DESC_PTR() 		bfin_read32(DMA7_PREV_DESC_PTR)
    601. 

  601. #define bfin_write_DMA7_PREV_DESC_PTR(val) 	bfin_write32(DMA7_PREV_DESC_PTR, val)
    602. 

  602. #define bfin_read_DMA7_CURR_ADDR() 		bfin_read32(DMA7_CURR_ADDR)
    603. 

  603. #define bfin_write_DMA7_CURR_ADDR(val) 		bfin_write32(DMA7_CURR_ADDR, val)
    604. 

  604. #define bfin_read_DMA7_IRQ_STATUS()		bfin_read32(DMA7_IRQ_STATUS)
    605. 

  605. #define bfin_write_DMA7_IRQ_STATUS(val)		bfin_write32(DMA7_IRQ_STATUS, val)
    606. 

  606. #define bfin_read_DMA7_CURR_X_COUNT()		bfin_read32(DMA7_CURR_X_COUNT)
    607. 

  607. #define bfin_write_DMA7_CURR_X_COUNT(val)	bfin_write32(DMA7_CURR_X_COUNT, val)
    608. 

  608. #define bfin_read_DMA7_CURR_Y_COUNT()		bfin_read32(DMA7_CURR_Y_COUNT)
    609. 

  609. #define bfin_write_DMA7_CURR_Y_COUNT(val)	bfin_write32(DMA7_CURR_Y_COUNT, val)
    610. 

  610. #define bfin_read_DMA7_BWL_COUNT()		bfin_read32(DMA7_BWL_COUNT)
    611. 

  611. #define bfin_write_DMA7_BWL_COUNT(val)		bfin_write32(DMA7_BWL_COUNT, val)
    612. 

  612. #define bfin_read_DMA7_CURR_BWL_COUNT()		bfin_read32(DMA7_CURR_BWL_COUNT)
    613. 

  613. #define bfin_write_DMA7_CURR_BWL_COUNT(val)	bfin_write32(DMA7_CURR_BWL_COUNT, val)
    614. 

  614. #define bfin_read_DMA7_BWM_COUNT()		bfin_read32(DMA7_BWM_COUNT)
    615. 

  615. #define bfin_write_DMA7_BWM_COUNT(val)		bfin_write32(DMA7_BWM_COUNT, val)
    616. 

  616. #define bfin_read_DMA7_CURR_BWM_COUNT()		bfin_read32(DMA7_CURR_BWM_COUNT)
    617. 

  617. #define bfin_write_DMA7_CURR_BWM_COUNT(val)	bfin_write32(DMA7_CURR_BWM_COUNT, val)
    618. 

  618. 

  619. /* DMA Channel 8 Registers */
    620. 

  620. 

  621. #define bfin_read_DMA8_NEXT_DESC_PTR() 		bfin_read32(DMA8_NEXT_DESC_PTR)
    622. 

  622. #define bfin_write_DMA8_NEXT_DESC_PTR(val) 	bfin_write32(DMA8_NEXT_DESC_PTR, val)
    623. 

  623. #define bfin_read_DMA8_START_ADDR() 		bfin_read32(DMA8_START_ADDR)
    624. 

  624. #define bfin_write_DMA8_START_ADDR(val) 	bfin_write32(DMA8_START_ADDR, val)
    625. 

  625. #define bfin_read_DMA8_CONFIG()			bfin_read32(DMA8_CONFIG)
    626. 

  626. #define bfin_write_DMA8_CONFIG(val)		bfin_write32(DMA8_CONFIG, val)
    627. 

  627. #define bfin_read_DMA8_X_COUNT()		bfin_read32(DMA8_X_COUNT)
    628. 

  628. #define bfin_write_DMA8_X_COUNT(val)		bfin_write32(DMA8_X_COUNT, val)
    629. 

  629. #define bfin_read_DMA8_X_MODIFY()		bfin_read32(DMA8_X_MODIFY)
    630. 

  630. #define bfin_write_DMA8_X_MODIFY(val) 		bfin_write32(DMA8_X_MODIFY, val)
    631. 

  631. #define bfin_read_DMA8_Y_COUNT()		bfin_read32(DMA8_Y_COUNT)
    632. 

  632. #define bfin_write_DMA8_Y_COUNT(val)		bfin_write32(DMA8_Y_COUNT, val)
    633. 

  633. #define bfin_read_DMA8_Y_MODIFY()		bfin_read32(DMA8_Y_MODIFY)
    634. 

  634. #define bfin_write_DMA8_Y_MODIFY(val) 		bfin_write32(DMA8_Y_MODIFY, val)
    635. 

  635. #define bfin_read_DMA8_CURR_DESC_PTR() 		bfin_read32(DMA8_CURR_DESC_PTR)
    636. 

  636. #define bfin_write_DMA8_CURR_DESC_PTR(val) 	bfin_write32(DMA8_CURR_DESC_PTR, val)
    637. 

  637. #define bfin_read_DMA8_PREV_DESC_PTR() 		bfin_read32(DMA8_PREV_DESC_PTR)
    638. 

  638. #define bfin_write_DMA8_PREV_DESC_PTR(val) 	bfin_write32(DMA8_PREV_DESC_PTR, val)
    639. 

  639. #define bfin_read_DMA8_CURR_ADDR() 		bfin_read32(DMA8_CURR_ADDR)
    640. 

  640. #define bfin_write_DMA8_CURR_ADDR(val) 		bfin_write32(DMA8_CURR_ADDR, val)
    641. 

  641. #define bfin_read_DMA8_IRQ_STATUS()		bfin_read32(DMA8_IRQ_STATUS)
    642. 

  642. #define bfin_write_DMA8_IRQ_STATUS(val)		bfin_write32(DMA8_IRQ_STATUS, val)
    643. 

  643. #define bfin_read_DMA8_CURR_X_COUNT()		bfin_read32(DMA8_CURR_X_COUNT)
    644. 

  644. #define bfin_write_DMA8_CURR_X_COUNT(val)	bfin_write32(DMA8_CURR_X_COUNT, val)
    645. 

  645. #define bfin_read_DMA8_CURR_Y_COUNT()		bfin_read32(DMA8_CURR_Y_COUNT)
    646. 

  646. #define bfin_write_DMA8_CURR_Y_COUNT(val)	bfin_write32(DMA8_CURR_Y_COUNT, val)
    647. 

  647. #define bfin_read_DMA8_BWL_COUNT()		bfin_read32(DMA8_BWL_COUNT)
    648. 

  648. #define bfin_write_DMA8_BWL_COUNT(val)		bfin_write32(DMA8_BWL_COUNT, val)
    649. 

  649. #define bfin_read_DMA8_CURR_BWL_COUNT()		bfin_read32(DMA8_CURR_BWL_COUNT)
    650. 

  650. #define bfin_write_DMA8_CURR_BWL_COUNT(val)	bfin_write32(DMA8_CURR_BWL_COUNT, val)
    651. 

  651. #define bfin_read_DMA8_BWM_COUNT()		bfin_read32(DMA8_BWM_COUNT)
    652. 

  652. #define bfin_write_DMA8_BWM_COUNT(val)		bfin_write32(DMA8_BWM_COUNT, val)
    653. 

  653. #define bfin_read_DMA8_CURR_BWM_COUNT()		bfin_read32(DMA8_CURR_BWM_COUNT)
    654. 

  654. #define bfin_write_DMA8_CURR_BWM_COUNT(val)	bfin_write32(DMA8_CURR_BWM_COUNT, val)
    655. 

  655. 

  656. /* DMA Channel 9 Registers */
    657. 

  657. 

  658. #define bfin_read_DMA9_NEXT_DESC_PTR() 		bfin_read32(DMA9_NEXT_DESC_PTR)
    659. 

  659. #define bfin_write_DMA9_NEXT_DESC_PTR(val) 	bfin_write32(DMA9_NEXT_DESC_PTR, val)
    660. 

  660. #define bfin_read_DMA9_START_ADDR() 		bfin_read32(DMA9_START_ADDR)
    661. 

  661. #define bfin_write_DMA9_START_ADDR(val) 	bfin_write32(DMA9_START_ADDR, val)
    662. 

  662. #define bfin_read_DMA9_CONFIG()			bfin_read32(DMA9_CONFIG)
    663. 

  663. #define bfin_write_DMA9_CONFIG(val)		bfin_write32(DMA9_CONFIG, val)
    664. 

  664. #define bfin_read_DMA9_X_COUNT()		bfin_read32(DMA9_X_COUNT)
    665. 

  665. #define bfin_write_DMA9_X_COUNT(val)		bfin_write32(DMA9_X_COUNT, val)
    666. 

  666. #define bfin_read_DMA9_X_MODIFY()		bfin_read32(DMA9_X_MODIFY)
    667. 

  667. #define bfin_write_DMA9_X_MODIFY(val) 		bfin_write32(DMA9_X_MODIFY, val)
    668. 

  668. #define bfin_read_DMA9_Y_COUNT()		bfin_read32(DMA9_Y_COUNT)
    669. 

  669. #define bfin_write_DMA9_Y_COUNT(val)		bfin_write32(DMA9_Y_COUNT, val)
    670. 

  670. #define bfin_read_DMA9_Y_MODIFY()		bfin_read32(DMA9_Y_MODIFY)
    671. 

  671. #define bfin_write_DMA9_Y_MODIFY(val) 		bfin_write32(DMA9_Y_MODIFY, val)
    672. 

  672. #define bfin_read_DMA9_CURR_DESC_PTR() 		bfin_read32(DMA9_CURR_DESC_PTR)
    673. 

  673. #define bfin_write_DMA9_CURR_DESC_PTR(val) 	bfin_write32(DMA9_CURR_DESC_PTR, val)
    674. 

  674. #define bfin_read_DMA9_PREV_DESC_PTR() 		bfin_read32(DMA9_PREV_DESC_PTR)
    675. 

  675. #define bfin_write_DMA9_PREV_DESC_PTR(val) 	bfin_write32(DMA9_PREV_DESC_PTR, val)
    676. 

  676. #define bfin_read_DMA9_CURR_ADDR() 		bfin_read32(DMA9_CURR_ADDR)
    677. 

  677. #define bfin_write_DMA9_CURR_ADDR(val) 		bfin_write32(DMA9_CURR_ADDR, val)
    678. 

  678. #define bfin_read_DMA9_IRQ_STATUS()		bfin_read32(DMA9_IRQ_STATUS)
    679. 

  679. #define bfin_write_DMA9_IRQ_STATUS(val)		bfin_write32(DMA9_IRQ_STATUS, val)
    680. 

  680. #define bfin_read_DMA9_CURR_X_COUNT()		bfin_read32(DMA9_CURR_X_COUNT)
    681. 

  681. #define bfin_write_DMA9_CURR_X_COUNT(val)	bfin_write32(DMA9_CURR_X_COUNT, val)
    682. 

  682. #define bfin_read_DMA9_CURR_Y_COUNT()		bfin_read32(DMA9_CURR_Y_COUNT)
    683. 

  683. #define bfin_write_DMA9_CURR_Y_COUNT(val)	bfin_write32(DMA9_CURR_Y_COUNT, val)
    684. 

  684. #define bfin_read_DMA9_BWL_COUNT()		bfin_read32(DMA9_BWL_COUNT)
    685. 

  685. #define bfin_write_DMA9_BWL_COUNT(val)		bfin_write32(DMA9_BWL_COUNT, val)
    686. 

  686. #define bfin_read_DMA9_CURR_BWL_COUNT()		bfin_read32(DMA9_CURR_BWL_COUNT)
    687. 

  687. #define bfin_write_DMA9_CURR_BWL_COUNT(val)	bfin_write32(DMA9_CURR_BWL_COUNT, val)
    688. 

  688. #define bfin_read_DMA9_BWM_COUNT()		bfin_read32(DMA9_BWM_COUNT)
    689. 

  689. #define bfin_write_DMA9_BWM_COUNT(val)		bfin_write32(DMA9_BWM_COUNT, val)
    690. 

  690. #define bfin_read_DMA9_CURR_BWM_COUNT()		bfin_read32(DMA9_CURR_BWM_COUNT)
    691. 

  691. #define bfin_write_DMA9_CURR_BWM_COUNT(val)	bfin_write32(DMA9_CURR_BWM_COUNT, val)
    692. 

  692. 

  693. /* DMA Channel 10 Registers */
    694. 

  694. 

  695. #define bfin_read_DMA10_NEXT_DESC_PTR() 	bfin_read32(DMA10_NEXT_DESC_PTR)
    696. 

  696. #define bfin_write_DMA10_NEXT_DESC_PTR(val) 	bfin_write32(DMA10_NEXT_DESC_PTR, val)
    697. 

  697. #define bfin_read_DMA10_START_ADDR() 		bfin_read32(DMA10_START_ADDR)
    698. 

  698. #define bfin_write_DMA10_START_ADDR(val) 	bfin_write32(DMA10_START_ADDR, val)
    699. 

  699. #define bfin_read_DMA10_CONFIG()		bfin_read32(DMA10_CONFIG)
    700. 

  700. #define bfin_write_DMA10_CONFIG(val)		bfin_write32(DMA10_CONFIG, val)
    701. 

  701. #define bfin_read_DMA10_X_COUNT()		bfin_read32(DMA10_X_COUNT)
    702. 

  702. #define bfin_write_DMA10_X_COUNT(val)		bfin_write32(DMA10_X_COUNT, val)
    703. 

  703. #define bfin_read_DMA10_X_MODIFY()		bfin_read32(DMA10_X_MODIFY)
    704. 

  704. #define bfin_write_DMA10_X_MODIFY(val) 		bfin_write32(DMA10_X_MODIFY, val)
    705. 

  705. #define bfin_read_DMA10_Y_COUNT()		bfin_read32(DMA10_Y_COUNT)
    706. 

  706. #define bfin_write_DMA10_Y_COUNT(val)		bfin_write32(DMA10_Y_COUNT, val)
    707. 

  707. #define bfin_read_DMA10_Y_MODIFY()		bfin_read32(DMA10_Y_MODIFY)
    708. 

  708. #define bfin_write_DMA10_Y_MODIFY(val) 		bfin_write32(DMA10_Y_MODIFY, val)
    709. 

  709. #define bfin_read_DMA10_CURR_DESC_PTR() 	bfin_read32(DMA10_CURR_DESC_PTR)
    710. 

  710. #define bfin_write_DMA10_CURR_DESC_PTR(val) 	bfin_write32(DMA10_CURR_DESC_PTR, val)
    711. 

  711. #define bfin_read_DMA10_PREV_DESC_PTR() 	bfin_read32(DMA10_PREV_DESC_PTR)
    712. 

  712. #define bfin_write_DMA10_PREV_DESC_PTR(val) 	bfin_write32(DMA10_PREV_DESC_PTR, val)
    713. 

  713. #define bfin_read_DMA10_CURR_ADDR() 		bfin_read32(DMA10_CURR_ADDR)
    714. 

  714. #define bfin_write_DMA10_CURR_ADDR(val) 	bfin_write32(DMA10_CURR_ADDR, val)
    715. 

  715. #define bfin_read_DMA10_IRQ_STATUS()		bfin_read32(DMA10_IRQ_STATUS)
    716. 

  716. #define bfin_write_DMA10_IRQ_STATUS(val)	bfin_write32(DMA10_IRQ_STATUS, val)
    717. 

  717. #define bfin_read_DMA10_CURR_X_COUNT()		bfin_read32(DMA10_CURR_X_COUNT)
    718. 

  718. #define bfin_write_DMA10_CURR_X_COUNT(val)	bfin_write32(DMA10_CURR_X_COUNT, val)
    719. 

  719. #define bfin_read_DMA10_CURR_Y_COUNT()		bfin_read32(DMA10_CURR_Y_COUNT)
    720. 

  720. #define bfin_write_DMA10_CURR_Y_COUNT(val)	bfin_write32(DMA10_CURR_Y_COUNT, val)
    721. 

  721. #define bfin_read_DMA10_BWL_COUNT()		bfin_read32(DMA10_BWL_COUNT)
    722. 

  722. #define bfin_write_DMA10_BWL_COUNT(val)		bfin_write32(DMA10_BWL_COUNT, val)
    723. 

  723. #define bfin_read_DMA10_CURR_BWL_COUNT()	bfin_read32(DMA10_CURR_BWL_COUNT)
    724. 

  724. #define bfin_write_DMA10_CURR_BWL_COUNT(val)	bfin_write32(DMA10_CURR_BWL_COUNT, val)
    725. 

  725. #define bfin_read_DMA10_BWM_COUNT()		bfin_read32(DMA10_BWM_COUNT)
    726. 

  726. #define bfin_write_DMA10_BWM_COUNT(val)		bfin_write32(DMA10_BWM_COUNT, val)
    727. 

  727. #define bfin_read_DMA10_CURR_BWM_COUNT()	bfin_read32(DMA10_CURR_BWM_COUNT)
    728. 

  728. #define bfin_write_DMA10_CURR_BWM_COUNT(val)	bfin_write32(DMA10_CURR_BWM_COUNT, val)
    729. 

  729. 

  730. /* DMA Channel 11 Registers */
    731. 

  731. 

  732. #define bfin_read_DMA11_NEXT_DESC_PTR() 	bfin_read32(DMA11_NEXT_DESC_PTR)
    733. 

  733. #define bfin_write_DMA11_NEXT_DESC_PTR(val) 	bfin_write32(DMA11_NEXT_DESC_PTR, val)
    734. 

  734. #define bfin_read_DMA11_START_ADDR() 		bfin_read32(DMA11_START_ADDR)
    735. 

  735. #define bfin_write_DMA11_START_ADDR(val) 	bfin_write32(DMA11_START_ADDR, val)
    736. 

  736. #define bfin_read_DMA11_CONFIG()		bfin_read32(DMA11_CONFIG)
    737. 

  737. #define bfin_write_DMA11_CONFIG(val)		bfin_write32(DMA11_CONFIG, val)
    738. 

  738. #define bfin_read_DMA11_X_COUNT()		bfin_read32(DMA11_X_COUNT)
    739. 

  739. #define bfin_write_DMA11_X_COUNT(val)		bfin_write32(DMA11_X_COUNT, val)
    740. 

  740. #define bfin_read_DMA11_X_MODIFY()		bfin_read32(DMA11_X_MODIFY)
    741. 

  741. #define bfin_write_DMA11_X_MODIFY(val) 		bfin_write32(DMA11_X_MODIFY, val)
    742. 

  742. #define bfin_read_DMA11_Y_COUNT()		bfin_read32(DMA11_Y_COUNT)
    743. 

  743. #define bfin_write_DMA11_Y_COUNT(val)		bfin_write32(DMA11_Y_COUNT, val)
    744. 

  744. #define bfin_read_DMA11_Y_MODIFY()		bfin_read32(DMA11_Y_MODIFY)
    745. 

  745. #define bfin_write_DMA11_Y_MODIFY(val) 		bfin_write32(DMA11_Y_MODIFY, val)
    746. 

  746. #define bfin_read_DMA11_CURR_DESC_PTR() 	bfin_read32(DMA11_CURR_DESC_PTR)
    747. 

  747. #define bfin_write_DMA11_CURR_DESC_PTR(val) 	bfin_write32(DMA11_CURR_DESC_PTR, val)
    748. 

  748. #define bfin_read_DMA11_PREV_DESC_PTR() 	bfin_read32(DMA11_PREV_DESC_PTR)
    749. 

  749. #define bfin_write_DMA11_PREV_DESC_PTR(val) 	bfin_write32(DMA11_PREV_DESC_PTR, val)
    750. 

  750. #define bfin_read_DMA11_CURR_ADDR() 		bfin_read32(DMA11_CURR_ADDR)
    751. 

  751. #define bfin_write_DMA11_CURR_ADDR(val) 	bfin_write32(DMA11_CURR_ADDR, val)
    752. 

  752. #define bfin_read_DMA11_IRQ_STATUS()		bfin_read32(DMA11_IRQ_STATUS)
    753. 

  753. #define bfin_write_DMA11_IRQ_STATUS(val)	bfin_write32(DMA11_IRQ_STATUS, val)
    754. 

  754. #define bfin_read_DMA11_CURR_X_COUNT()		bfin_read32(DMA11_CURR_X_COUNT)
    755. 

  755. #define bfin_write_DMA11_CURR_X_COUNT(val)	bfin_write32(DMA11_CURR_X_COUNT, val)
    756. 

  756. #define bfin_read_DMA11_CURR_Y_COUNT()		bfin_read32(DMA11_CURR_Y_COUNT)
    757. 

  757. #define bfin_write_DMA11_CURR_Y_COUNT(val)	bfin_write32(DMA11_CURR_Y_COUNT, val)
    758. 

  758. #define bfin_read_DMA11_BWL_COUNT()		bfin_read32(DMA11_BWL_COUNT)
    759. 

  759. #define bfin_write_DMA11_BWL_COUNT(val)		bfin_write32(DMA11_BWL_COUNT, val)
    760. 

  760. #define bfin_read_DMA11_CURR_BWL_COUNT()	bfin_read32(DMA11_CURR_BWL_COUNT)
    761. 

  761. #define bfin_write_DMA11_CURR_BWL_COUNT(val)	bfin_write32(DMA11_CURR_BWL_COUNT, val)
    762. 

  762. #define bfin_read_DMA11_BWM_COUNT()		bfin_read32(DMA11_BWM_COUNT)
    763. 

  763. #define bfin_write_DMA11_BWM_COUNT(val)		bfin_write32(DMA11_BWM_COUNT, val)
    764. 

  764. #define bfin_read_DMA11_CURR_BWM_COUNT()	bfin_read32(DMA11_CURR_BWM_COUNT)
    765. 

  765. #define bfin_write_DMA11_CURR_BWM_COUNT(val)	bfin_write32(DMA11_CURR_BWM_COUNT, val)
    766. 

  766. 

  767. /* DMA Channel 12 Registers */
    768. 

  768. 

  769. #define bfin_read_DMA12_NEXT_DESC_PTR() 	bfin_read32(DMA12_NEXT_DESC_PTR)
    770. 

  770. #define bfin_write_DMA12_NEXT_DESC_PTR(val) 	bfin_write32(DMA12_NEXT_DESC_PTR, val)
    771. 

  771. #define bfin_read_DMA12_START_ADDR() 		bfin_read32(DMA12_START_ADDR)
    772. 

  772. #define bfin_write_DMA12_START_ADDR(val) 	bfin_write32(DMA12_START_ADDR, val)
    773. 

  773. #define bfin_read_DMA12_CONFIG()		bfin_read32(DMA12_CONFIG)
    774. 

  774. #define bfin_write_DMA12_CONFIG(val)		bfin_write32(DMA12_CONFIG, val)
    775. 

  775. #define bfin_read_DMA12_X_COUNT()		bfin_read32(DMA12_X_COUNT)
    776. 

  776. #define bfin_write_DMA12_X_COUNT(val)		bfin_write32(DMA12_X_COUNT, val)
    777. 

  777. #define bfin_read_DMA12_X_MODIFY()		bfin_read32(DMA12_X_MODIFY)
    778. 

  778. #define bfin_write_DMA12_X_MODIFY(val) 		bfin_write32(DMA12_X_MODIFY, val)
    779. 

  779. #define bfin_read_DMA12_Y_COUNT()		bfin_read32(DMA12_Y_COUNT)
    780. 

  780. #define bfin_write_DMA12_Y_COUNT(val)		bfin_write32(DMA12_Y_COUNT, val)
    781. 

  781. #define bfin_read_DMA12_Y_MODIFY()		bfin_read32(DMA12_Y_MODIFY)
    782. 

  782. #define bfin_write_DMA12_Y_MODIFY(val) 		bfin_write32(DMA12_Y_MODIFY, val)
    783. 

  783. #define bfin_read_DMA12_CURR_DESC_PTR() 	bfin_read32(DMA12_CURR_DESC_PTR)
    784. 

  784. #define bfin_write_DMA12_CURR_DESC_PTR(val) 	bfin_write32(DMA12_CURR_DESC_PTR, val)
    785. 

  785. #define bfin_read_DMA12_PREV_DESC_PTR() 	bfin_read32(DMA12_PREV_DESC_PTR)
    786. 

  786. #define bfin_write_DMA12_PREV_DESC_PTR(val) 	bfin_write32(DMA12_PREV_DESC_PTR, val)
    787. 

  787. #define bfin_read_DMA12_CURR_ADDR() 		bfin_read32(DMA12_CURR_ADDR)
    788. 

  788. #define bfin_write_DMA12_CURR_ADDR(val) 	bfin_write32(DMA12_CURR_ADDR, val)
    789. 

  789. #define bfin_read_DMA12_IRQ_STATUS()		bfin_read32(DMA12_IRQ_STATUS)
    790. 

  790. #define bfin_write_DMA12_IRQ_STATUS(val)	bfin_write32(DMA12_IRQ_STATUS, val)
    791. 

  791. #define bfin_read_DMA12_CURR_X_COUNT()		bfin_read32(DMA12_CURR_X_COUNT)
    792. 

  792. #define bfin_write_DMA12_CURR_X_COUNT(val)	bfin_write32(DMA12_CURR_X_COUNT, val)
    793. 

  793. #define bfin_read_DMA12_CURR_Y_COUNT()		bfin_read32(DMA12_CURR_Y_COUNT)
    794. 

  794. #define bfin_write_DMA12_CURR_Y_COUNT(val)	bfin_write32(DMA12_CURR_Y_COUNT, val)
    795. 

  795. #define bfin_read_DMA12_BWL_COUNT()		bfin_read32(DMA12_BWL_COUNT)
    796. 

  796. #define bfin_write_DMA12_BWL_COUNT(val)		bfin_write32(DMA12_BWL_COUNT, val)
    797. 

  797. #define bfin_read_DMA12_CURR_BWL_COUNT()	bfin_read32(DMA12_CURR_BWL_COUNT)
    798. 

  798. #define bfin_write_DMA12_CURR_BWL_COUNT(val)	bfin_write32(DMA12_CURR_BWL_COUNT, val)
    799. 

  799. #define bfin_read_DMA12_BWM_COUNT()		bfin_read32(DMA12_BWM_COUNT)
    800. 

  800. #define bfin_write_DMA12_BWM_COUNT(val)		bfin_write32(DMA12_BWM_COUNT, val)
    801. 

  801. #define bfin_read_DMA12_CURR_BWM_COUNT()	bfin_read32(DMA12_CURR_BWM_COUNT)
    802. 

  802. #define bfin_write_DMA12_CURR_BWM_COUNT(val)	bfin_write32(DMA12_CURR_BWM_COUNT, val)
    803. 

  803. 

  804. /* DMA Channel 13 Registers */
    805. 

  805. 

  806. #define bfin_read_DMA13_NEXT_DESC_PTR() 	bfin_read32(DMA13_NEXT_DESC_PTR)
    807. 

  807. #define bfin_write_DMA13_NEXT_DESC_PTR(val) 	bfin_write32(DMA13_NEXT_DESC_PTR, val)
    808. 

  808. #define bfin_read_DMA13_START_ADDR() 		bfin_read32(DMA13_START_ADDR)
    809. 

  809. #define bfin_write_DMA13_START_ADDR(val) 	bfin_write32(DMA13_START_ADDR, val)
    810. 

  810. #define bfin_read_DMA13_CONFIG()		bfin_read32(DMA13_CONFIG)
    811. 

  811. #define bfin_write_DMA13_CONFIG(val)		bfin_write32(DMA13_CONFIG, val)
    812. 

  812. #define bfin_read_DMA13_X_COUNT()		bfin_read32(DMA13_X_COUNT)
    813. 

  813. #define bfin_write_DMA13_X_COUNT(val)		bfin_write32(DMA13_X_COUNT, val)
    814. 

  814. #define bfin_read_DMA13_X_MODIFY()		bfin_read32(DMA13_X_MODIFY)
    815. 

  815. #define bfin_write_DMA13_X_MODIFY(val) 		bfin_write32(DMA13_X_MODIFY, val)
    816. 

  816. #define bfin_read_DMA13_Y_COUNT()		bfin_read32(DMA13_Y_COUNT)
    817. 

  817. #define bfin_write_DMA13_Y_COUNT(val)		bfin_write32(DMA13_Y_COUNT, val)
    818. 

  818. #define bfin_read_DMA13_Y_MODIFY()		bfin_read32(DMA13_Y_MODIFY)
    819. 

  819. #define bfin_write_DMA13_Y_MODIFY(val) 		bfin_write32(DMA13_Y_MODIFY, val)
    820. 

  820. #define bfin_read_DMA13_CURR_DESC_PTR() 	bfin_read32(DMA13_CURR_DESC_PTR)
    821. 

  821. #define bfin_write_DMA13_CURR_DESC_PTR(val) 	bfin_write32(DMA13_CURR_DESC_PTR, val)
    822. 

  822. #define bfin_read_DMA13_PREV_DESC_PTR() 	bfin_read32(DMA13_PREV_DESC_PTR)
    823. 

  823. #define bfin_write_DMA13_PREV_DESC_PTR(val) 	bfin_write32(DMA13_PREV_DESC_PTR, val)
    824. 

  824. #define bfin_read_DMA13_CURR_ADDR() 		bfin_read32(DMA13_CURR_ADDR)
    825. 

  825. #define bfin_write_DMA13_CURR_ADDR(val) 	bfin_write32(DMA13_CURR_ADDR, val)
    826. 

  826. #define bfin_read_DMA13_IRQ_STATUS()		bfin_read32(DMA13_IRQ_STATUS)
    827. 

  827. #define bfin_write_DMA13_IRQ_STATUS(val)	bfin_write32(DMA13_IRQ_STATUS, val)
    828. 

  828. #define bfin_read_DMA13_CURR_X_COUNT()		bfin_read32(DMA13_CURR_X_COUNT)
    829. 

  829. #define bfin_write_DMA13_CURR_X_COUNT(val)	bfin_write32(DMA13_CURR_X_COUNT, val)
    830. 

  830. #define bfin_read_DMA13_CURR_Y_COUNT()		bfin_read32(DMA13_CURR_Y_COUNT)
    831. 

  831. #define bfin_write_DMA13_CURR_Y_COUNT(val)	bfin_write32(DMA13_CURR_Y_COUNT, val)
    832. 

  832. #define bfin_read_DMA13_BWL_COUNT()		bfin_read32(DMA13_BWL_COUNT)
    833. 

  833. #define bfin_write_DMA13_BWL_COUNT(val)		bfin_write32(DMA13_BWL_COUNT, val)
    834. 

  834. #define bfin_read_DMA13_CURR_BWL_COUNT()	bfin_read32(DMA13_CURR_BWL_COUNT)
    835. 

  835. #define bfin_write_DMA13_CURR_BWL_COUNT(val)	bfin_write32(DMA13_CURR_BWL_COUNT, val)
    836. 

  836. #define bfin_read_DMA13_BWM_COUNT()		bfin_read32(DMA13_BWM_COUNT)
    837. 

  837. #define bfin_write_DMA13_BWM_COUNT(val)		bfin_write32(DMA13_BWM_COUNT, val)
    838. 

  838. #define bfin_read_DMA13_CURR_BWM_COUNT()	bfin_read32(DMA13_CURR_BWM_COUNT)
    839. 

  839. #define bfin_write_DMA13_CURR_BWM_COUNT(val)	bfin_write32(DMA13_CURR_BWM_COUNT, val)
    840. 

  840. 

  841. /* DMA Channel 14 Registers */
    842. 

  842. 

  843. #define bfin_read_DMA14_NEXT_DESC_PTR() 	bfin_read32(DMA14_NEXT_DESC_PTR)
    844. 

  844. #define bfin_write_DMA14_NEXT_DESC_PTR(val) 	bfin_write32(DMA14_NEXT_DESC_PTR, val)
    845. 

  845. #define bfin_read_DMA14_START_ADDR() 		bfin_read32(DMA14_START_ADDR)
    846. 

  846. #define bfin_write_DMA14_START_ADDR(val) 	bfin_write32(DMA14_START_ADDR, val)
    847. 

  847. #define bfin_read_DMA14_CONFIG()		bfin_read32(DMA14_CONFIG)
    848. 

  848. #define bfin_write_DMA14_CONFIG(val)		bfin_write32(DMA14_CONFIG, val)
    849. 

  849. #define bfin_read_DMA14_X_COUNT()		bfin_read32(DMA14_X_COUNT)
    850. 

  850. #define bfin_write_DMA14_X_COUNT(val)		bfin_write32(DMA14_X_COUNT, val)
    851. 

  851. #define bfin_read_DMA14_X_MODIFY()		bfin_read32(DMA14_X_MODIFY)
    852. 

  852. #define bfin_write_DMA14_X_MODIFY(val) 		bfin_write32(DMA14_X_MODIFY, val)
    853. 

  853. #define bfin_read_DMA14_Y_COUNT()		bfin_read32(DMA14_Y_COUNT)
    854. 

  854. #define bfin_write_DMA14_Y_COUNT(val)		bfin_write32(DMA14_Y_COUNT, val)
    855. 

  855. #define bfin_read_DMA14_Y_MODIFY()		bfin_read32(DMA14_Y_MODIFY)
    856. 

  856. #define bfin_write_DMA14_Y_MODIFY(val) 		bfin_write32(DMA14_Y_MODIFY, val)
    857. 

  857. #define bfin_read_DMA14_CURR_DESC_PTR() 	bfin_read32(DMA14_CURR_DESC_PTR)
    858. 

  858. #define bfin_write_DMA14_CURR_DESC_PTR(val) 	bfin_write32(DMA14_CURR_DESC_PTR, val)
    859. 

  859. #define bfin_read_DMA14_PREV_DESC_PTR() 	bfin_read32(DMA14_PREV_DESC_PTR)
    860. 

  860. #define bfin_write_DMA14_PREV_DESC_PTR(val) 	bfin_write32(DMA14_PREV_DESC_PTR, val)
    861. 

  861. #define bfin_read_DMA14_CURR_ADDR() 		bfin_read32(DMA14_CURR_ADDR)
    862. 

  862. #define bfin_write_DMA14_CURR_ADDR(val) 	bfin_write32(DMA14_CURR_ADDR, val)
    863. 

  863. #define bfin_read_DMA14_IRQ_STATUS()		bfin_read32(DMA14_IRQ_STATUS)
    864. 

  864. #define bfin_write_DMA14_IRQ_STATUS(val)	bfin_write32(DMA14_IRQ_STATUS, val)
    865. 

  865. #define bfin_read_DMA14_CURR_X_COUNT()		bfin_read32(DMA14_CURR_X_COUNT)
    866. 

  866. #define bfin_write_DMA14_CURR_X_COUNT(val)	bfin_write32(DMA14_CURR_X_COUNT, val)
    867. 

  867. #define bfin_read_DMA14_CURR_Y_COUNT()		bfin_read32(DMA14_CURR_Y_COUNT)
    868. 

  868. #define bfin_write_DMA14_CURR_Y_COUNT(val)	bfin_write32(DMA14_CURR_Y_COUNT, val)
    869. 

  869. #define bfin_read_DMA14_BWL_COUNT()		bfin_read32(DMA14_BWL_COUNT)
    870. 

  870. #define bfin_write_DMA14_BWL_COUNT(val)		bfin_write32(DMA14_BWL_COUNT, val)
    871. 

  871. #define bfin_read_DMA14_CURR_BWL_COUNT()	bfin_read32(DMA14_CURR_BWL_COUNT)
    872. 

  872. #define bfin_write_DMA14_CURR_BWL_COUNT(val)	bfin_write32(DMA14_CURR_BWL_COUNT, val)
    873. 

  873. #define bfin_read_DMA14_BWM_COUNT()		bfin_read32(DMA14_BWM_COUNT)
    874. 

  874. #define bfin_write_DMA14_BWM_COUNT(val)		bfin_write32(DMA14_BWM_COUNT, val)
    875. 

  875. #define bfin_read_DMA14_CURR_BWM_COUNT()	bfin_read32(DMA14_CURR_BWM_COUNT)
    876. 

  876. #define bfin_write_DMA14_CURR_BWM_COUNT(val)	bfin_write32(DMA14_CURR_BWM_COUNT, val)
    877. 

  877. 

  878. /* DMA Channel 15 Registers */
    879. 

  879. 

  880. #define bfin_read_DMA15_NEXT_DESC_PTR() 	bfin_read32(DMA15_NEXT_DESC_PTR)
    881. 

  881. #define bfin_write_DMA15_NEXT_DESC_PTR(val) 	bfin_write32(DMA15_NEXT_DESC_PTR, val)
    882. 

  882. #define bfin_read_DMA15_START_ADDR() 		bfin_read32(DMA15_START_ADDR)
    883. 

  883. #define bfin_write_DMA15_START_ADDR(val) 	bfin_write32(DMA15_START_ADDR, val)
    884. 

  884. #define bfin_read_DMA15_CONFIG()		bfin_read32(DMA15_CONFIG)
    885. 

  885. #define bfin_write_DMA15_CONFIG(val)		bfin_write32(DMA15_CONFIG, val)
    886. 

  886. #define bfin_read_DMA15_X_COUNT()		bfin_read32(DMA15_X_COUNT)
    887. 

  887. #define bfin_write_DMA15_X_COUNT(val)		bfin_write32(DMA15_X_COUNT, val)
    888. 

  888. #define bfin_read_DMA15_X_MODIFY()		bfin_read32(DMA15_X_MODIFY)
    889. 

  889. #define bfin_write_DMA15_X_MODIFY(val) 		bfin_write32(DMA15_X_MODIFY, val)
    890. 

  890. #define bfin_read_DMA15_Y_COUNT()		bfin_read32(DMA15_Y_COUNT)
    891. 

  891. #define bfin_write_DMA15_Y_COUNT(val)		bfin_write32(DMA15_Y_COUNT, val)
    892. 

  892. #define bfin_read_DMA15_Y_MODIFY()		bfin_read32(DMA15_Y_MODIFY)
    893. 

  893. #define bfin_write_DMA15_Y_MODIFY(val) 		bfin_write32(DMA15_Y_MODIFY, val)
    894. 

  894. #define bfin_read_DMA15_CURR_DESC_PTR() 	bfin_read32(DMA15_CURR_DESC_PTR)
    895. 

  895. #define bfin_write_DMA15_CURR_DESC_PTR(val) 	bfin_write32(DMA15_CURR_DESC_PTR, val)
    896. 

  896. #define bfin_read_DMA15_PREV_DESC_PTR() 	bfin_read32(DMA15_PREV_DESC_PTR)
    897. 

  897. #define bfin_write_DMA15_PREV_DESC_PTR(val) 	bfin_write32(DMA15_PREV_DESC_PTR, val)
    898. 

  898. #define bfin_read_DMA15_CURR_ADDR() 		bfin_read32(DMA15_CURR_ADDR)
    899. 

  899. #define bfin_write_DMA15_CURR_ADDR(val) 	bfin_write32(DMA15_CURR_ADDR, val)
    900. 

  900. #define bfin_read_DMA15_IRQ_STATUS()		bfin_read32(DMA15_IRQ_STATUS)
    901. 

  901. #define bfin_write_DMA15_IRQ_STATUS(val)	bfin_write32(DMA15_IRQ_STATUS, val)
    902. 

  902. #define bfin_read_DMA15_CURR_X_COUNT()		bfin_read32(DMA15_CURR_X_COUNT)
    903. 

  903. #define bfin_write_DMA15_CURR_X_COUNT(val)	bfin_write32(DMA15_CURR_X_COUNT, val)
    904. 

  904. #define bfin_read_DMA15_CURR_Y_COUNT()		bfin_read32(DMA15_CURR_Y_COUNT)
    905. 

  905. #define bfin_write_DMA15_CURR_Y_COUNT(val)	bfin_write32(DMA15_CURR_Y_COUNT, val)
    906. 

  906. #define bfin_read_DMA15_BWL_COUNT()		bfin_read32(DMA15_BWL_COUNT)
    907. 

  907. #define bfin_write_DMA15_BWL_COUNT(val)		bfin_write32(DMA15_BWL_COUNT, val)
    908. 

  908. #define bfin_read_DMA15_CURR_BWL_COUNT()	bfin_read32(DMA15_CURR_BWL_COUNT)
    909. 

  909. #define bfin_write_DMA15_CURR_BWL_COUNT(val)	bfin_write32(DMA15_CURR_BWL_COUNT, val)
    910. 

  910. #define bfin_read_DMA15_BWM_COUNT()		bfin_read32(DMA15_BWM_COUNT)
    911. 

  911. #define bfin_write_DMA15_BWM_COUNT(val)		bfin_write32(DMA15_BWM_COUNT, val)
    912. 

  912. #define bfin_read_DMA15_CURR_BWM_COUNT()	bfin_read32(DMA15_CURR_BWM_COUNT)
    913. 

  913. #define bfin_write_DMA15_CURR_BWM_COUNT(val)	bfin_write32(DMA15_CURR_BWM_COUNT, val)
    914. 

  914. 

  915. /* DMA Channel 16 Registers */
    916. 

  916. 

  917. #define bfin_read_DMA16_NEXT_DESC_PTR() 	bfin_read32(DMA16_NEXT_DESC_PTR)
    918. 

  918. #define bfin_write_DMA16_NEXT_DESC_PTR(val) 	bfin_write32(DMA16_NEXT_DESC_PTR, val)
    919. 

  919. #define bfin_read_DMA16_START_ADDR() 		bfin_read32(DMA16_START_ADDR)
    920. 

  920. #define bfin_write_DMA16_START_ADDR(val) 	bfin_write32(DMA16_START_ADDR, val)
    921. 

  921. #define bfin_read_DMA16_CONFIG()		bfin_read32(DMA16_CONFIG)
    922. 

  922. #define bfin_write_DMA16_CONFIG(val)		bfin_write32(DMA16_CONFIG, val)
    923. 

  923. #define bfin_read_DMA16_X_COUNT()		bfin_read32(DMA16_X_COUNT)
    924. 

  924. #define bfin_write_DMA16_X_COUNT(val)		bfin_write32(DMA16_X_COUNT, val)
    925. 

  925. #define bfin_read_DMA16_X_MODIFY()		bfin_read32(DMA16_X_MODIFY)
    926. 

  926. #define bfin_write_DMA16_X_MODIFY(val) 		bfin_write32(DMA16_X_MODIFY, val)
    927. 

  927. #define bfin_read_DMA16_Y_COUNT()		bfin_read32(DMA16_Y_COUNT)
    928. 

  928. #define bfin_write_DMA16_Y_COUNT(val)		bfin_write32(DMA16_Y_COUNT, val)
    929. 

  929. #define bfin_read_DMA16_Y_MODIFY()		bfin_read32(DMA16_Y_MODIFY)
    930. 

  930. #define bfin_write_DMA16_Y_MODIFY(val) 		bfin_write32(DMA16_Y_MODIFY, val)
    931. 

  931. #define bfin_read_DMA16_CURR_DESC_PTR() 	bfin_read32(DMA16_CURR_DESC_PTR)
    932. 

  932. #define bfin_write_DMA16_CURR_DESC_PTR(val) 	bfin_write32(DMA16_CURR_DESC_PTR, val)
    933. 

  933. #define bfin_read_DMA16_PREV_DESC_PTR() 	bfin_read32(DMA16_PREV_DESC_PTR)
    934. 

  934. #define bfin_write_DMA16_PREV_DESC_PTR(val) 	bfin_write32(DMA16_PREV_DESC_PTR, val)
    935. 

  935. #define bfin_read_DMA16_CURR_ADDR() 		bfin_read32(DMA16_CURR_ADDR)
    936. 

  936. #define bfin_write_DMA16_CURR_ADDR(val) 	bfin_write32(DMA16_CURR_ADDR, val)
    937. 

  937. #define bfin_read_DMA16_IRQ_STATUS()		bfin_read32(DMA16_IRQ_STATUS)
    938. 

  938. #define bfin_write_DMA16_IRQ_STATUS(val)	bfin_write32(DMA16_IRQ_STATUS, val)
    939. 

  939. #define bfin_read_DMA16_CURR_X_COUNT()		bfin_read32(DMA16_CURR_X_COUNT)
    940. 

  940. #define bfin_write_DMA16_CURR_X_COUNT(val)	bfin_write32(DMA16_CURR_X_COUNT, val)
    941. 

  941. #define bfin_read_DMA16_CURR_Y_COUNT()		bfin_read32(DMA16_CURR_Y_COUNT)
    942. 

  942. #define bfin_write_DMA16_CURR_Y_COUNT(val)	bfin_write32(DMA16_CURR_Y_COUNT, val)
    943. 

  943. #define bfin_read_DMA16_BWL_COUNT()		bfin_read32(DMA16_BWL_COUNT)
    944. 

  944. #define bfin_write_DMA16_BWL_COUNT(val)		bfin_write32(DMA16_BWL_COUNT, val)
    945. 

  945. #define bfin_read_DMA16_CURR_BWL_COUNT()	bfin_read32(DMA16_CURR_BWL_COUNT)
    946. 

  946. #define bfin_write_DMA16_CURR_BWL_COUNT(val)	bfin_write32(DMA16_CURR_BWL_COUNT, val)
    947. 

  947. #define bfin_read_DMA16_BWM_COUNT()		bfin_read32(DMA16_BWM_COUNT)
    948. 

  948. #define bfin_write_DMA16_BWM_COUNT(val)		bfin_write32(DMA16_BWM_COUNT, val)
    949. 

  949. #define bfin_read_DMA16_CURR_BWM_COUNT()	bfin_read32(DMA16_CURR_BWM_COUNT)
    950. 

  950. #define bfin_write_DMA16_CURR_BWM_COUNT(val)	bfin_write32(DMA16_CURR_BWM_COUNT, val)
    951. 

  951. 

  952. /* DMA Channel 17 Registers */
    953. 

  953. 

  954. #define bfin_read_DMA17_NEXT_DESC_PTR() 	bfin_read32(DMA17_NEXT_DESC_PTR)
    955. 

  955. #define bfin_write_DMA17_NEXT_DESC_PTR(val) 	bfin_write32(DMA17_NEXT_DESC_PTR, val)
    956. 

  956. #define bfin_read_DMA17_START_ADDR() 		bfin_read32(DMA17_START_ADDR)
    957. 

  957. #define bfin_write_DMA17_START_ADDR(val) 	bfin_write32(DMA17_START_ADDR, val)
    958. 

  958. #define bfin_read_DMA17_CONFIG()		bfin_read32(DMA17_CONFIG)
    959. 

  959. #define bfin_write_DMA17_CONFIG(val)		bfin_write32(DMA17_CONFIG, val)
    960. 

  960. #define bfin_read_DMA17_X_COUNT()		bfin_read32(DMA17_X_COUNT)
    961. 

  961. #define bfin_write_DMA17_X_COUNT(val)		bfin_write32(DMA17_X_COUNT, val)
    962. 

  962. #define bfin_read_DMA17_X_MODIFY()		bfin_read32(DMA17_X_MODIFY)
    963. 

  963. #define bfin_write_DMA17_X_MODIFY(val) 		bfin_write32(DMA17_X_MODIFY, val)
    964. 

  964. #define bfin_read_DMA17_Y_COUNT()		bfin_read32(DMA17_Y_COUNT)
    965. 

  965. #define bfin_write_DMA17_Y_COUNT(val)		bfin_write32(DMA17_Y_COUNT, val)
    966. 

  966. #define bfin_read_DMA17_Y_MODIFY()		bfin_read32(DMA17_Y_MODIFY)
    967. 

  967. #define bfin_write_DMA17_Y_MODIFY(val) 		bfin_write32(DMA17_Y_MODIFY, val)
    968. 

  968. #define bfin_read_DMA17_CURR_DESC_PTR() 	bfin_read32(DMA17_CURR_DESC_PTR)
    969. 

  969. #define bfin_write_DMA17_CURR_DESC_PTR(val) 	bfin_write32(DMA17_CURR_DESC_PTR, val)
    970. 

  970. #define bfin_read_DMA17_PREV_DESC_PTR() 	bfin_read32(DMA17_PREV_DESC_PTR)
    971. 

  971. #define bfin_write_DMA17_PREV_DESC_PTR(val) 	bfin_write32(DMA17_PREV_DESC_PTR, val)
    972. 

  972. #define bfin_read_DMA17_CURR_ADDR() 		bfin_read32(DMA17_CURR_ADDR)
    973. 

  973. #define bfin_write_DMA17_CURR_ADDR(val) 	bfin_write32(DMA17_CURR_ADDR, val)
    974. 

  974. #define bfin_read_DMA17_IRQ_STATUS()		bfin_read32(DMA17_IRQ_STATUS)
    975. 

  975. #define bfin_write_DMA17_IRQ_STATUS(val)	bfin_write32(DMA17_IRQ_STATUS, val)
    976. 

  976. #define bfin_read_DMA17_CURR_X_COUNT()		bfin_read32(DMA17_CURR_X_COUNT)
    977. 

  977. #define bfin_write_DMA17_CURR_X_COUNT(val)	bfin_write32(DMA17_CURR_X_COUNT, val)
    978. 

  978. #define bfin_read_DMA17_CURR_Y_COUNT()		bfin_read32(DMA17_CURR_Y_COUNT)
    979. 

  979. #define bfin_write_DMA17_CURR_Y_COUNT(val)	bfin_write32(DMA17_CURR_Y_COUNT, val)
    980. 

  980. #define bfin_read_DMA17_BWL_COUNT()		bfin_read32(DMA17_BWL_COUNT)
    981. 

  981. #define bfin_write_DMA17_BWL_COUNT(val)		bfin_write32(DMA17_BWL_COUNT, val)
    982. 

  982. #define bfin_read_DMA17_CURR_BWL_COUNT()	bfin_read32(DMA17_CURR_BWL_COUNT)
    983. 

  983. #define bfin_write_DMA17_CURR_BWL_COUNT(val)	bfin_write32(DMA17_CURR_BWL_COUNT, val)
    984. 

  984. #define bfin_read_DMA17_BWM_COUNT()		bfin_read32(DMA17_BWM_COUNT)
    985. 

  985. #define bfin_write_DMA17_BWM_COUNT(val)		bfin_write32(DMA17_BWM_COUNT, val)
    986. 

  986. #define bfin_read_DMA17_CURR_BWM_COUNT()	bfin_read32(DMA17_CURR_BWM_COUNT)
    987. 

  987. #define bfin_write_DMA17_CURR_BWM_COUNT(val)	bfin_write32(DMA17_CURR_BWM_COUNT, val)
    988. 

  988. 

  989. /* DMA Channel 18 Registers */
    990. 

  990. 

  991. #define bfin_read_DMA18_NEXT_DESC_PTR() 	bfin_read32(DMA18_NEXT_DESC_PTR)
    992. 

  992. #define bfin_write_DMA18_NEXT_DESC_PTR(val) 	bfin_write32(DMA18_NEXT_DESC_PTR, val)
    993. 

  993. #define bfin_read_DMA18_START_ADDR() 		bfin_read32(DMA18_START_ADDR)
    994. 

  994. #define bfin_write_DMA18_START_ADDR(val) 	bfin_write32(DMA18_START_ADDR, val)
    995. 

  995. #define bfin_read_DMA18_CONFIG()		bfin_read32(DMA18_CONFIG)
    996. 

  996. #define bfin_write_DMA18_CONFIG(val)		bfin_write32(DMA18_CONFIG, val)
    997. 

  997. #define bfin_read_DMA18_X_COUNT()		bfin_read32(DMA18_X_COUNT)
    998. 

  998. #define bfin_write_DMA18_X_COUNT(val)		bfin_write32(DMA18_X_COUNT, val)
    999. 

  999. #define bfin_read_DMA18_X_MODIFY()		bfin_read32(DMA18_X_MODIFY)
    1000. 

  1000. #define bfin_write_DMA18_X_MODIFY(val) 		bfin_write32(DMA18_X_MODIFY, val)
    1001. 

  1001. #define bfin_read_DMA18_Y_COUNT()		bfin_read32(DMA18_Y_COUNT)
    1002. 

  1002. #define bfin_write_DMA18_Y_COUNT(val)		bfin_write32(DMA18_Y_COUNT, val)
    1003. 

  1003. #define bfin_read_DMA18_Y_MODIFY()		bfin_read32(DMA18_Y_MODIFY)
    1004. 

  1004. #define bfin_write_DMA18_Y_MODIFY(val) 		bfin_write32(DMA18_Y_MODIFY, val)
    1005. 

  1005. #define bfin_read_DMA18_CURR_DESC_PTR() 	bfin_read32(DMA18_CURR_DESC_PTR)
    1006. 

  1006. #define bfin_write_DMA18_CURR_DESC_PTR(val) 	bfin_write32(DMA18_CURR_DESC_PTR, val)
    1007. 

  1007. #define bfin_read_DMA18_PREV_DESC_PTR() 	bfin_read32(DMA18_PREV_DESC_PTR)
    1008. 

  1008. #define bfin_write_DMA18_PREV_DESC_PTR(val) 	bfin_write32(DMA18_PREV_DESC_PTR, val)
    1009. 

  1009. #define bfin_read_DMA18_CURR_ADDR() 		bfin_read32(DMA18_CURR_ADDR)
    1010. 

  1010. #define bfin_write_DMA18_CURR_ADDR(val) 	bfin_write32(DMA18_CURR_ADDR, val)
    1011. 

  1011. #define bfin_read_DMA18_IRQ_STATUS()		bfin_read32(DMA18_IRQ_STATUS)
    1012. 

  1012. #define bfin_write_DMA18_IRQ_STATUS(val)	bfin_write32(DMA18_IRQ_STATUS, val)
    1013. 

  1013. #define bfin_read_DMA18_CURR_X_COUNT()		bfin_read32(DMA18_CURR_X_COUNT)
    1014. 

  1014. #define bfin_write_DMA18_CURR_X_COUNT(val)	bfin_write32(DMA18_CURR_X_COUNT, val)
    1015. 

  1015. #define bfin_read_DMA18_CURR_Y_COUNT()		bfin_read32(DMA18_CURR_Y_COUNT)
    1016. 

  1016. #define bfin_write_DMA18_CURR_Y_COUNT(val)	bfin_write32(DMA18_CURR_Y_COUNT, val)
    1017. 

  1017. #define bfin_read_DMA18_BWL_COUNT()		bfin_read32(DMA18_BWL_COUNT)
    1018. 

  1018. #define bfin_write_DMA18_BWL_COUNT(val)		bfin_write32(DMA18_BWL_COUNT, val)
    1019. 

  1019. #define bfin_read_DMA18_CURR_BWL_COUNT()	bfin_read32(DMA18_CURR_BWL_COUNT)
    1020. 

  1020. #define bfin_write_DMA18_CURR_BWL_COUNT(val)	bfin_write32(DMA18_CURR_BWL_COUNT, val)
    1021. 

  1021. #define bfin_read_DMA18_BWM_COUNT()		bfin_read32(DMA18_BWM_COUNT)
    1022. 

  1022. #define bfin_write_DMA18_BWM_COUNT(val)		bfin_write32(DMA18_BWM_COUNT, val)
    1023. 

  1023. #define bfin_read_DMA18_CURR_BWM_COUNT()	bfin_read32(DMA18_CURR_BWM_COUNT)
    1024. 

  1024. #define bfin_write_DMA18_CURR_BWM_COUNT(val)	bfin_write32(DMA18_CURR_BWM_COUNT, val)
    1025. 

  1025. 

  1026. /* DMA Channel 19 Registers */
    1027. 

  1027. 

  1028. #define bfin_read_DMA19_NEXT_DESC_PTR() 	bfin_read32(DMA19_NEXT_DESC_PTR)
    1029. 

  1029. #define bfin_write_DMA19_NEXT_DESC_PTR(val) 	bfin_write32(DMA19_NEXT_DESC_PTR, val)
    1030. 

  1030. #define bfin_read_DMA19_START_ADDR() 		bfin_read32(DMA19_START_ADDR)
    1031. 

  1031. #define bfin_write_DMA19_START_ADDR(val) 	bfin_write32(DMA19_START_ADDR, val)
    1032. 

  1032. #define bfin_read_DMA19_CONFIG()		bfin_read32(DMA19_CONFIG)
    1033. 

  1033. #define bfin_write_DMA19_CONFIG(val)		bfin_write32(DMA19_CONFIG, val)
    1034. 

  1034. #define bfin_read_DMA19_X_COUNT()		bfin_read32(DMA19_X_COUNT)
    1035. 

  1035. #define bfin_write_DMA19_X_COUNT(val)		bfin_write32(DMA19_X_COUNT, val)
    1036. 

  1036. #define bfin_read_DMA19_X_MODIFY()		bfin_read32(DMA19_X_MODIFY)
    1037. 

  1037. #define bfin_write_DMA19_X_MODIFY(val) 		bfin_write32(DMA19_X_MODIFY, val)
    1038. 

  1038. #define bfin_read_DMA19_Y_COUNT()		bfin_read32(DMA19_Y_COUNT)
    1039. 

  1039. #define bfin_write_DMA19_Y_COUNT(val)		bfin_write32(DMA19_Y_COUNT, val)
    1040. 

  1040. #define bfin_read_DMA19_Y_MODIFY()		bfin_read32(DMA19_Y_MODIFY)
    1041. 

  1041. #define bfin_write_DMA19_Y_MODIFY(val) 		bfin_write32(DMA19_Y_MODIFY, val)
    1042. 

  1042. #define bfin_read_DMA19_CURR_DESC_PTR() 	bfin_read32(DMA19_CURR_DESC_PTR)
    1043. 

  1043. #define bfin_write_DMA19_CURR_DESC_PTR(val) 	bfin_write32(DMA19_CURR_DESC_PTR, val)
    1044. 

  1044. #define bfin_read_DMA19_PREV_DESC_PTR() 	bfin_read32(DMA19_PREV_DESC_PTR)
    1045. 

  1045. #define bfin_write_DMA19_PREV_DESC_PTR(val) 	bfin_write32(DMA19_PREV_DESC_PTR, val)
    1046. 

  1046. #define bfin_read_DMA19_CURR_ADDR() 		bfin_read32(DMA19_CURR_ADDR)
    1047. 

  1047. #define bfin_write_DMA19_CURR_ADDR(val) 	bfin_write32(DMA19_CURR_ADDR, val)
    1048. 

  1048. #define bfin_read_DMA19_IRQ_STATUS()		bfin_read32(DMA19_IRQ_STATUS)
    1049. 

  1049. #define bfin_write_DMA19_IRQ_STATUS(val)	bfin_write32(DMA19_IRQ_STATUS, val)
    1050. 

  1050. #define bfin_read_DMA19_CURR_X_COUNT()		bfin_read32(DMA19_CURR_X_COUNT)
    1051. 

  1051. #define bfin_write_DMA19_CURR_X_COUNT(val)	bfin_write32(DMA19_CURR_X_COUNT, val)
    1052. 

  1052. #define bfin_read_DMA19_CURR_Y_COUNT()		bfin_read32(DMA19_CURR_Y_COUNT)
    1053. 

  1053. #define bfin_write_DMA19_CURR_Y_COUNT(val)	bfin_write32(DMA19_CURR_Y_COUNT, val)
    1054. 

  1054. #define bfin_read_DMA19_BWL_COUNT()		bfin_read32(DMA19_BWL_COUNT)
    1055. 

  1055. #define bfin_write_DMA19_BWL_COUNT(val)		bfin_write32(DMA19_BWL_COUNT, val)
    1056. 

  1056. #define bfin_read_DMA19_CURR_BWL_COUNT()	bfin_read32(DMA19_CURR_BWL_COUNT)
    1057. 

  1057. #define bfin_write_DMA19_CURR_BWL_COUNT(val)	bfin_write32(DMA19_CURR_BWL_COUNT, val)
    1058. 

  1058. #define bfin_read_DMA19_BWM_COUNT()		bfin_read32(DMA19_BWM_COUNT)
    1059. 

  1059. #define bfin_write_DMA19_BWM_COUNT(val)		bfin_write32(DMA19_BWM_COUNT, val)
    1060. 

  1060. #define bfin_read_DMA19_CURR_BWM_COUNT()	bfin_read32(DMA19_CURR_BWM_COUNT)
    1061. 

  1061. #define bfin_write_DMA19_CURR_BWM_COUNT(val)	bfin_write32(DMA19_CURR_BWM_COUNT, val)
    1062. 

  1062. 

  1063. /* DMA Channel 20 Registers */
    1064. 

  1064. 

  1065. #define bfin_read_DMA20_NEXT_DESC_PTR() 	bfin_read32(DMA20_NEXT_DESC_PTR)
    1066. 

  1066. #define bfin_write_DMA20_NEXT_DESC_PTR(val) 	bfin_write32(DMA20_NEXT_DESC_PTR, val)
    1067. 

  1067. #define bfin_read_DMA20_START_ADDR() 		bfin_read32(DMA20_START_ADDR)
    1068. 

  1068. #define bfin_write_DMA20_START_ADDR(val) 	bfin_write32(DMA20_START_ADDR, val)
    1069. 

  1069. #define bfin_read_DMA20_CONFIG()		bfin_read32(DMA20_CONFIG)
    1070. 

  1070. #define bfin_write_DMA20_CONFIG(val)		bfin_write32(DMA20_CONFIG, val)
    1071. 

  1071. #define bfin_read_DMA20_X_COUNT()		bfin_read32(DMA20_X_COUNT)
    1072. 

  1072. #define bfin_write_DMA20_X_COUNT(val)		bfin_write32(DMA20_X_COUNT, val)
    1073. 

  1073. #define bfin_read_DMA20_X_MODIFY()		bfin_read32(DMA20_X_MODIFY)
    1074. 

  1074. #define bfin_write_DMA20_X_MODIFY(val) 		bfin_write32(DMA20_X_MODIFY, val)
    1075. 

  1075. #define bfin_read_DMA20_Y_COUNT()		bfin_read32(DMA20_Y_COUNT)
    1076. 

  1076. #define bfin_write_DMA20_Y_COUNT(val)		bfin_write32(DMA20_Y_COUNT, val)
    1077. 

  1077. #define bfin_read_DMA20_Y_MODIFY()		bfin_read32(DMA20_Y_MODIFY)
    1078. 

  1078. #define bfin_write_DMA20_Y_MODIFY(val) 		bfin_write32(DMA20_Y_MODIFY, val)
    1079. 

  1079. #define bfin_read_DMA20_CURR_DESC_PTR() 	bfin_read32(DMA20_CURR_DESC_PTR)
    1080. 

  1080. #define bfin_write_DMA20_CURR_DESC_PTR(val) 	bfin_write32(DMA20_CURR_DESC_PTR, val)
    1081. 

  1081. #define bfin_read_DMA20_PREV_DESC_PTR() 	bfin_read32(DMA20_PREV_DESC_PTR)
    1082. 

  1082. #define bfin_write_DMA20_PREV_DESC_PTR(val) 	bfin_write32(DMA20_PREV_DESC_PTR, val)
    1083. 

  1083. #define bfin_read_DMA20_CURR_ADDR() 		bfin_read32(DMA20_CURR_ADDR)
    1084. 

  1084. #define bfin_write_DMA20_CURR_ADDR(val) 	bfin_write32(DMA20_CURR_ADDR, val)
    1085. 

  1085. #define bfin_read_DMA20_IRQ_STATUS()		bfin_read32(DMA20_IRQ_STATUS)
    1086. 

  1086. #define bfin_write_DMA20_IRQ_STATUS(val)	bfin_write32(DMA20_IRQ_STATUS, val)
    1087. 

  1087. #define bfin_read_DMA20_CURR_X_COUNT()		bfin_read32(DMA20_CURR_X_COUNT)
    1088. 

  1088. #define bfin_write_DMA20_CURR_X_COUNT(val)	bfin_write32(DMA20_CURR_X_COUNT, val)
    1089. 

  1089. #define bfin_read_DMA20_CURR_Y_COUNT()		bfin_read32(DMA20_CURR_Y_COUNT)
    1090. 

  1090. #define bfin_write_DMA20_CURR_Y_COUNT(val)	bfin_write32(DMA20_CURR_Y_COUNT, val)
    1091. 

  1091. #define bfin_read_DMA20_BWL_COUNT()		bfin_read32(DMA20_BWL_COUNT)
    1092. 

  1092. #define bfin_write_DMA20_BWL_COUNT(val)		bfin_write32(DMA20_BWL_COUNT, val)
    1093. 

  1093. #define bfin_read_DMA20_CURR_BWL_COUNT()	bfin_read32(DMA20_CURR_BWL_COUNT)
    1094. 

  1094. #define bfin_write_DMA20_CURR_BWL_COUNT(val)	bfin_write32(DMA20_CURR_BWL_COUNT, val)
    1095. 

  1095. #define bfin_read_DMA20_BWM_COUNT()		bfin_read32(DMA20_BWM_COUNT)
    1096. 

  1096. #define bfin_write_DMA20_BWM_COUNT(val)		bfin_write32(DMA20_BWM_COUNT, val)
    1097. 

  1097. #define bfin_read_DMA20_CURR_BWM_COUNT()	bfin_read32(DMA20_CURR_BWM_COUNT)
    1098. 

  1098. #define bfin_write_DMA20_CURR_BWM_COUNT(val)	bfin_write32(DMA20_CURR_BWM_COUNT, val)
    1099. 

  1099. 

  1100. 

  1101. /* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
    1102. 

  1102. 

  1103. #define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
    1104. 

  1104. #define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
    1105. 

  1105. #define bfin_read_MDMA0_DEST_CRC0_START_ADDR() 		bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
    1106. 

  1106. #define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) 	bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
    1107. 

  1107. #define bfin_read_MDMA0_DEST_CRC0_CONFIG()		bfin_read32(MDMA0_DEST_CRC0_CONFIG)
    1108. 

  1108. #define bfin_write_MDMA0_DEST_CRC0_CONFIG(val)		bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
    1109. 

  1109. #define bfin_read_MDMA0_DEST_CRC0_X_COUNT()		bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
    1110. 

  1110. #define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val)		bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
    1111. 

  1111. #define bfin_read_MDMA0_DEST_CRC0_X_MODIFY()		bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
    1112. 

  1112. #define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) 	bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
    1113. 

  1113. #define bfin_read_MDMA0_DEST_CRC0_Y_COUNT()		bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
    1114. 

  1114. #define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val)		bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
    1115. 

  1115. #define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY()		bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
    1116. 

  1116. #define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) 	bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
    1117. 

  1117. #define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
    1118. 

  1118. #define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
    1119. 

  1119. #define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
    1120. 

  1120. #define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
    1121. 

  1121. #define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() 		bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
    1122. 

  1122. #define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) 	bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
    1123. 

  1123. #define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS()		bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
    1124. 

  1124. #define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val)	bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
    1125. 

  1125. #define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT()	bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
    1126. 

  1126. #define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val)	bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
    1127. 

  1127. #define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT()	bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
    1128. 

  1128. #define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val)	bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
    1129. 

  1129. #define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
    1130. 

  1130. #define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
    1131. 

  1131. #define bfin_read_MDMA0_SRC_CRC0_START_ADDR() 		bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
    1132. 

  1132. #define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) 	bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
    1133. 

  1133. #define bfin_read_MDMA0_SRC_CRC0_CONFIG()		bfin_read32(MDMA0_SRC_CRC0_CONFIG)
    1134. 

  1134. #define bfin_write_MDMA0_SRC_CRC0_CONFIG(val)		bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
    1135. 

  1135. #define bfin_read_MDMA0_SRC_CRC0_X_COUNT()		bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
    1136. 

  1136. #define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val)		bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
    1137. 

  1137. #define bfin_read_MDMA0_SRC_CRC0_X_MODIFY()		bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
    1138. 

  1138. #define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) 	bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
    1139. 

  1139. #define bfin_read_MDMA0_SRC_CRC0_Y_COUNT()		bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
    1140. 

  1140. #define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val)		bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
    1141. 

  1141. #define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY()		bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
    1142. 

  1142. #define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) 	bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
    1143. 

  1143. #define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
    1144. 

  1144. #define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
    1145. 

  1145. #define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
    1146. 

  1146. #define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
    1147. 

  1147. #define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() 		bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
    1148. 

  1148. #define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) 	bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
    1149. 

  1149. #define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS()		bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
    1150. 

  1150. #define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val)	bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
    1151. 

  1151. #define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT()		bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
    1152. 

  1152. #define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val)	bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
    1153. 

  1153. #define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT()		bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
    1154. 

  1154. #define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val)	bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
    1155. 

  1155. 

  1156. /* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
    1157. 

  1157. 

  1158. #define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
    1159. 

  1159. #define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
    1160. 

  1160. #define bfin_read_MDMA1_DEST_CRC1_START_ADDR() 		bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
    1161. 

  1161. #define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) 	bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
    1162. 

  1162. #define bfin_read_MDMA1_DEST_CRC1_CONFIG()		bfin_read32(MDMA1_DEST_CRC1_CONFIG)
    1163. 

  1163. #define bfin_write_MDMA1_DEST_CRC1_CONFIG(val)		bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
    1164. 

  1164. #define bfin_read_MDMA1_DEST_CRC1_X_COUNT()		bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
    1165. 

  1165. #define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val)		bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
    1166. 

  1166. #define bfin_read_MDMA1_DEST_CRC1_X_MODIFY()		bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
    1167. 

  1167. #define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) 	bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
    1168. 

  1168. #define bfin_read_MDMA1_DEST_CRC1_Y_COUNT()		bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
    1169. 

  1169. #define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val)		bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
    1170. 

  1170. #define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY()		bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
    1171. 

  1171. #define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) 	bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
    1172. 

  1172. #define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
    1173. 

  1173. #define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
    1174. 

  1174. #define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
    1175. 

  1175. #define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
    1176. 

  1176. #define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() 		bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
    1177. 

  1177. #define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) 	bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
    1178. 

  1178. #define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS()		bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
    1179. 

  1179. #define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val)	bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
    1180. 

  1180. #define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT()	bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
    1181. 

  1181. #define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val)	bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
    1182. 

  1182. #define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT()	bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
    1183. 

  1183. #define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val)	bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
    1184. 

  1184. #define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
    1185. 

  1185. #define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
    1186. 

  1186. #define bfin_read_MDMA1_SRC_CRC1_START_ADDR() 		bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
    1187. 

  1187. #define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) 	bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
    1188. 

  1188. #define bfin_read_MDMA1_SRC_CRC1_CONFIG()		bfin_read32(MDMA1_SRC_CRC1_CONFIG)
    1189. 

  1189. #define bfin_write_MDMA1_SRC_CRC1_CONFIG(val)		bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
    1190. 

  1190. #define bfin_read_MDMA1_SRC_CRC1_X_COUNT()		bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
    1191. 

  1191. #define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val)		bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
    1192. 

  1192. #define bfin_read_MDMA1_SRC_CRC1_X_MODIFY()		bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
    1193. 

  1193. #define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) 	bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
    1194. 

  1194. #define bfin_read_MDMA1_SRC_CRC1_Y_COUNT()		bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
    1195. 

  1195. #define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val)		bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
    1196. 

  1196. #define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY()		bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
    1197. 

  1197. #define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) 	bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
    1198. 

  1198. #define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
    1199. 

  1199. #define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
    1200. 

  1200. #define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
    1201. 

  1201. #define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
    1202. 

  1202. #define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() 		bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
    1203. 

  1203. #define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) 	bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
    1204. 

  1204. #define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS()		bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
    1205. 

  1205. #define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val)	bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
    1206. 

  1206. #define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT()		bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
    1207. 

  1207. #define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val)	bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
    1208. 

  1208. #define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT()		bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
    1209. 

  1209. #define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val)	bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
    1210. 

  1210. 

  1211. 

  1212. /* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
    1213. 

  1213. 

  1214. #define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() 		bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
    1215. 

  1215. #define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
    1216. 

  1216. #define bfin_read_MDMA2_DEST_START_ADDR() 		bfin_read32(MDMA2_DEST_START_ADDR)
    1217. 

  1217. #define bfin_write_MDMA2_DEST_START_ADDR(val) 		bfin_write32(MDMA2_DEST_START_ADDR, val)
    1218. 

  1218. #define bfin_read_MDMA2_DEST_CONFIG()			bfin_read32(MDMA2_DEST_CONFIG)
    1219. 

  1219. #define bfin_write_MDMA2_DEST_CONFIG(val)		bfin_write32(MDMA2_DEST_CONFIG, val)
    1220. 

  1220. #define bfin_read_MDMA2_DEST_X_COUNT()			bfin_read32(MDMA2_DEST_X_COUNT)
    1221. 

  1221. #define bfin_write_MDMA2_DEST_X_COUNT(val)		bfin_write32(MDMA2_DEST_X_COUNT, val)
    1222. 

  1222. #define bfin_read_MDMA2_DEST_X_MODIFY()			bfin_read32(MDMA2_DEST_X_MODIFY)
    1223. 

  1223. #define bfin_write_MDMA2_DEST_X_MODIFY(val) 		bfin_write32(MDMA2_DEST_X_MODIFY, val)
    1224. 

  1224. #define bfin_read_MDMA2_DEST_Y_COUNT()			bfin_read32(MDMA2_DEST_Y_COUNT)
    1225. 

  1225. #define bfin_write_MDMA2_DEST_Y_COUNT(val)		bfin_write32(MDMA2_DEST_Y_COUNT, val)
    1226. 

  1226. #define bfin_read_MDMA2_DEST_Y_MODIFY()			bfin_read32(MDMA2_DEST_Y_MODIFY)
    1227. 

  1227. #define bfin_write_MDMA2_DEST_Y_MODIFY(val) 		bfin_write32(MDMA2_DEST_Y_MODIFY, val)
    1228. 

  1228. #define bfin_read_MDMA2_DEST_CURR_DESC_PTR() 		bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
    1229. 

  1229. #define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
    1230. 

  1230. #define bfin_read_MDMA2_DEST_PREV_DESC_PTR() 		bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
    1231. 

  1231. #define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
    1232. 

  1232. #define bfin_read_MDMA2_DEST_CURR_ADDR() 		bfin_read32(MDMA2_DEST_CURR_ADDR)
    1233. 

  1233. #define bfin_write_MDMA2_DEST_CURR_ADDR(val) 		bfin_write32(MDMA2_DEST_CURR_ADDR, val)
    1234. 

  1234. #define bfin_read_MDMA2_DEST_IRQ_STATUS()		bfin_read32(MDMA2_DEST_IRQ_STATUS)
    1235. 

  1235. #define bfin_write_MDMA2_DEST_IRQ_STATUS(val)		bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
    1236. 

  1236. #define bfin_read_MDMA2_DEST_CURR_X_COUNT()		bfin_read32(MDMA2_DEST_CURR_X_COUNT)
    1237. 

  1237. #define bfin_write_MDMA2_DEST_CURR_X_COUNT(val)		bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
    1238. 

  1238. #define bfin_read_MDMA2_DEST_CURR_Y_COUNT()		bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
    1239. 

  1239. #define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val)		bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
    1240. 

  1240. #define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() 		bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
    1241. 

  1241. #define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) 	bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
    1242. 

  1242. #define bfin_read_MDMA2_SRC_START_ADDR() 		bfin_read32(MDMA2_SRC_START_ADDR)
    1243. 

  1243. #define bfin_write_MDMA2_SRC_START_ADDR(val) 		bfin_write32(MDMA2_SRC_START_ADDR, val)
    1244. 

  1244. #define bfin_read_MDMA2_SRC_CONFIG()			bfin_read32(MDMA2_SRC_CONFIG)
    1245. 

  1245. #define bfin_write_MDMA2_SRC_CONFIG(val)		bfin_write32(MDMA2_SRC_CONFIG, val)
    1246. 

  1246. #define bfin_read_MDMA2_SRC_X_COUNT()			bfin_read32(MDMA2_SRC_X_COUNT)
    1247. 

  1247. #define bfin_write_MDMA2_SRC_X_COUNT(val)		bfin_write32(MDMA2_SRC_X_COUNT, val)
    1248. 

  1248. #define bfin_read_MDMA2_SRC_X_MODIFY()			bfin_read32(MDMA2_SRC_X_MODIFY)
    1249. 

  1249. #define bfin_write_MDMA2_SRC_X_MODIFY(val) 		bfin_write32(MDMA2_SRC_X_MODIFY, val)
    1250. 

  1250. #define bfin_read_MDMA2_SRC_Y_COUNT()			bfin_read32(MDMA2_SRC_Y_COUNT)
    1251. 

  1251. #define bfin_write_MDMA2_SRC_Y_COUNT(val)		bfin_write32(MDMA2_SRC_Y_COUNT, val)
    1252. 

  1252. #define bfin_read_MDMA2_SRC_Y_MODIFY()			bfin_read32(MDMA2_SRC_Y_MODIFY)
    1253. 

  1253. #define bfin_write_MDMA2_SRC_Y_MODIFY(val) 		bfin_write32(MDMA2_SRC_Y_MODIFY, val)
    1254. 

  1254. #define bfin_read_MDMA2_SRC_CURR_DESC_PTR() 		bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
    1255. 

  1255. #define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val)		bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
    1256. 

  1256. #define bfin_read_MDMA2_SRC_PREV_DESC_PTR() 		bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
    1257. 

  1257. #define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) 	bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
    1258. 

  1258. #define bfin_read_MDMA2_SRC_CURR_ADDR() 		bfin_read32(MDMA2_SRC_CURR_ADDR)
    1259. 

  1259. #define bfin_write_MDMA2_SRC_CURR_ADDR(val) 		bfin_write32(MDMA2_SRC_CURR_ADDR, val)
    1260. 

  1260. #define bfin_read_MDMA2_SRC_IRQ_STATUS()		bfin_read32(MDMA2_SRC_IRQ_STATUS)
    1261. 

  1261. #define bfin_write_MDMA2_SRC_IRQ_STATUS(val)		bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
    1262. 

  1262. #define bfin_read_MDMA2_SRC_CURR_X_COUNT()		bfin_read32(MDMA2_SRC_CURR_X_COUNT)
    1263. 

  1263. #define bfin_write_MDMA2_SRC_CURR_X_COUNT(val)		bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
    1264. 

  1264. #define bfin_read_MDMA2_SRC_CURR_Y_COUNT()		bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
    1265. 

  1265. #define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val)		bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
    1266. 

  1266. 

  1267. /* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
    1268. 

  1268. 

  1269. #define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() 		bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
    1270. 

  1270. #define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
    1271. 

  1271. #define bfin_read_MDMA3_DEST_START_ADDR() 		bfin_read32(MDMA3_DEST_START_ADDR)
    1272. 

  1272. #define bfin_write_MDMA3_DEST_START_ADDR(val) 		bfin_write32(MDMA3_DEST_START_ADDR, val)
    1273. 

  1273. #define bfin_read_MDMA3_DEST_CONFIG()			bfin_read32(MDMA3_DEST_CONFIG)
    1274. 

  1274. #define bfin_write_MDMA3_DEST_CONFIG(val)		bfin_write32(MDMA3_DEST_CONFIG, val)
    1275. 

  1275. #define bfin_read_MDMA3_DEST_X_COUNT()			bfin_read32(MDMA3_DEST_X_COUNT)
    1276. 

  1276. #define bfin_write_MDMA3_DEST_X_COUNT(val)		bfin_write32(MDMA3_DEST_X_COUNT, val)
    1277. 

  1277. #define bfin_read_MDMA3_DEST_X_MODIFY()			bfin_read32(MDMA3_DEST_X_MODIFY)
    1278. 

  1278. #define bfin_write_MDMA3_DEST_X_MODIFY(val) 		bfin_write32(MDMA3_DEST_X_MODIFY, val)
    1279. 

  1279. #define bfin_read_MDMA3_DEST_Y_COUNT()			bfin_read32(MDMA3_DEST_Y_COUNT)
    1280. 

  1280. #define bfin_write_MDMA3_DEST_Y_COUNT(val)		bfin_write32(MDMA3_DEST_Y_COUNT, val)
    1281. 

  1281. #define bfin_read_MDMA3_DEST_Y_MODIFY()			bfin_read32(MDMA3_DEST_Y_MODIFY)
    1282. 

  1282. #define bfin_write_MDMA3_DEST_Y_MODIFY(val) 		bfin_write32(MDMA3_DEST_Y_MODIFY, val)
    1283. 

  1283. #define bfin_read_MDMA3_DEST_CURR_DESC_PTR() 		bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
    1284. 

  1284. #define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
    1285. 

  1285. #define bfin_read_MDMA3_DEST_PREV_DESC_PTR()	 	bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
    1286. 

  1286. #define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
    1287. 

  1287. #define bfin_read_MDMA3_DEST_CURR_ADDR() 		bfin_read32(MDMA3_DEST_CURR_ADDR)
    1288. 

  1288. #define bfin_write_MDMA3_DEST_CURR_ADDR(val) 		bfin_write32(MDMA3_DEST_CURR_ADDR, val)
    1289. 

  1289. #define bfin_read_MDMA3_DEST_IRQ_STATUS()		bfin_read32(MDMA3_DEST_IRQ_STATUS)
    1290. 

  1290. #define bfin_write_MDMA3_DEST_IRQ_STATUS(val)		bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
    1291. 

  1291. #define bfin_read_MDMA3_DEST_CURR_X_COUNT()		bfin_read32(MDMA3_DEST_CURR_X_COUNT)
    1292. 

  1292. #define bfin_write_MDMA3_DEST_CURR_X_COUNT(val)		bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
    1293. 

  1293. #define bfin_read_MDMA3_DEST_CURR_Y_COUNT()		bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
    1294. 

  1294. #define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val)		bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
    1295. 

  1295. #define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() 		bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
    1296. 

  1296. #define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
    1297. 

  1297. #define bfin_read_MDMA3_SRC_START_ADDR() 		bfin_read32(MDMA3_SRC_START_ADDR)
    1298. 

  1298. #define bfin_write_MDMA3_SRC_START_ADDR(val) 		bfin_write32(MDMA3_SRC_START_ADDR, val)
    1299. 

  1299. #define bfin_read_MDMA3_SRC_CONFIG()			bfin_read32(MDMA3_SRC_CONFIG)
    1300. 

  1300. #define bfin_write_MDMA3_SRC_CONFIG(val)		bfin_write32(MDMA3_SRC_CONFIG, val)
    1301. 

  1301. #define bfin_read_MDMA3_SRC_X_COUNT()			bfin_read32(MDMA3_SRC_X_COUNT)
    1302. 

  1302. #define bfin_write_MDMA3_SRC_X_COUNT(val)		bfin_write32(MDMA3_SRC_X_COUNT, val)
    1303. 

  1303. #define bfin_read_MDMA3_SRC_X_MODIFY()			bfin_read32(MDMA3_SRC_X_MODIFY)
    1304. 

  1304. #define bfin_write_MDMA3_SRC_X_MODIFY(val) 		bfin_write32(MDMA3_SRC_X_MODIFY, val)
    1305. 

  1305. #define bfin_read_MDMA3_SRC_Y_COUNT()			bfin_read32(MDMA3_SRC_Y_COUNT)
    1306. 

  1306. #define bfin_write_MDMA3_SRC_Y_COUNT(val)		bfin_write32(MDMA3_SRC_Y_COUNT, val)
    1307. 

  1307. #define bfin_read_MDMA3_SRC_Y_MODIFY()			bfin_read32(MDMA3_SRC_Y_MODIFY)
    1308. 

  1308. #define bfin_write_MDMA3_SRC_Y_MODIFY(val) 		bfin_write32(MDMA3_SRC_Y_MODIFY, val)
    1309. 

  1309. #define bfin_read_MDMA3_SRC_CURR_DESC_PTR() 		bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
    1310. 

  1310. #define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
    1311. 

  1311. #define bfin_read_MDMA3_SRC_PREV_DESC_PTR() 		bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
    1312. 

  1312. #define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
    1313. 

  1313. #define bfin_read_MDMA3_SRC_CURR_ADDR() 		bfin_read32(MDMA3_SRC_CURR_ADDR)
    1314. 

  1314. #define bfin_write_MDMA3_SRC_CURR_ADDR(val) 		bfin_write32(MDMA3_SRC_CURR_ADDR, val)
    1315. 

  1315. #define bfin_read_MDMA3_SRC_IRQ_STATUS()		bfin_read32(MDMA3_SRC_IRQ_STATUS)
    1316. 

  1316. #define bfin_write_MDMA3_SRC_IRQ_STATUS(val)		bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
    1317. 

  1317. #define bfin_read_MDMA3_SRC_CURR_X_COUNT()		bfin_read32(MDMA3_SRC_CURR_X_COUNT)
    1318. 

  1318. #define bfin_write_MDMA3_SRC_CURR_X_COUNT(val)		bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
    1319. 

  1319. #define bfin_read_MDMA3_SRC_CURR_Y_COUNT()		bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
    1320. 

  1320. #define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val)		bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
    1321. 

  1321. 

  1322. 

  1323. /* DMA Channel 29 Registers */
    1324. 

  1324. 

  1325. #define bfin_read_DMA29_NEXT_DESC_PTR() 	bfin_read32(DMA29_NEXT_DESC_PTR)
    1326. 

  1326. #define bfin_write_DMA29_NEXT_DESC_PTR(val) 	bfin_write32(DMA29_NEXT_DESC_PTR, val)
    1327. 

  1327. #define bfin_read_DMA29_START_ADDR() 		bfin_read32(DMA29_START_ADDR)
    1328. 

  1328. #define bfin_write_DMA29_START_ADDR(val) 	bfin_write32(DMA29_START_ADDR, val)
    1329. 

  1329. #define bfin_read_DMA29_CONFIG()		bfin_read32(DMA29_CONFIG)
    1330. 

  1330. #define bfin_write_DMA29_CONFIG(val)		bfin_write32(DMA29_CONFIG, val)
    1331. 

  1331. #define bfin_read_DMA29_X_COUNT()		bfin_read32(DMA29_X_COUNT)
    1332. 

  1332. #define bfin_write_DMA29_X_COUNT(val)		bfin_write32(DMA29_X_COUNT, val)
    1333. 

  1333. #define bfin_read_DMA29_X_MODIFY()		bfin_read32(DMA29_X_MODIFY)
    1334. 

  1334. #define bfin_write_DMA29_X_MODIFY(val) 		bfin_write32(DMA29_X_MODIFY, val)
    1335. 

  1335. #define bfin_read_DMA29_Y_COUNT()		bfin_read32(DMA29_Y_COUNT)
    1336. 

  1336. #define bfin_write_DMA29_Y_COUNT(val)		bfin_write32(DMA29_Y_COUNT, val)
    1337. 

  1337. #define bfin_read_DMA29_Y_MODIFY()		bfin_read32(DMA29_Y_MODIFY)
    1338. 

  1338. #define bfin_write_DMA29_Y_MODIFY(val) 		bfin_write32(DMA29_Y_MODIFY, val)
    1339. 

  1339. #define bfin_read_DMA29_CURR_DESC_PTR() 	bfin_read32(DMA29_CURR_DESC_PTR)
    1340. 

  1340. #define bfin_write_DMA29_CURR_DESC_PTR(val) 	bfin_write32(DMA29_CURR_DESC_PTR, val)
    1341. 

  1341. #define bfin_read_DMA29_PREV_DESC_PTR() 	bfin_read32(DMA29_PREV_DESC_PTR)
    1342. 

  1342. #define bfin_write_DMA29_PREV_DESC_PTR(val) 	bfin_write32(DMA29_PREV_DESC_PTR, val)
    1343. 

  1343. #define bfin_read_DMA29_CURR_ADDR() 		bfin_read32(DMA29_CURR_ADDR)
    1344. 

  1344. #define bfin_write_DMA29_CURR_ADDR(val) 	bfin_write32(DMA29_CURR_ADDR, val)
    1345. 

  1345. #define bfin_read_DMA29_IRQ_STATUS()		bfin_read32(DMA29_IRQ_STATUS)
    1346. 

  1346. #define bfin_write_DMA29_IRQ_STATUS(val)	bfin_write32(DMA29_IRQ_STATUS, val)
    1347. 

  1347. #define bfin_read_DMA29_CURR_X_COUNT()		bfin_read32(DMA29_CURR_X_COUNT)
    1348. 

  1348. #define bfin_write_DMA29_CURR_X_COUNT(val)	bfin_write32(DMA29_CURR_X_COUNT, val)
    1349. 

  1349. #define bfin_read_DMA29_CURR_Y_COUNT()		bfin_read32(DMA29_CURR_Y_COUNT)
    1350. 

  1350. #define bfin_write_DMA29_CURR_Y_COUNT(val)	bfin_write32(DMA29_CURR_Y_COUNT, val)
    1351. 

  1351. #define bfin_read_DMA29_BWL_COUNT()		bfin_read32(DMA29_BWL_COUNT)
    1352. 

  1352. #define bfin_write_DMA29_BWL_COUNT(val)		bfin_write32(DMA29_BWL_COUNT, val)
    1353. 

  1353. #define bfin_read_DMA29_CURR_BWL_COUNT()	bfin_read32(DMA29_CURR_BWL_COUNT)
    1354. 

  1354. #define bfin_write_DMA29_CURR_BWL_COUNT(val)	bfin_write32(DMA29_CURR_BWL_COUNT, val)
    1355. 

  1355. #define bfin_read_DMA29_BWM_COUNT()		bfin_read32(DMA29_BWM_COUNT)
    1356. 

  1356. #define bfin_write_DMA29_BWM_COUNT(val)		bfin_write32(DMA29_BWM_COUNT, val)
    1357. 

  1357. #define bfin_read_DMA29_CURR_BWM_COUNT()	bfin_read32(DMA29_CURR_BWM_COUNT)
    1358. 

  1358. #define bfin_write_DMA29_CURR_BWM_COUNT(val)	bfin_write32(DMA29_CURR_BWM_COUNT, val)
    1359. 

  1359. 

  1360. /* DMA Channel 30 Registers */
    1361. 

  1361. 

  1362. #define bfin_read_DMA30_NEXT_DESC_PTR() 	bfin_read32(DMA30_NEXT_DESC_PTR)
    1363. 

  1363. #define bfin_write_DMA30_NEXT_DESC_PTR(val) 	bfin_write32(DMA30_NEXT_DESC_PTR, val)
    1364. 

  1364. #define bfin_read_DMA30_START_ADDR() 		bfin_read32(DMA30_START_ADDR)
    1365. 

  1365. #define bfin_write_DMA30_START_ADDR(val) 	bfin_write32(DMA30_START_ADDR, val)
    1366. 

  1366. #define bfin_read_DMA30_CONFIG()		bfin_read32(DMA30_CONFIG)
    1367. 

  1367. #define bfin_write_DMA30_CONFIG(val)		bfin_write32(DMA30_CONFIG, val)
    1368. 

  1368. #define bfin_read_DMA30_X_COUNT()		bfin_read32(DMA30_X_COUNT)
    1369. 

  1369. #define bfin_write_DMA30_X_COUNT(val)		bfin_write32(DMA30_X_COUNT, val)
    1370. 

  1370. #define bfin_read_DMA30_X_MODIFY()		bfin_read32(DMA30_X_MODIFY)
    1371. 

  1371. #define bfin_write_DMA30_X_MODIFY(val) 		bfin_write32(DMA30_X_MODIFY, val)
    1372. 

  1372. #define bfin_read_DMA30_Y_COUNT()		bfin_read32(DMA30_Y_COUNT)
    1373. 

  1373. #define bfin_write_DMA30_Y_COUNT(val)		bfin_write32(DMA30_Y_COUNT, val)
    1374. 

  1374. #define bfin_read_DMA30_Y_MODIFY()		bfin_read32(DMA30_Y_MODIFY)
    1375. 

  1375. #define bfin_write_DMA30_Y_MODIFY(val) 		bfin_write32(DMA30_Y_MODIFY, val)
    1376. 

  1376. #define bfin_read_DMA30_CURR_DESC_PTR() 	bfin_read32(DMA30_CURR_DESC_PTR)
    1377. 

  1377. #define bfin_write_DMA30_CURR_DESC_PTR(val) 	bfin_write32(DMA30_CURR_DESC_PTR, val)
    1378. 

  1378. #define bfin_read_DMA30_PREV_DESC_PTR() 	bfin_read32(DMA30_PREV_DESC_PTR)
    1379. 

  1379. #define bfin_write_DMA30_PREV_DESC_PTR(val) 	bfin_write32(DMA30_PREV_DESC_PTR, val)
    1380. 

  1380. #define bfin_read_DMA30_CURR_ADDR() 		bfin_read32(DMA30_CURR_ADDR)
    1381. 

  1381. #define bfin_write_DMA30_CURR_ADDR(val) 	bfin_write32(DMA30_CURR_ADDR, val)
    1382. 

  1382. #define bfin_read_DMA30_IRQ_STATUS()		bfin_read32(DMA30_IRQ_STATUS)
    1383. 

  1383. #define bfin_write_DMA30_IRQ_STATUS(val)	bfin_write32(DMA30_IRQ_STATUS, val)
    1384. 

  1384. #define bfin_read_DMA30_CURR_X_COUNT()		bfin_read32(DMA30_CURR_X_COUNT)
    1385. 

  1385. #define bfin_write_DMA30_CURR_X_COUNT(val)	bfin_write32(DMA30_CURR_X_COUNT, val)
    1386. 

  1386. #define bfin_read_DMA30_CURR_Y_COUNT()		bfin_read32(DMA30_CURR_Y_COUNT)
    1387. 

  1387. #define bfin_write_DMA30_CURR_Y_COUNT(val)	bfin_write32(DMA30_CURR_Y_COUNT, val)
    1388. 

  1388. #define bfin_read_DMA30_BWL_COUNT()		bfin_read32(DMA30_BWL_COUNT)
    1389. 

  1389. #define bfin_write_DMA30_BWL_COUNT(val)		bfin_write32(DMA30_BWL_COUNT, val)
    1390. 

  1390. #define bfin_read_DMA30_CURR_BWL_COUNT()	bfin_read32(DMA30_CURR_BWL_COUNT)
    1391. 

  1391. #define bfin_write_DMA30_CURR_BWL_COUNT(val)	bfin_write32(DMA30_CURR_BWL_COUNT, val)
    1392. 

  1392. #define bfin_read_DMA30_BWM_COUNT()		bfin_read32(DMA30_BWM_COUNT)
    1393. 

  1393. #define bfin_write_DMA30_BWM_COUNT(val)		bfin_write32(DMA30_BWM_COUNT, val)
    1394. 

  1394. #define bfin_read_DMA30_CURR_BWM_COUNT()	bfin_read32(DMA30_CURR_BWM_COUNT)
    1395. 

  1395. #define bfin_write_DMA30_CURR_BWM_COUNT(val)	bfin_write32(DMA30_CURR_BWM_COUNT, val)
    1396. 

  1396. 

  1397. /* DMA Channel 31 Registers */
    1398. 

  1398. 

  1399. #define bfin_read_DMA31_NEXT_DESC_PTR() 	bfin_read32(DMA31_NEXT_DESC_PTR)
    1400. 

  1400. #define bfin_write_DMA31_NEXT_DESC_PTR(val) 	bfin_write32(DMA31_NEXT_DESC_PTR, val)
    1401. 

  1401. #define bfin_read_DMA31_START_ADDR() 		bfin_read32(DMA31_START_ADDR)
    1402. 

  1402. #define bfin_write_DMA31_START_ADDR(val) 	bfin_write32(DMA31_START_ADDR, val)
    1403. 

  1403. #define bfin_read_DMA31_CONFIG()		bfin_read32(DMA31_CONFIG)
    1404. 

  1404. #define bfin_write_DMA31_CONFIG(val)		bfin_write32(DMA31_CONFIG, val)
    1405. 

  1405. #define bfin_read_DMA31_X_COUNT()		bfin_read32(DMA31_X_COUNT)
    1406. 

  1406. #define bfin_write_DMA31_X_COUNT(val)		bfin_write32(DMA31_X_COUNT, val)
    1407. 

  1407. #define bfin_read_DMA31_X_MODIFY()		bfin_read32(DMA31_X_MODIFY)
    1408. 

  1408. #define bfin_write_DMA31_X_MODIFY(val) 		bfin_write32(DMA31_X_MODIFY, val)
    1409. 

  1409. #define bfin_read_DMA31_Y_COUNT()		bfin_read32(DMA31_Y_COUNT)
    1410. 

  1410. #define bfin_write_DMA31_Y_COUNT(val)		bfin_write32(DMA31_Y_COUNT, val)
    1411. 

  1411. #define bfin_read_DMA31_Y_MODIFY()		bfin_read32(DMA31_Y_MODIFY)
    1412. 

  1412. #define bfin_write_DMA31_Y_MODIFY(val) 		bfin_write32(DMA31_Y_MODIFY, val)
    1413. 

  1413. #define bfin_read_DMA31_CURR_DESC_PTR() 	bfin_read32(DMA31_CURR_DESC_PTR)
    1414. 

  1414. #define bfin_write_DMA31_CURR_DESC_PTR(val) 	bfin_write32(DMA31_CURR_DESC_PTR, val)
    1415. 

  1415. #define bfin_read_DMA31_PREV_DESC_PTR() 	bfin_read32(DMA31_PREV_DESC_PTR)
    1416. 

  1416. #define bfin_write_DMA31_PREV_DESC_PTR(val) 	bfin_write32(DMA31_PREV_DESC_PTR, val)
    1417. 

  1417. #define bfin_read_DMA31_CURR_ADDR() 		bfin_read32(DMA31_CURR_ADDR)
    1418. 

  1418. #define bfin_write_DMA31_CURR_ADDR(val) 	bfin_write32(DMA31_CURR_ADDR, val)
    1419. 

  1419. #define bfin_read_DMA31_IRQ_STATUS()		bfin_read32(DMA31_IRQ_STATUS)
    1420. 

  1420. #define bfin_write_DMA31_IRQ_STATUS(val)	bfin_write32(DMA31_IRQ_STATUS, val)
    1421. 

  1421. #define bfin_read_DMA31_CURR_X_COUNT()		bfin_read32(DMA31_CURR_X_COUNT)
    1422. 

  1422. #define bfin_write_DMA31_CURR_X_COUNT(val)	bfin_write32(DMA31_CURR_X_COUNT, val)
    1423. 

  1423. #define bfin_read_DMA31_CURR_Y_COUNT()		bfin_read32(DMA31_CURR_Y_COUNT)
    1424. 

  1424. #define bfin_write_DMA31_CURR_Y_COUNT(val)	bfin_write32(DMA31_CURR_Y_COUNT, val)
    1425. 

  1425. #define bfin_read_DMA31_BWL_COUNT()		bfin_read32(DMA31_BWL_COUNT)
    1426. 

  1426. #define bfin_write_DMA31_BWL_COUNT(val)		bfin_write32(DMA31_BWL_COUNT, val)
    1427. 

  1427. #define bfin_read_DMA31_CURR_BWL_COUNT()	bfin_read32(DMA31_CURR_BWL_COUNT)
    1428. 

  1428. #define bfin_write_DMA31_CURR_BWL_COUNT(val)	bfin_write32(DMA31_CURR_BWL_COUNT, val)
    1429. 

  1429. #define bfin_read_DMA31_BWM_COUNT()		bfin_read32(DMA31_BWM_COUNT)
    1430. 

  1430. #define bfin_write_DMA31_BWM_COUNT(val)		bfin_write32(DMA31_BWM_COUNT, val)
    1431. 

  1431. #define bfin_read_DMA31_CURR_BWM_COUNT()	bfin_read32(DMA31_CURR_BWM_COUNT)
    1432. 

  1432. #define bfin_write_DMA31_CURR_BWM_COUNT(val)	bfin_write32(DMA31_CURR_BWM_COUNT, val)
    1433. 

  1433. 

  1434. /* DMA Channel 32 Registers */
    1435. 

  1435. 

  1436. #define bfin_read_DMA32_NEXT_DESC_PTR() 	bfin_read32(DMA32_NEXT_DESC_PTR)
    1437. 

  1437. #define bfin_write_DMA32_NEXT_DESC_PTR(val) 	bfin_write32(DMA32_NEXT_DESC_PTR, val)
    1438. 

  1438. #define bfin_read_DMA32_START_ADDR() 		bfin_read32(DMA32_START_ADDR)
    1439. 

  1439. #define bfin_write_DMA32_START_ADDR(val) 	bfin_write32(DMA32_START_ADDR, val)
    1440. 

  1440. #define bfin_read_DMA32_CONFIG()		bfin_read32(DMA32_CONFIG)
    1441. 

  1441. #define bfin_write_DMA32_CONFIG(val)		bfin_write32(DMA32_CONFIG, val)
    1442. 

  1442. #define bfin_read_DMA32_X_COUNT()		bfin_read32(DMA32_X_COUNT)
    1443. 

  1443. #define bfin_write_DMA32_X_COUNT(val)		bfin_write32(DMA32_X_COUNT, val)
    1444. 

  1444. #define bfin_read_DMA32_X_MODIFY()		bfin_read32(DMA32_X_MODIFY)
    1445. 

  1445. #define bfin_write_DMA32_X_MODIFY(val) 		bfin_write32(DMA32_X_MODIFY, val)
    1446. 

  1446. #define bfin_read_DMA32_Y_COUNT()		bfin_read32(DMA32_Y_COUNT)
    1447. 

  1447. #define bfin_write_DMA32_Y_COUNT(val)		bfin_write32(DMA32_Y_COUNT, val)
    1448. 

  1448. #define bfin_read_DMA32_Y_MODIFY()		bfin_read32(DMA32_Y_MODIFY)
    1449. 

  1449. #define bfin_write_DMA32_Y_MODIFY(val) 		bfin_write32(DMA32_Y_MODIFY, val)
    1450. 

  1450. #define bfin_read_DMA32_CURR_DESC_PTR() 	bfin_read32(DMA32_CURR_DESC_PTR)
    1451. 

  1451. #define bfin_write_DMA32_CURR_DESC_PTR(val) 	bfin_write32(DMA32_CURR_DESC_PTR, val)
    1452. 

  1452. #define bfin_read_DMA32_PREV_DESC_PTR() 	bfin_read32(DMA32_PREV_DESC_PTR)
    1453. 

  1453. #define bfin_write_DMA32_PREV_DESC_PTR(val) 	bfin_write32(DMA32_PREV_DESC_PTR, val)
    1454. 

  1454. #define bfin_read_DMA32_CURR_ADDR() 		bfin_read32(DMA32_CURR_ADDR)
    1455. 

  1455. #define bfin_write_DMA32_CURR_ADDR(val) 	bfin_write32(DMA32_CURR_ADDR, val)
    1456. 

  1456. #define bfin_read_DMA32_IRQ_STATUS()		bfin_read32(DMA32_IRQ_STATUS)
    1457. 

  1457. #define bfin_write_DMA32_IRQ_STATUS(val)	bfin_write32(DMA32_IRQ_STATUS, val)
    1458. 

  1458. #define bfin_read_DMA32_CURR_X_COUNT()		bfin_read32(DMA32_CURR_X_COUNT)
    1459. 

  1459. #define bfin_write_DMA32_CURR_X_COUNT(val)	bfin_write32(DMA32_CURR_X_COUNT, val)
    1460. 

  1460. #define bfin_read_DMA32_CURR_Y_COUNT()		bfin_read32(DMA32_CURR_Y_COUNT)
    1461. 

  1461. #define bfin_write_DMA32_CURR_Y_COUNT(val)	bfin_write32(DMA32_CURR_Y_COUNT, val)
    1462. 

  1462. #define bfin_read_DMA32_BWL_COUNT()		bfin_read32(DMA32_BWL_COUNT)
    1463. 

  1463. #define bfin_write_DMA32_BWL_COUNT(val)		bfin_write32(DMA32_BWL_COUNT, val)
    1464. 

  1464. #define bfin_read_DMA32_CURR_BWL_COUNT()	bfin_read32(DMA32_CURR_BWL_COUNT)
    1465. 

  1465. #define bfin_write_DMA32_CURR_BWL_COUNT(val)	bfin_write32(DMA32_CURR_BWL_COUNT, val)
    1466. 

  1466. #define bfin_read_DMA32_BWM_COUNT()		bfin_read32(DMA32_BWM_COUNT)
    1467. 

  1467. #define bfin_write_DMA32_BWM_COUNT(val)		bfin_write32(DMA32_BWM_COUNT, val)
    1468. 

  1468. #define bfin_read_DMA32_CURR_BWM_COUNT()	bfin_read32(DMA32_CURR_BWM_COUNT)
    1469. 

  1469. #define bfin_write_DMA32_CURR_BWM_COUNT(val)	bfin_write32(DMA32_CURR_BWM_COUNT, val)
    1470. 

  1470. 

  1471. /* DMA Channel 33 Registers */
    1472. 

  1472. 

  1473. #define bfin_read_DMA33_NEXT_DESC_PTR() 	bfin_read32(DMA33_NEXT_DESC_PTR)
    1474. 

  1474. #define bfin_write_DMA33_NEXT_DESC_PTR(val) 	bfin_write32(DMA33_NEXT_DESC_PTR, val)
    1475. 

  1475. #define bfin_read_DMA33_START_ADDR() 		bfin_read32(DMA33_START_ADDR)
    1476. 

  1476. #define bfin_write_DMA33_START_ADDR(val) 	bfin_write32(DMA33_START_ADDR, val)
    1477. 

  1477. #define bfin_read_DMA33_CONFIG()		bfin_read32(DMA33_CONFIG)
    1478. 

  1478. #define bfin_write_DMA33_CONFIG(val)		bfin_write32(DMA33_CONFIG, val)
    1479. 

  1479. #define bfin_read_DMA33_X_COUNT()		bfin_read32(DMA33_X_COUNT)
    1480. 

  1480. #define bfin_write_DMA33_X_COUNT(val)		bfin_write32(DMA33_X_COUNT, val)
    1481. 

  1481. #define bfin_read_DMA33_X_MODIFY()		bfin_read32(DMA33_X_MODIFY)
    1482. 

  1482. #define bfin_write_DMA33_X_MODIFY(val) 		bfin_write32(DMA33_X_MODIFY, val)
    1483. 

  1483. #define bfin_read_DMA33_Y_COUNT()		bfin_read32(DMA33_Y_COUNT)
    1484. 

  1484. #define bfin_write_DMA33_Y_COUNT(val)		bfin_write32(DMA33_Y_COUNT, val)
    1485. 

  1485. #define bfin_read_DMA33_Y_MODIFY()		bfin_read32(DMA33_Y_MODIFY)
    1486. 

  1486. #define bfin_write_DMA33_Y_MODIFY(val) 		bfin_write32(DMA33_Y_MODIFY, val)
    1487. 

  1487. #define bfin_read_DMA33_CURR_DESC_PTR() 	bfin_read32(DMA33_CURR_DESC_PTR)
    1488. 

  1488. #define bfin_write_DMA33_CURR_DESC_PTR(val) 	bfin_write32(DMA33_CURR_DESC_PTR, val)
    1489. 

  1489. #define bfin_read_DMA33_PREV_DESC_PTR() 	bfin_read32(DMA33_PREV_DESC_PTR)
    1490. 

  1490. #define bfin_write_DMA33_PREV_DESC_PTR(val) 	bfin_write32(DMA33_PREV_DESC_PTR, val)
    1491. 

  1491. #define bfin_read_DMA33_CURR_ADDR() 		bfin_read32(DMA33_CURR_ADDR)
    1492. 

  1492. #define bfin_write_DMA33_CURR_ADDR(val) 	bfin_write32(DMA33_CURR_ADDR, val)
    1493. 

  1493. #define bfin_read_DMA33_IRQ_STATUS()		bfin_read32(DMA33_IRQ_STATUS)
    1494. 

  1494. #define bfin_write_DMA33_IRQ_STATUS(val)	bfin_write32(DMA33_IRQ_STATUS, val)
    1495. 

  1495. #define bfin_read_DMA33_CURR_X_COUNT()		bfin_read32(DMA33_CURR_X_COUNT)
    1496. 

  1496. #define bfin_write_DMA33_CURR_X_COUNT(val)	bfin_write32(DMA33_CURR_X_COUNT, val)
    1497. 

  1497. #define bfin_read_DMA33_CURR_Y_COUNT()		bfin_read32(DMA33_CURR_Y_COUNT)
    1498. 

  1498. #define bfin_write_DMA33_CURR_Y_COUNT(val)	bfin_write32(DMA33_CURR_Y_COUNT, val)
    1499. 

  1499. #define bfin_read_DMA33_BWL_COUNT()		bfin_read32(DMA33_BWL_COUNT)
    1500. 

  1500. #define bfin_write_DMA33_BWL_COUNT(val)		bfin_write32(DMA33_BWL_COUNT, val)
    1501. 

  1501. #define bfin_read_DMA33_CURR_BWL_COUNT()	bfin_read32(DMA33_CURR_BWL_COUNT)
    1502. 

  1502. #define bfin_write_DMA33_CURR_BWL_COUNT(val)	bfin_write32(DMA33_CURR_BWL_COUNT, val)
    1503. 

  1503. #define bfin_read_DMA33_BWM_COUNT()		bfin_read32(DMA33_BWM_COUNT)
    1504. 

  1504. #define bfin_write_DMA33_BWM_COUNT(val)		bfin_write32(DMA33_BWM_COUNT, val)
    1505. 

  1505. #define bfin_read_DMA33_CURR_BWM_COUNT()	bfin_read32(DMA33_CURR_BWM_COUNT)
    1506. 

  1506. #define bfin_write_DMA33_CURR_BWM_COUNT(val)	bfin_write32(DMA33_CURR_BWM_COUNT, val)
    1507. 

  1507. 

  1508. /* DMA Channel 34 Registers */
    1509. 

  1509. 

  1510. #define bfin_read_DMA34_NEXT_DESC_PTR() 	bfin_read32(DMA34_NEXT_DESC_PTR)
    1511. 

  1511. #define bfin_write_DMA34_NEXT_DESC_PTR(val) 	bfin_write32(DMA34_NEXT_DESC_PTR, val)
    1512. 

  1512. #define bfin_read_DMA34_START_ADDR() 		bfin_read32(DMA34_START_ADDR)
    1513. 

  1513. #define bfin_write_DMA34_START_ADDR(val) 	bfin_write32(DMA34_START_ADDR, val)
    1514. 

  1514. #define bfin_read_DMA34_CONFIG()		bfin_read32(DMA34_CONFIG)
    1515. 

  1515. #define bfin_write_DMA34_CONFIG(val)		bfin_write32(DMA34_CONFIG, val)
    1516. 

  1516. #define bfin_read_DMA34_X_COUNT()		bfin_read32(DMA34_X_COUNT)
    1517. 

  1517. #define bfin_write_DMA34_X_COUNT(val)		bfin_write32(DMA34_X_COUNT, val)
    1518. 

  1518. #define bfin_read_DMA34_X_MODIFY()		bfin_read32(DMA34_X_MODIFY)
    1519. 

  1519. #define bfin_write_DMA34_X_MODIFY(val) 		bfin_write32(DMA34_X_MODIFY, val)
    1520. 

  1520. #define bfin_read_DMA34_Y_COUNT()		bfin_read32(DMA34_Y_COUNT)
    1521. 

  1521. #define bfin_write_DMA34_Y_COUNT(val)		bfin_write32(DMA34_Y_COUNT, val)
    1522. 

  1522. #define bfin_read_DMA34_Y_MODIFY()		bfin_read32(DMA34_Y_MODIFY)
    1523. 

  1523. #define bfin_write_DMA34_Y_MODIFY(val) 		bfin_write32(DMA34_Y_MODIFY, val)
    1524. 

  1524. #define bfin_read_DMA34_CURR_DESC_PTR() 	bfin_read32(DMA34_CURR_DESC_PTR)
    1525. 

  1525. #define bfin_write_DMA34_CURR_DESC_PTR(val) 	bfin_write32(DMA34_CURR_DESC_PTR, val)
    1526. 

  1526. #define bfin_read_DMA34_PREV_DESC_PTR() 	bfin_read32(DMA34_PREV_DESC_PTR)
    1527. 

  1527. #define bfin_write_DMA34_PREV_DESC_PTR(val) 	bfin_write32(DMA34_PREV_DESC_PTR, val)
    1528. 

  1528. #define bfin_read_DMA34_CURR_ADDR() 		bfin_read32(DMA34_CURR_ADDR)
    1529. 

  1529. #define bfin_write_DMA34_CURR_ADDR(val) 	bfin_write32(DMA34_CURR_ADDR, val)
    1530. 

  1530. #define bfin_read_DMA34_IRQ_STATUS()		bfin_read32(DMA34_IRQ_STATUS)
    1531. 

  1531. #define bfin_write_DMA34_IRQ_STATUS(val)	bfin_write32(DMA34_IRQ_STATUS, val)
    1532. 

  1532. #define bfin_read_DMA34_CURR_X_COUNT()		bfin_read32(DMA34_CURR_X_COUNT)
    1533. 

  1533. #define bfin_write_DMA34_CURR_X_COUNT(val)	bfin_write32(DMA34_CURR_X_COUNT, val)
    1534. 

  1534. #define bfin_read_DMA34_CURR_Y_COUNT()		bfin_read32(DMA34_CURR_Y_COUNT)
    1535. 

  1535. #define bfin_write_DMA34_CURR_Y_COUNT(val)	bfin_write32(DMA34_CURR_Y_COUNT, val)
    1536. 

  1536. #define bfin_read_DMA34_BWL_COUNT()		bfin_read32(DMA34_BWL_COUNT)
    1537. 

  1537. #define bfin_write_DMA34_BWL_COUNT(val)		bfin_write32(DMA34_BWL_COUNT, val)
    1538. 

  1538. #define bfin_read_DMA34_CURR_BWL_COUNT()	bfin_read32(DMA34_CURR_BWL_COUNT)
    1539. 

  1539. #define bfin_write_DMA34_CURR_BWL_COUNT(val)	bfin_write32(DMA34_CURR_BWL_COUNT, val)
    1540. 

  1540. #define bfin_read_DMA34_BWM_COUNT()		bfin_read32(DMA34_BWM_COUNT)
    1541. 

  1541. #define bfin_write_DMA34_BWM_COUNT(val)		bfin_write32(DMA34_BWM_COUNT, val)
    1542. 

  1542. #define bfin_read_DMA34_CURR_BWM_COUNT()	bfin_read32(DMA34_CURR_BWM_COUNT)
    1543. 

  1543. #define bfin_write_DMA34_CURR_BWM_COUNT(val)	bfin_write32(DMA34_CURR_BWM_COUNT, val)
    1544. 

  1544. 

  1545. /* DMA Channel 35 Registers */
    1546. 

  1546. 

  1547. #define bfin_read_DMA35_NEXT_DESC_PTR() 	bfin_read32(DMA35_NEXT_DESC_PTR)
    1548. 

  1548. #define bfin_write_DMA35_NEXT_DESC_PTR(val) 	bfin_write32(DMA35_NEXT_DESC_PTR, val)
    1549. 

  1549. #define bfin_read_DMA35_START_ADDR() 		bfin_read32(DMA35_START_ADDR)
    1550. 

  1550. #define bfin_write_DMA35_START_ADDR(val) 	bfin_write32(DMA35_START_ADDR, val)
    1551. 

  1551. #define bfin_read_DMA35_CONFIG()		bfin_read32(DMA35_CONFIG)
    1552. 

  1552. #define bfin_write_DMA35_CONFIG(val)		bfin_write32(DMA35_CONFIG, val)
    1553. 

  1553. #define bfin_read_DMA35_X_COUNT()		bfin_read32(DMA35_X_COUNT)
    1554. 

  1554. #define bfin_write_DMA35_X_COUNT(val)		bfin_write32(DMA35_X_COUNT, val)
    1555. 

  1555. #define bfin_read_DMA35_X_MODIFY()		bfin_read32(DMA35_X_MODIFY)
    1556. 

  1556. #define bfin_write_DMA35_X_MODIFY(val) 		bfin_write32(DMA35_X_MODIFY, val)
    1557. 

  1557. #define bfin_read_DMA35_Y_COUNT()		bfin_read32(DMA35_Y_COUNT)
    1558. 

  1558. #define bfin_write_DMA35_Y_COUNT(val)		bfin_write32(DMA35_Y_COUNT, val)
    1559. 

  1559. #define bfin_read_DMA35_Y_MODIFY()		bfin_read32(DMA35_Y_MODIFY)
    1560. 

  1560. #define bfin_write_DMA35_Y_MODIFY(val) 		bfin_write32(DMA35_Y_MODIFY, val)
    1561. 

  1561. #define bfin_read_DMA35_CURR_DESC_PTR() 	bfin_read32(DMA35_CURR_DESC_PTR)
    1562. 

  1562. #define bfin_write_DMA35_CURR_DESC_PTR(val) 	bfin_write32(DMA35_CURR_DESC_PTR, val)
    1563. 

  1563. #define bfin_read_DMA35_PREV_DESC_PTR() 	bfin_read32(DMA35_PREV_DESC_PTR)
    1564. 

  1564. #define bfin_write_DMA35_PREV_DESC_PTR(val) 	bfin_write32(DMA35_PREV_DESC_PTR, val)
    1565. 

  1565. #define bfin_read_DMA35_CURR_ADDR() 		bfin_read32(DMA35_CURR_ADDR)
    1566. 

  1566. #define bfin_write_DMA35_CURR_ADDR(val) 	bfin_write32(DMA35_CURR_ADDR, val)
    1567. 

  1567. #define bfin_read_DMA35_IRQ_STATUS()		bfin_read32(DMA35_IRQ_STATUS)
    1568. 

  1568. #define bfin_write_DMA35_IRQ_STATUS(val)	bfin_write32(DMA35_IRQ_STATUS, val)
    1569. 

  1569. #define bfin_read_DMA35_CURR_X_COUNT()		bfin_read32(DMA35_CURR_X_COUNT)
    1570. 

  1570. #define bfin_write_DMA35_CURR_X_COUNT(val)	bfin_write32(DMA35_CURR_X_COUNT, val)
    1571. 

  1571. #define bfin_read_DMA35_CURR_Y_COUNT()		bfin_read32(DMA35_CURR_Y_COUNT)
    1572. 

  1572. #define bfin_write_DMA35_CURR_Y_COUNT(val)	bfin_write32(DMA35_CURR_Y_COUNT, val)
    1573. 

  1573. #define bfin_read_DMA35_BWL_COUNT()		bfin_read32(DMA35_BWL_COUNT)
    1574. 

  1574. #define bfin_write_DMA35_BWL_COUNT(val)		bfin_write32(DMA35_BWL_COUNT, val)
    1575. 

  1575. #define bfin_read_DMA35_CURR_BWL_COUNT()	bfin_read32(DMA35_CURR_BWL_COUNT)
    1576. 

  1576. #define bfin_write_DMA35_CURR_BWL_COUNT(val)	bfin_write32(DMA35_CURR_BWL_COUNT, val)
    1577. 

  1577. #define bfin_read_DMA35_BWM_COUNT()		bfin_read32(DMA35_BWM_COUNT)
    1578. 

  1578. #define bfin_write_DMA35_BWM_COUNT(val)		bfin_write32(DMA35_BWM_COUNT, val)
    1579. 

  1579. #define bfin_read_DMA35_CURR_BWM_COUNT()	bfin_read32(DMA35_CURR_BWM_COUNT)
    1580. 

  1580. #define bfin_write_DMA35_CURR_BWM_COUNT(val)	bfin_write32(DMA35_CURR_BWM_COUNT, val)
    1581. 

  1581. 

  1582. /* DMA Channel 36 Registers */
    1583. 

  1583. 

  1584. #define bfin_read_DMA36_NEXT_DESC_PTR() 	bfin_read32(DMA36_NEXT_DESC_PTR)
    1585. 

  1585. #define bfin_write_DMA36_NEXT_DESC_PTR(val) 	bfin_write32(DMA36_NEXT_DESC_PTR, val)
    1586. 

  1586. #define bfin_read_DMA36_START_ADDR() 		bfin_read32(DMA36_START_ADDR)
    1587. 

  1587. #define bfin_write_DMA36_START_ADDR(val) 	bfin_write32(DMA36_START_ADDR, val)
    1588. 

  1588. #define bfin_read_DMA36_CONFIG()		bfin_read32(DMA36_CONFIG)
    1589. 

  1589. #define bfin_write_DMA36_CONFIG(val)		bfin_write32(DMA36_CONFIG, val)
    1590. 

  1590. #define bfin_read_DMA36_X_COUNT()		bfin_read32(DMA36_X_COUNT)
    1591. 

  1591. #define bfin_write_DMA36_X_COUNT(val)		bfin_write32(DMA36_X_COUNT, val)
    1592. 

  1592. #define bfin_read_DMA36_X_MODIFY()		bfin_read32(DMA36_X_MODIFY)
    1593. 

  1593. #define bfin_write_DMA36_X_MODIFY(val) 		bfin_write32(DMA36_X_MODIFY, val)
    1594. 

  1594. #define bfin_read_DMA36_Y_COUNT()		bfin_read32(DMA36_Y_COUNT)
    1595. 

  1595. #define bfin_write_DMA36_Y_COUNT(val)		bfin_write32(DMA36_Y_COUNT, val)
    1596. 

  1596. #define bfin_read_DMA36_Y_MODIFY()		bfin_read32(DMA36_Y_MODIFY)
    1597. 

  1597. #define bfin_write_DMA36_Y_MODIFY(val) 		bfin_write32(DMA36_Y_MODIFY, val)
    1598. 

  1598. #define bfin_read_DMA36_CURR_DESC_PTR() 	bfin_read32(DMA36_CURR_DESC_PTR)
    1599. 

  1599. #define bfin_write_DMA36_CURR_DESC_PTR(val) 	bfin_write32(DMA36_CURR_DESC_PTR, val)
    1600. 

  1600. #define bfin_read_DMA36_PREV_DESC_PTR() 	bfin_read32(DMA36_PREV_DESC_PTR)
    1601. 

  1601. #define bfin_write_DMA36_PREV_DESC_PTR(val) 	bfin_write32(DMA36_PREV_DESC_PTR, val)
    1602. 

  1602. #define bfin_read_DMA36_CURR_ADDR() 		bfin_read32(DMA36_CURR_ADDR)
    1603. 

  1603. #define bfin_write_DMA36_CURR_ADDR(val) 	bfin_write32(DMA36_CURR_ADDR, val)
    1604. 

  1604. #define bfin_read_DMA36_IRQ_STATUS()		bfin_read32(DMA36_IRQ_STATUS)
    1605. 

  1605. #define bfin_write_DMA36_IRQ_STATUS(val)	bfin_write32(DMA36_IRQ_STATUS, val)
    1606. 

  1606. #define bfin_read_DMA36_CURR_X_COUNT()		bfin_read32(DMA36_CURR_X_COUNT)
    1607. 

  1607. #define bfin_write_DMA36_CURR_X_COUNT(val)	bfin_write32(DMA36_CURR_X_COUNT, val)
    1608. 

  1608. #define bfin_read_DMA36_CURR_Y_COUNT()		bfin_read32(DMA36_CURR_Y_COUNT)
    1609. 

  1609. #define bfin_write_DMA36_CURR_Y_COUNT(val)	bfin_write32(DMA36_CURR_Y_COUNT, val)
    1610. 

  1610. #define bfin_read_DMA36_BWL_COUNT()		bfin_read32(DMA36_BWL_COUNT)
    1611. 

  1611. #define bfin_write_DMA36_BWL_COUNT(val)		bfin_write32(DMA36_BWL_COUNT, val)
    1612. 

  1612. #define bfin_read_DMA36_CURR_BWL_COUNT()	bfin_read32(DMA36_CURR_BWL_COUNT)
    1613. 

  1613. #define bfin_write_DMA36_CURR_BWL_COUNT(val)	bfin_write32(DMA36_CURR_BWL_COUNT, val)
    1614. 

  1614. #define bfin_read_DMA36_BWM_COUNT()		bfin_read32(DMA36_BWM_COUNT)
    1615. 

  1615. #define bfin_write_DMA36_BWM_COUNT(val)		bfin_write32(DMA36_BWM_COUNT, val)
    1616. 

  1616. #define bfin_read_DMA36_CURR_BWM_COUNT()	bfin_read32(DMA36_CURR_BWM_COUNT)
    1617. 

  1617. #define bfin_write_DMA36_CURR_BWM_COUNT(val)	bfin_write32(DMA36_CURR_BWM_COUNT, val)
    1618. 

  1618. 

  1619. /* DMA Channel 37 Registers */
    1620. 

  1620. 

  1621. #define bfin_read_DMA37_NEXT_DESC_PTR() 	bfin_read32(DMA37_NEXT_DESC_PTR)
    1622. 

  1622. #define bfin_write_DMA37_NEXT_DESC_PTR(val) 	bfin_write32(DMA37_NEXT_DESC_PTR, val)
    1623. 

  1623. #define bfin_read_DMA37_START_ADDR() 		bfin_read32(DMA37_START_ADDR)
    1624. 

  1624. #define bfin_write_DMA37_START_ADDR(val) 	bfin_write32(DMA37_START_ADDR, val)
    1625. 

  1625. #define bfin_read_DMA37_CONFIG()		bfin_read32(DMA37_CONFIG)
    1626. 

  1626. #define bfin_write_DMA37_CONFIG(val)		bfin_write32(DMA37_CONFIG, val)
    1627. 

  1627. #define bfin_read_DMA37_X_COUNT()		bfin_read32(DMA37_X_COUNT)
    1628. 

  1628. #define bfin_write_DMA37_X_COUNT(val)		bfin_write32(DMA37_X_COUNT, val)
    1629. 

  1629. #define bfin_read_DMA37_X_MODIFY()		bfin_read32(DMA37_X_MODIFY)
    1630. 

  1630. #define bfin_write_DMA37_X_MODIFY(val) 		bfin_write32(DMA37_X_MODIFY, val)
    1631. 

  1631. #define bfin_read_DMA37_Y_COUNT()		bfin_read32(DMA37_Y_COUNT)
    1632. 

  1632. #define bfin_write_DMA37_Y_COUNT(val)		bfin_write32(DMA37_Y_COUNT, val)
    1633. 

  1633. #define bfin_read_DMA37_Y_MODIFY()		bfin_read32(DMA37_Y_MODIFY)
    1634. 

  1634. #define bfin_write_DMA37_Y_MODIFY(val) 		bfin_write32(DMA37_Y_MODIFY, val)
    1635. 

  1635. #define bfin_read_DMA37_CURR_DESC_PTR() 	bfin_read32(DMA37_CURR_DESC_PTR)
    1636. 

  1636. #define bfin_write_DMA37_CURR_DESC_PTR(val) 	bfin_write32(DMA37_CURR_DESC_PTR, val)
    1637. 

  1637. #define bfin_read_DMA37_PREV_DESC_PTR() 	bfin_read32(DMA37_PREV_DESC_PTR)
    1638. 

  1638. #define bfin_write_DMA37_PREV_DESC_PTR(val) 	bfin_write32(DMA37_PREV_DESC_PTR, val)
    1639. 

  1639. #define bfin_read_DMA37_CURR_ADDR() 		bfin_read32(DMA37_CURR_ADDR)
    1640. 

  1640. #define bfin_write_DMA37_CURR_ADDR(val) 	bfin_write32(DMA37_CURR_ADDR, val)
    1641. 

  1641. #define bfin_read_DMA37_IRQ_STATUS()		bfin_read32(DMA37_IRQ_STATUS)
    1642. 

  1642. #define bfin_write_DMA37_IRQ_STATUS(val)	bfin_write32(DMA37_IRQ_STATUS, val)
    1643. 

  1643. #define bfin_read_DMA37_CURR_X_COUNT()		bfin_read32(DMA37_CURR_X_COUNT)
    1644. 

  1644. #define bfin_write_DMA37_CURR_X_COUNT(val)	bfin_write32(DMA37_CURR_X_COUNT, val)
    1645. 

  1645. #define bfin_read_DMA37_CURR_Y_COUNT()		bfin_read32(DMA37_CURR_Y_COUNT)
    1646. 

  1646. #define bfin_write_DMA37_CURR_Y_COUNT(val)	bfin_write32(DMA37_CURR_Y_COUNT, val)
    1647. 

  1647. #define bfin_read_DMA37_BWL_COUNT()		bfin_read32(DMA37_BWL_COUNT)
    1648. 

  1648. #define bfin_write_DMA37_BWL_COUNT(val)		bfin_write32(DMA37_BWL_COUNT, val)
    1649. 

  1649. #define bfin_read_DMA37_CURR_BWL_COUNT()	bfin_read32(DMA37_CURR_BWL_COUNT)
    1650. 

  1650. #define bfin_write_DMA37_CURR_BWL_COUNT(val)	bfin_write32(DMA37_CURR_BWL_COUNT, val)
    1651. 

  1651. #define bfin_read_DMA37_BWM_COUNT()		bfin_read32(DMA37_BWM_COUNT)
    1652. 

  1652. #define bfin_write_DMA37_BWM_COUNT(val)		bfin_write32(DMA37_BWM_COUNT, val)
    1653. 

  1653. #define bfin_read_DMA37_CURR_BWM_COUNT()	bfin_read32(DMA37_CURR_BWM_COUNT)
    1654. 

  1654. #define bfin_write_DMA37_CURR_BWM_COUNT(val)	bfin_write32(DMA37_CURR_BWM_COUNT, val)
    1655. 

  1655. 

  1656. /* DMA Channel 38 Registers */
    1657. 

  1657. 

  1658. #define bfin_read_DMA38_NEXT_DESC_PTR() 	bfin_read32(DMA38_NEXT_DESC_PTR)
    1659. 

  1659. #define bfin_write_DMA38_NEXT_DESC_PTR(val) 	bfin_write32(DMA38_NEXT_DESC_PTR, val)
    1660. 

  1660. #define bfin_read_DMA38_START_ADDR() 		bfin_read32(DMA38_START_ADDR)
    1661. 

  1661. #define bfin_write_DMA38_START_ADDR(val) 	bfin_write32(DMA38_START_ADDR, val)
    1662. 

  1662. #define bfin_read_DMA38_CONFIG()		bfin_read32(DMA38_CONFIG)
    1663. 

  1663. #define bfin_write_DMA38_CONFIG(val)		bfin_write32(DMA38_CONFIG, val)
    1664. 

  1664. #define bfin_read_DMA38_X_COUNT()		bfin_read32(DMA38_X_COUNT)
    1665. 

  1665. #define bfin_write_DMA38_X_COUNT(val)		bfin_write32(DMA38_X_COUNT, val)
    1666. 

  1666. #define bfin_read_DMA38_X_MODIFY()		bfin_read32(DMA38_X_MODIFY)
    1667. 

  1667. #define bfin_write_DMA38_X_MODIFY(val) 		bfin_write32(DMA38_X_MODIFY, val)
    1668. 

  1668. #define bfin_read_DMA38_Y_COUNT()		bfin_read32(DMA38_Y_COUNT)
    1669. 

  1669. #define bfin_write_DMA38_Y_COUNT(val)		bfin_write32(DMA38_Y_COUNT, val)
    1670. 

  1670. #define bfin_read_DMA38_Y_MODIFY()		bfin_read32(DMA38_Y_MODIFY)
    1671. 

  1671. #define bfin_write_DMA38_Y_MODIFY(val) 		bfin_write32(DMA38_Y_MODIFY, val)
    1672. 

  1672. #define bfin_read_DMA38_CURR_DESC_PTR() 	bfin_read32(DMA38_CURR_DESC_PTR)
    1673. 

  1673. #define bfin_write_DMA38_CURR_DESC_PTR(val) 	bfin_write32(DMA38_CURR_DESC_PTR, val)
    1674. 

  1674. #define bfin_read_DMA38_PREV_DESC_PTR() 	bfin_read32(DMA38_PREV_DESC_PTR)
    1675. 

  1675. #define bfin_write_DMA38_PREV_DESC_PTR(val) 	bfin_write32(DMA38_PREV_DESC_PTR, val)
    1676. 

  1676. #define bfin_read_DMA38_CURR_ADDR() 		bfin_read32(DMA38_CURR_ADDR)
    1677. 

  1677. #define bfin_write_DMA38_CURR_ADDR(val) 	bfin_write32(DMA38_CURR_ADDR, val)
    1678. 

  1678. #define bfin_read_DMA38_IRQ_STATUS()		bfin_read32(DMA38_IRQ_STATUS)
    1679. 

  1679. #define bfin_write_DMA38_IRQ_STATUS(val)	bfin_write32(DMA38_IRQ_STATUS, val)
    1680. 

  1680. #define bfin_read_DMA38_CURR_X_COUNT()		bfin_read32(DMA38_CURR_X_COUNT)
    1681. 

  1681. #define bfin_write_DMA38_CURR_X_COUNT(val)	bfin_write32(DMA38_CURR_X_COUNT, val)
    1682. 

  1682. #define bfin_read_DMA38_CURR_Y_COUNT()		bfin_read32(DMA38_CURR_Y_COUNT)
    1683. 

  1683. #define bfin_write_DMA38_CURR_Y_COUNT(val)	bfin_write32(DMA38_CURR_Y_COUNT, val)
    1684. 

  1684. #define bfin_read_DMA38_BWL_COUNT()		bfin_read32(DMA38_BWL_COUNT)
    1685. 

  1685. #define bfin_write_DMA38_BWL_COUNT(val)		bfin_write32(DMA38_BWL_COUNT, val)
    1686. 

  1686. #define bfin_read_DMA38_CURR_BWL_COUNT()	bfin_read32(DMA38_CURR_BWL_COUNT)
    1687. 

  1687. #define bfin_write_DMA38_CURR_BWL_COUNT(val)	bfin_write32(DMA38_CURR_BWL_COUNT, val)
    1688. 

  1688. #define bfin_read_DMA38_BWM_COUNT()		bfin_read32(DMA38_BWM_COUNT)
    1689. 

  1689. #define bfin_write_DMA38_BWM_COUNT(val)		bfin_write32(DMA38_BWM_COUNT, val)
    1690. 

  1690. #define bfin_read_DMA38_CURR_BWM_COUNT()	bfin_read32(DMA38_CURR_BWM_COUNT)
    1691. 

  1691. #define bfin_write_DMA38_CURR_BWM_COUNT(val)	bfin_write32(DMA38_CURR_BWM_COUNT, val)
    1692. 

  1692. 

  1693. /* DMA Channel 39 Registers */
    1694. 

  1694. 

  1695. #define bfin_read_DMA39_NEXT_DESC_PTR() 	bfin_read32(DMA39_NEXT_DESC_PTR)
    1696. 

  1696. #define bfin_write_DMA39_NEXT_DESC_PTR(val) 	bfin_write32(DMA39_NEXT_DESC_PTR, val)
    1697. 

  1697. #define bfin_read_DMA39_START_ADDR() 		bfin_read32(DMA39_START_ADDR)
    1698. 

  1698. #define bfin_write_DMA39_START_ADDR(val) 	bfin_write32(DMA39_START_ADDR, val)
    1699. 

  1699. #define bfin_read_DMA39_CONFIG()		bfin_read32(DMA39_CONFIG)
    1700. 

  1700. #define bfin_write_DMA39_CONFIG(val)		bfin_write32(DMA39_CONFIG, val)
    1701. 

  1701. #define bfin_read_DMA39_X_COUNT()		bfin_read32(DMA39_X_COUNT)
    1702. 

  1702. #define bfin_write_DMA39_X_COUNT(val)		bfin_write32(DMA39_X_COUNT, val)
    1703. 

  1703. #define bfin_read_DMA39_X_MODIFY()		bfin_read32(DMA39_X_MODIFY)
    1704. 

  1704. #define bfin_write_DMA39_X_MODIFY(val) 		bfin_write32(DMA39_X_MODIFY, val)
    1705. 

  1705. #define bfin_read_DMA39_Y_COUNT()		bfin_read32(DMA39_Y_COUNT)
    1706. 

  1706. #define bfin_write_DMA39_Y_COUNT(val)		bfin_write32(DMA39_Y_COUNT, val)
    1707. 

  1707. #define bfin_read_DMA39_Y_MODIFY()		bfin_read32(DMA39_Y_MODIFY)
    1708. 

  1708. #define bfin_write_DMA39_Y_MODIFY(val) 		bfin_write32(DMA39_Y_MODIFY, val)
    1709. 

  1709. #define bfin_read_DMA39_CURR_DESC_PTR() 	bfin_read32(DMA39_CURR_DESC_PTR)
    1710. 

  1710. #define bfin_write_DMA39_CURR_DESC_PTR(val) 	bfin_write32(DMA39_CURR_DESC_PTR, val)
    1711. 

  1711. #define bfin_read_DMA39_PREV_DESC_PTR() 	bfin_read32(DMA39_PREV_DESC_PTR)
    1712. 

  1712. #define bfin_write_DMA39_PREV_DESC_PTR(val) 	bfin_write32(DMA39_PREV_DESC_PTR, val)
    1713. 

  1713. #define bfin_read_DMA39_CURR_ADDR() 		bfin_read32(DMA39_CURR_ADDR)
    1714. 

  1714. #define bfin_write_DMA39_CURR_ADDR(val) 	bfin_write32(DMA39_CURR_ADDR, val)
    1715. 

  1715. #define bfin_read_DMA39_IRQ_STATUS()		bfin_read32(DMA39_IRQ_STATUS)
    1716. 

  1716. #define bfin_write_DMA39_IRQ_STATUS(val)	bfin_write32(DMA39_IRQ_STATUS, val)
    1717. 

  1717. #define bfin_read_DMA39_CURR_X_COUNT()		bfin_read32(DMA39_CURR_X_COUNT)
    1718. 

  1718. #define bfin_write_DMA39_CURR_X_COUNT(val)	bfin_write32(DMA39_CURR_X_COUNT, val)
    1719. 

  1719. #define bfin_read_DMA39_CURR_Y_COUNT()		bfin_read32(DMA39_CURR_Y_COUNT)
    1720. 

  1720. #define bfin_write_DMA39_CURR_Y_COUNT(val)	bfin_write32(DMA39_CURR_Y_COUNT, val)
    1721. 

  1721. #define bfin_read_DMA39_BWL_COUNT()		bfin_read32(DMA39_BWL_COUNT)
    1722. 

  1722. #define bfin_write_DMA39_BWL_COUNT(val)		bfin_write32(DMA39_BWL_COUNT, val)
    1723. 

  1723. #define bfin_read_DMA39_CURR_BWL_COUNT()	bfin_read32(DMA39_CURR_BWL_COUNT)
    1724. 

  1724. #define bfin_write_DMA39_CURR_BWL_COUNT(val)	bfin_write32(DMA39_CURR_BWL_COUNT, val)
    1725. 

  1725. #define bfin_read_DMA39_BWM_COUNT()		bfin_read32(DMA39_BWM_COUNT)
    1726. 

  1726. #define bfin_write_DMA39_BWM_COUNT(val)		bfin_write32(DMA39_BWM_COUNT, val)
    1727. 

  1727. #define bfin_read_DMA39_CURR_BWM_COUNT()	bfin_read32(DMA39_CURR_BWM_COUNT)
    1728. 

  1728. #define bfin_write_DMA39_CURR_BWM_COUNT(val)	bfin_write32(DMA39_CURR_BWM_COUNT, val)
    1729. 

  1729. 

  1730. /* DMA Channel 40 Registers */
    1731. 

  1731. 

  1732. #define bfin_read_DMA40_NEXT_DESC_PTR() 	bfin_read32(DMA40_NEXT_DESC_PTR)
    1733. 

  1733. #define bfin_write_DMA40_NEXT_DESC_PTR(val) 	bfin_write32(DMA40_NEXT_DESC_PTR, val)
    1734. 

  1734. #define bfin_read_DMA40_START_ADDR() 		bfin_read32(DMA40_START_ADDR)
    1735. 

  1735. #define bfin_write_DMA40_START_ADDR(val) 	bfin_write32(DMA40_START_ADDR, val)
    1736. 

  1736. #define bfin_read_DMA40_CONFIG()		bfin_read32(DMA40_CONFIG)
    1737. 

  1737. #define bfin_write_DMA40_CONFIG(val)		bfin_write32(DMA40_CONFIG, val)
    1738. 

  1738. #define bfin_read_DMA40_X_COUNT()		bfin_read32(DMA40_X_COUNT)
    1739. 

  1739. #define bfin_write_DMA40_X_COUNT(val)		bfin_write32(DMA40_X_COUNT, val)
    1740. 

  1740. #define bfin_read_DMA40_X_MODIFY()		bfin_read32(DMA40_X_MODIFY)
    1741. 

  1741. #define bfin_write_DMA40_X_MODIFY(val) 		bfin_write32(DMA40_X_MODIFY, val)
    1742. 

  1742. #define bfin_read_DMA40_Y_COUNT()		bfin_read32(DMA40_Y_COUNT)
    1743. 

  1743. #define bfin_write_DMA40_Y_COUNT(val)		bfin_write32(DMA40_Y_COUNT, val)
    1744. 

  1744. #define bfin_read_DMA40_Y_MODIFY()		bfin_read32(DMA40_Y_MODIFY)
    1745. 

  1745. #define bfin_write_DMA40_Y_MODIFY(val) 		bfin_write32(DMA40_Y_MODIFY, val)
    1746. 

  1746. #define bfin_read_DMA40_CURR_DESC_PTR() 	bfin_read32(DMA40_CURR_DESC_PTR)
    1747. 

  1747. #define bfin_write_DMA40_CURR_DESC_PTR(val) 	bfin_write32(DMA40_CURR_DESC_PTR, val)
    1748. 

  1748. #define bfin_read_DMA40_PREV_DESC_PTR() 	bfin_read32(DMA40_PREV_DESC_PTR)
    1749. 

  1749. #define bfin_write_DMA40_PREV_DESC_PTR(val) 	bfin_write32(DMA40_PREV_DESC_PTR, val)
    1750. 

  1750. #define bfin_read_DMA40_CURR_ADDR() 		bfin_read32(DMA40_CURR_ADDR)
    1751. 

  1751. #define bfin_write_DMA40_CURR_ADDR(val) 	bfin_write32(DMA40_CURR_ADDR, val)
    1752. 

  1752. #define bfin_read_DMA40_IRQ_STATUS()		bfin_read32(DMA40_IRQ_STATUS)
    1753. 

  1753. #define bfin_write_DMA40_IRQ_STATUS(val)	bfin_write32(DMA40_IRQ_STATUS, val)
    1754. 

  1754. #define bfin_read_DMA40_CURR_X_COUNT()		bfin_read32(DMA40_CURR_X_COUNT)
    1755. 

  1755. #define bfin_write_DMA40_CURR_X_COUNT(val)	bfin_write32(DMA40_CURR_X_COUNT, val)
    1756. 

  1756. #define bfin_read_DMA40_CURR_Y_COUNT()		bfin_read32(DMA40_CURR_Y_COUNT)
    1757. 

  1757. #define bfin_write_DMA40_CURR_Y_COUNT(val)	bfin_write32(DMA40_CURR_Y_COUNT, val)
    1758. 

  1758. #define bfin_read_DMA40_BWL_COUNT()		bfin_read32(DMA40_BWL_COUNT)
    1759. 

  1759. #define bfin_write_DMA40_BWL_COUNT(val)		bfin_write32(DMA40_BWL_COUNT, val)
    1760. 

  1760. #define bfin_read_DMA40_CURR_BWL_COUNT()	bfin_read32(DMA40_CURR_BWL_COUNT)
    1761. 

  1761. #define bfin_write_DMA40_CURR_BWL_COUNT(val)	bfin_write32(DMA40_CURR_BWL_COUNT, val)
    1762. 

  1762. #define bfin_read_DMA40_BWM_COUNT()		bfin_read32(DMA40_BWM_COUNT)
    1763. 

  1763. #define bfin_write_DMA40_BWM_COUNT(val)		bfin_write32(DMA40_BWM_COUNT, val)
    1764. 

  1764. #define bfin_read_DMA40_CURR_BWM_COUNT()	bfin_read32(DMA40_CURR_BWM_COUNT)
    1765. 

  1765. #define bfin_write_DMA40_CURR_BWM_COUNT(val)	bfin_write32(DMA40_CURR_BWM_COUNT, val)
    1766. 

  1766. 

  1767. /* DMA Channel 41 Registers */
    1768. 

  1768. 

  1769. #define bfin_read_DMA41_NEXT_DESC_PTR() 	bfin_read32(DMA41_NEXT_DESC_PTR)
    1770. 

  1770. #define bfin_write_DMA41_NEXT_DESC_PTR(val) 	bfin_write32(DMA41_NEXT_DESC_PTR, val)
    1771. 

  1771. #define bfin_read_DMA41_START_ADDR() 		bfin_read32(DMA41_START_ADDR)
    1772. 

  1772. #define bfin_write_DMA41_START_ADDR(val) 	bfin_write32(DMA41_START_ADDR, val)
    1773. 

  1773. #define bfin_read_DMA41_CONFIG()		bfin_read32(DMA41_CONFIG)
    1774. 

  1774. #define bfin_write_DMA41_CONFIG(val)		bfin_write32(DMA41_CONFIG, val)
    1775. 

  1775. #define bfin_read_DMA41_X_COUNT()		bfin_read32(DMA41_X_COUNT)
    1776. 

  1776. #define bfin_write_DMA41_X_COUNT(val)		bfin_write32(DMA41_X_COUNT, val)
    1777. 

  1777. #define bfin_read_DMA41_X_MODIFY()		bfin_read32(DMA41_X_MODIFY)
    1778. 

  1778. #define bfin_write_DMA41_X_MODIFY(val) 		bfin_write32(DMA41_X_MODIFY, val)
    1779. 

  1779. #define bfin_read_DMA41_Y_COUNT()		bfin_read32(DMA41_Y_COUNT)
    1780. 

  1780. #define bfin_write_DMA41_Y_COUNT(val)		bfin_write32(DMA41_Y_COUNT, val)
    1781. 

  1781. #define bfin_read_DMA41_Y_MODIFY()		bfin_read32(DMA41_Y_MODIFY)
    1782. 

  1782. #define bfin_write_DMA41_Y_MODIFY(val) 		bfin_write32(DMA41_Y_MODIFY, val)
    1783. 

  1783. #define bfin_read_DMA41_CURR_DESC_PTR() 	bfin_read32(DMA41_CURR_DESC_PTR)
    1784. 

  1784. #define bfin_write_DMA41_CURR_DESC_PTR(val) 	bfin_write32(DMA41_CURR_DESC_PTR, val)
    1785. 

  1785. #define bfin_read_DMA41_PREV_DESC_PTR() 	bfin_read32(DMA41_PREV_DESC_PTR)
    1786. 

  1786. #define bfin_write_DMA41_PREV_DESC_PTR(val) 	bfin_write32(DMA41_PREV_DESC_PTR, val)
    1787. 

  1787. #define bfin_read_DMA41_CURR_ADDR() 		bfin_read32(DMA41_CURR_ADDR)
    1788. 

  1788. #define bfin_write_DMA41_CURR_ADDR(val) 	bfin_write32(DMA41_CURR_ADDR, val)
    1789. 

  1789. #define bfin_read_DMA41_IRQ_STATUS()		bfin_read32(DMA41_IRQ_STATUS)
    1790. 

  1790. #define bfin_write_DMA41_IRQ_STATUS(val)	bfin_write32(DMA41_IRQ_STATUS, val)
    1791. 

  1791. #define bfin_read_DMA41_CURR_X_COUNT()		bfin_read32(DMA41_CURR_X_COUNT)
    1792. 

  1792. #define bfin_write_DMA41_CURR_X_COUNT(val)	bfin_write32(DMA41_CURR_X_COUNT, val)
    1793. 

  1793. #define bfin_read_DMA41_CURR_Y_COUNT()		bfin_read32(DMA41_CURR_Y_COUNT)
    1794. 

  1794. #define bfin_write_DMA41_CURR_Y_COUNT(val)	bfin_write32(DMA41_CURR_Y_COUNT, val)
    1795. 

  1795. #define bfin_read_DMA41_BWL_COUNT()		bfin_read32(DMA41_BWL_COUNT)
    1796. 

  1796. #define bfin_write_DMA41_BWL_COUNT(val)		bfin_write32(DMA41_BWL_COUNT, val)
    1797. 

  1797. #define bfin_read_DMA41_CURR_BWL_COUNT()	bfin_read32(DMA41_CURR_BWL_COUNT)
    1798. 

  1798. #define bfin_write_DMA41_CURR_BWL_COUNT(val)	bfin_write32(DMA41_CURR_BWL_COUNT, val)
    1799. 

  1799. #define bfin_read_DMA41_BWM_COUNT()		bfin_read32(DMA41_BWM_COUNT)
    1800. 

  1800. #define bfin_write_DMA41_BWM_COUNT(val)		bfin_write32(DMA41_BWM_COUNT, val)
    1801. 

  1801. #define bfin_read_DMA41_CURR_BWM_COUNT()	bfin_read32(DMA41_CURR_BWM_COUNT)
    1802. 

  1802. #define bfin_write_DMA41_CURR_BWM_COUNT(val)	bfin_write32(DMA41_CURR_BWM_COUNT, val)
    1803. 

  1803. 

  1804. /* DMA Channel 42 Registers */
    1805. 

  1805. 

  1806. #define bfin_read_DMA42_NEXT_DESC_PTR() 	bfin_read32(DMA42_NEXT_DESC_PTR)
    1807. 

  1807. #define bfin_write_DMA42_NEXT_DESC_PTR(val) 	bfin_write32(DMA42_NEXT_DESC_PTR, val)
    1808. 

  1808. #define bfin_read_DMA42_START_ADDR() 		bfin_read32(DMA42_START_ADDR)
    1809. 

  1809. #define bfin_write_DMA42_START_ADDR(val) 	bfin_write32(DMA42_START_ADDR, val)
    1810. 

  1810. #define bfin_read_DMA42_CONFIG()		bfin_read32(DMA42_CONFIG)
    1811. 

  1811. #define bfin_write_DMA42_CONFIG(val)		bfin_write32(DMA42_CONFIG, val)
    1812. 

  1812. #define bfin_read_DMA42_X_COUNT()		bfin_read32(DMA42_X_COUNT)
    1813. 

  1813. #define bfin_write_DMA42_X_COUNT(val)		bfin_write32(DMA42_X_COUNT, val)
    1814. 

  1814. #define bfin_read_DMA42_X_MODIFY()		bfin_read32(DMA42_X_MODIFY)
    1815. 

  1815. #define bfin_write_DMA42_X_MODIFY(val) 		bfin_write32(DMA42_X_MODIFY, val)
    1816. 

  1816. #define bfin_read_DMA42_Y_COUNT()		bfin_read32(DMA42_Y_COUNT)
    1817. 

  1817. #define bfin_write_DMA42_Y_COUNT(val)		bfin_write32(DMA42_Y_COUNT, val)
    1818. 

  1818. #define bfin_read_DMA42_Y_MODIFY()		bfin_read32(DMA42_Y_MODIFY)
    1819. 

  1819. #define bfin_write_DMA42_Y_MODIFY(val) 		bfin_write32(DMA42_Y_MODIFY, val)
    1820. 

  1820. #define bfin_read_DMA42_CURR_DESC_PTR() 	bfin_read32(DMA42_CURR_DESC_PTR)
    1821. 

  1821. #define bfin_write_DMA42_CURR_DESC_PTR(val) 	bfin_write32(DMA42_CURR_DESC_PTR, val)
    1822. 

  1822. #define bfin_read_DMA42_PREV_DESC_PTR() 	bfin_read32(DMA42_PREV_DESC_PTR)
    1823. 

  1823. #define bfin_write_DMA42_PREV_DESC_PTR(val) 	bfin_write32(DMA42_PREV_DESC_PTR, val)
    1824. 

  1824. #define bfin_read_DMA42_CURR_ADDR() 		bfin_read32(DMA42_CURR_ADDR)
    1825. 

  1825. #define bfin_write_DMA42_CURR_ADDR(val) 	bfin_write32(DMA42_CURR_ADDR, val)
    1826. 

  1826. #define bfin_read_DMA42_IRQ_STATUS()		bfin_read32(DMA42_IRQ_STATUS)
    1827. 

  1827. #define bfin_write_DMA42_IRQ_STATUS(val)	bfin_write32(DMA42_IRQ_STATUS, val)
    1828. 

  1828. #define bfin_read_DMA42_CURR_X_COUNT()		bfin_read32(DMA42_CURR_X_COUNT)
    1829. 

  1829. #define bfin_write_DMA42_CURR_X_COUNT(val)	bfin_write32(DMA42_CURR_X_COUNT, val)
    1830. 

  1830. #define bfin_read_DMA42_CURR_Y_COUNT()		bfin_read32(DMA42_CURR_Y_COUNT)
    1831. 

  1831. #define bfin_write_DMA42_CURR_Y_COUNT(val)	bfin_write32(DMA42_CURR_Y_COUNT, val)
    1832. 

  1832. #define bfin_read_DMA42_BWL_COUNT()		bfin_read32(DMA42_BWL_COUNT)
    1833. 

  1833. #define bfin_write_DMA42_BWL_COUNT(val)		bfin_write32(DMA42_BWL_COUNT, val)
    1834. 

  1834. #define bfin_read_DMA42_CURR_BWL_COUNT()	bfin_read32(DMA42_CURR_BWL_COUNT)
    1835. 

  1835. #define bfin_write_DMA42_CURR_BWL_COUNT(val)	bfin_write32(DMA42_CURR_BWL_COUNT, val)
    1836. 

  1836. #define bfin_read_DMA42_BWM_COUNT()		bfin_read32(DMA42_BWM_COUNT)
    1837. 

  1837. #define bfin_write_DMA42_BWM_COUNT(val)		bfin_write32(DMA42_BWM_COUNT, val)
    1838. 

  1838. #define bfin_read_DMA42_CURR_BWM_COUNT()	bfin_read32(DMA42_CURR_BWM_COUNT)
    1839. 

  1839. #define bfin_write_DMA42_CURR_BWM_COUNT(val)	bfin_write32(DMA42_CURR_BWM_COUNT, val)
    1840. 

  1840. 

  1841. /* DMA Channel 43 Registers */
    1842. 

  1842. 

  1843. #define bfin_read_DMA43_NEXT_DESC_PTR() 	bfin_read32(DMA43_NEXT_DESC_PTR)
    1844. 

  1844. #define bfin_write_DMA43_NEXT_DESC_PTR(val) 	bfin_write32(DMA43_NEXT_DESC_PTR, val)
    1845. 

  1845. #define bfin_read_DMA43_START_ADDR() 		bfin_read32(DMA43_START_ADDR)
    1846. 

  1846. #define bfin_write_DMA43_START_ADDR(val) 	bfin_write32(DMA43_START_ADDR, val)
    1847. 

  1847. #define bfin_read_DMA43_CONFIG()		bfin_read32(DMA43_CONFIG)
    1848. 

  1848. #define bfin_write_DMA43_CONFIG(val)		bfin_write32(DMA43_CONFIG, val)
    1849. 

  1849. #define bfin_read_DMA43_X_COUNT()		bfin_read32(DMA43_X_COUNT)
    1850. 

  1850. #define bfin_write_DMA43_X_COUNT(val)		bfin_write32(DMA43_X_COUNT, val)
    1851. 

  1851. #define bfin_read_DMA43_X_MODIFY()		bfin_read32(DMA43_X_MODIFY)
    1852. 

  1852. #define bfin_write_DMA43_X_MODIFY(val) 		bfin_write32(DMA43_X_MODIFY, val)
    1853. 

  1853. #define bfin_read_DMA43_Y_COUNT()		bfin_read32(DMA43_Y_COUNT)
    1854. 

  1854. #define bfin_write_DMA43_Y_COUNT(val)		bfin_write32(DMA43_Y_COUNT, val)
    1855. 

  1855. #define bfin_read_DMA43_Y_MODIFY()		bfin_read32(DMA43_Y_MODIFY)
    1856. 

  1856. #define bfin_write_DMA43_Y_MODIFY(val) 		bfin_write32(DMA43_Y_MODIFY, val)
    1857. 

  1857. #define bfin_read_DMA43_CURR_DESC_PTR() 	bfin_read32(DMA43_CURR_DESC_PTR)
    1858. 

  1858. #define bfin_write_DMA43_CURR_DESC_PTR(val) 	bfin_write32(DMA43_CURR_DESC_PTR, val)
    1859. 

  1859. #define bfin_read_DMA43_PREV_DESC_PTR() 	bfin_read32(DMA43_PREV_DESC_PTR)
    1860. 

  1860. #define bfin_write_DMA43_PREV_DESC_PTR(val) 	bfin_write32(DMA43_PREV_DESC_PTR, val)
    1861. 

  1861. #define bfin_read_DMA43_CURR_ADDR() 		bfin_read32(DMA43_CURR_ADDR)
    1862. 

  1862. #define bfin_write_DMA43_CURR_ADDR(val) 	bfin_write32(DMA43_CURR_ADDR, val)
    1863. 

  1863. #define bfin_read_DMA43_IRQ_STATUS()		bfin_read32(DMA43_IRQ_STATUS)
    1864. 

  1864. #define bfin_write_DMA43_IRQ_STATUS(val)	bfin_write32(DMA43_IRQ_STATUS, val)
    1865. 

  1865. #define bfin_read_DMA43_CURR_X_COUNT()		bfin_read32(DMA43_CURR_X_COUNT)
    1866. 

  1866. #define bfin_write_DMA43_CURR_X_COUNT(val)	bfin_write32(DMA43_CURR_X_COUNT, val)
    1867. 

  1867. #define bfin_read_DMA43_CURR_Y_COUNT()		bfin_read32(DMA43_CURR_Y_COUNT)
    1868. 

  1868. #define bfin_write_DMA43_CURR_Y_COUNT(val)	bfin_write32(DMA43_CURR_Y_COUNT, val)
    1869. 

  1869. #define bfin_read_DMA43_BWL_COUNT()		bfin_read32(DMA43_BWL_COUNT)
    1870. 

  1870. #define bfin_write_DMA43_BWL_COUNT(val)		bfin_write32(DMA43_BWL_COUNT, val)
    1871. 

  1871. #define bfin_read_DMA43_CURR_BWL_COUNT()	bfin_read32(DMA43_CURR_BWL_COUNT)
    1872. 

  1872. #define bfin_write_DMA43_CURR_BWL_COUNT(val)	bfin_write32(DMA43_CURR_BWL_COUNT, val)
    1873. 

  1873. #define bfin_read_DMA43_BWM_COUNT()		bfin_read32(DMA43_BWM_COUNT)
    1874. 

  1874. #define bfin_write_DMA43_BWM_COUNT(val)		bfin_write32(DMA43_BWM_COUNT, val)
    1875. 

  1875. #define bfin_read_DMA43_CURR_BWM_COUNT()	bfin_read32(DMA43_CURR_BWM_COUNT)
    1876. 

  1876. #define bfin_write_DMA43_CURR_BWM_COUNT(val)	bfin_write32(DMA43_CURR_BWM_COUNT, val)
    1877. 

  1877. 

  1878. /* DMA Channel 44 Registers */
    1879. 

  1879. 

  1880. #define bfin_read_DMA44_NEXT_DESC_PTR() 	bfin_read32(DMA44_NEXT_DESC_PTR)
    1881. 

  1881. #define bfin_write_DMA44_NEXT_DESC_PTR(val) 	bfin_write32(DMA44_NEXT_DESC_PTR, val)
    1882. 

  1882. #define bfin_read_DMA44_START_ADDR() 		bfin_read32(DMA44_START_ADDR)
    1883. 

  1883. #define bfin_write_DMA44_START_ADDR(val) 	bfin_write32(DMA44_START_ADDR, val)
    1884. 

  1884. #define bfin_read_DMA44_CONFIG()		bfin_read32(DMA44_CONFIG)
    1885. 

  1885. #define bfin_write_DMA44_CONFIG(val)		bfin_write32(DMA44_CONFIG, val)
    1886. 

  1886. #define bfin_read_DMA44_X_COUNT()		bfin_read32(DMA44_X_COUNT)
    1887. 

  1887. #define bfin_write_DMA44_X_COUNT(val)		bfin_write32(DMA44_X_COUNT, val)
    1888. 

  1888. #define bfin_read_DMA44_X_MODIFY()		bfin_read32(DMA44_X_MODIFY)
    1889. 

  1889. #define bfin_write_DMA44_X_MODIFY(val) 		bfin_write32(DMA44_X_MODIFY, val)
    1890. 

  1890. #define bfin_read_DMA44_Y_COUNT()		bfin_read32(DMA44_Y_COUNT)
    1891. 

  1891. #define bfin_write_DMA44_Y_COUNT(val)		bfin_write32(DMA44_Y_COUNT, val)
    1892. 

  1892. #define bfin_read_DMA44_Y_MODIFY()		bfin_read32(DMA44_Y_MODIFY)
    1893. 

  1893. #define bfin_write_DMA44_Y_MODIFY(val) 		bfin_write32(DMA44_Y_MODIFY, val)
    1894. 

  1894. #define bfin_read_DMA44_CURR_DESC_PTR() 	bfin_read32(DMA44_CURR_DESC_PTR)
    1895. 

  1895. #define bfin_write_DMA44_CURR_DESC_PTR(val) 	bfin_write32(DMA44_CURR_DESC_PTR, val)
    1896. 

  1896. #define bfin_read_DMA44_PREV_DESC_PTR() 	bfin_read32(DMA44_PREV_DESC_PTR)
    1897. 

  1897. #define bfin_write_DMA44_PREV_DESC_PTR(val) 	bfin_write32(DMA44_PREV_DESC_PTR, val)
    1898. 

  1898. #define bfin_read_DMA44_CURR_ADDR() 		bfin_read32(DMA44_CURR_ADDR)
    1899. 

  1899. #define bfin_write_DMA44_CURR_ADDR(val) 	bfin_write32(DMA44_CURR_ADDR, val)
    1900. 

  1900. #define bfin_read_DMA44_IRQ_STATUS()		bfin_read32(DMA44_IRQ_STATUS)
    1901. 

  1901. #define bfin_write_DMA44_IRQ_STATUS(val)	bfin_write32(DMA44_IRQ_STATUS, val)
    1902. 

  1902. #define bfin_read_DMA44_CURR_X_COUNT()		bfin_read32(DMA44_CURR_X_COUNT)
    1903. 

  1903. #define bfin_write_DMA44_CURR_X_COUNT(val)	bfin_write32(DMA44_CURR_X_COUNT, val)
    1904. 

  1904. #define bfin_read_DMA44_CURR_Y_COUNT()		bfin_read32(DMA44_CURR_Y_COUNT)
    1905. 

  1905. #define bfin_write_DMA44_CURR_Y_COUNT(val)	bfin_write32(DMA44_CURR_Y_COUNT, val)
    1906. 

  1906. #define bfin_read_DMA44_BWL_COUNT()		bfin_read32(DMA44_BWL_COUNT)
    1907. 

  1907. #define bfin_write_DMA44_BWL_COUNT(val)		bfin_write32(DMA44_BWL_COUNT, val)
    1908. 

  1908. #define bfin_read_DMA44_CURR_BWL_COUNT()	bfin_read32(DMA44_CURR_BWL_COUNT)
    1909. 

  1909. #define bfin_write_DMA44_CURR_BWL_COUNT(val)	bfin_write32(DMA44_CURR_BWL_COUNT, val)
    1910. 

  1910. #define bfin_read_DMA44_BWM_COUNT()		bfin_read32(DMA44_BWM_COUNT)
    1911. 

  1911. #define bfin_write_DMA44_BWM_COUNT(val)		bfin_write32(DMA44_BWM_COUNT, val)
    1912. 

  1912. #define bfin_read_DMA44_CURR_BWM_COUNT()	bfin_read32(DMA44_CURR_BWM_COUNT)
    1913. 

  1913. #define bfin_write_DMA44_CURR_BWM_COUNT(val)	bfin_write32(DMA44_CURR_BWM_COUNT, val)
    1914. 

  1914. 

  1915. /* DMA Channel 45 Registers */
    1916. 

  1916. 

  1917. #define bfin_read_DMA45_NEXT_DESC_PTR() 	bfin_read32(DMA45_NEXT_DESC_PTR)
    1918. 

  1918. #define bfin_write_DMA45_NEXT_DESC_PTR(val) 	bfin_write32(DMA45_NEXT_DESC_PTR, val)
    1919. 

  1919. #define bfin_read_DMA45_START_ADDR() 		bfin_read32(DMA45_START_ADDR)
    1920. 

  1920. #define bfin_write_DMA45_START_ADDR(val) 	bfin_write32(DMA45_START_ADDR, val)
    1921. 

  1921. #define bfin_read_DMA45_CONFIG()		bfin_read32(DMA45_CONFIG)
    1922. 

  1922. #define bfin_write_DMA45_CONFIG(val)		bfin_write32(DMA45_CONFIG, val)
    1923. 

  1923. #define bfin_read_DMA45_X_COUNT()		bfin_read32(DMA45_X_COUNT)
    1924. 

  1924. #define bfin_write_DMA45_X_COUNT(val)		bfin_write32(DMA45_X_COUNT, val)
    1925. 

  1925. #define bfin_read_DMA45_X_MODIFY()		bfin_read32(DMA45_X_MODIFY)
    1926. 

  1926. #define bfin_write_DMA45_X_MODIFY(val) 		bfin_write32(DMA45_X_MODIFY, val)
    1927. 

  1927. #define bfin_read_DMA45_Y_COUNT()		bfin_read32(DMA45_Y_COUNT)
    1928. 

  1928. #define bfin_write_DMA45_Y_COUNT(val)		bfin_write32(DMA45_Y_COUNT, val)
    1929. 

  1929. #define bfin_read_DMA45_Y_MODIFY()		bfin_read32(DMA45_Y_MODIFY)
    1930. 

  1930. #define bfin_write_DMA45_Y_MODIFY(val) 		bfin_write32(DMA45_Y_MODIFY, val)
    1931. 

  1931. #define bfin_read_DMA45_CURR_DESC_PTR() 	bfin_read32(DMA45_CURR_DESC_PTR)
    1932. 

  1932. #define bfin_write_DMA45_CURR_DESC_PTR(val) 	bfin_write32(DMA45_CURR_DESC_PTR, val)
    1933. 

  1933. #define bfin_read_DMA45_PREV_DESC_PTR() 	bfin_read32(DMA45_PREV_DESC_PTR)
    1934. 

  1934. #define bfin_write_DMA45_PREV_DESC_PTR(val) 	bfin_write32(DMA45_PREV_DESC_PTR, val)
    1935. 

  1935. #define bfin_read_DMA45_CURR_ADDR() 		bfin_read32(DMA45_CURR_ADDR)
    1936. 

  1936. #define bfin_write_DMA45_CURR_ADDR(val) 	bfin_write32(DMA45_CURR_ADDR, val)
    1937. 

  1937. #define bfin_read_DMA45_IRQ_STATUS()		bfin_read32(DMA45_IRQ_STATUS)
    1938. 

  1938. #define bfin_write_DMA45_IRQ_STATUS(val)	bfin_write32(DMA45_IRQ_STATUS, val)
    1939. 

  1939. #define bfin_read_DMA45_CURR_X_COUNT()		bfin_read32(DMA45_CURR_X_COUNT)
    1940. 

  1940. #define bfin_write_DMA45_CURR_X_COUNT(val)	bfin_write32(DMA45_CURR_X_COUNT, val)
    1941. 

  1941. #define bfin_read_DMA45_CURR_Y_COUNT()		bfin_read32(DMA45_CURR_Y_COUNT)
    1942. 

  1942. #define bfin_write_DMA45_CURR_Y_COUNT(val)	bfin_write32(DMA45_CURR_Y_COUNT, val)
    1943. 

  1943. #define bfin_read_DMA45_BWL_COUNT()		bfin_read32(DMA45_BWL_COUNT)
    1944. 

  1944. #define bfin_write_DMA45_BWL_COUNT(val)		bfin_write32(DMA45_BWL_COUNT, val)
    1945. 

  1945. #define bfin_read_DMA45_CURR_BWL_COUNT()	bfin_read32(DMA45_CURR_BWL_COUNT)
    1946. 

  1946. #define bfin_write_DMA45_CURR_BWL_COUNT(val)	bfin_write32(DMA45_CURR_BWL_COUNT, val)
    1947. 

  1947. #define bfin_read_DMA45_BWM_COUNT()		bfin_read32(DMA45_BWM_COUNT)
    1948. 

  1948. #define bfin_write_DMA45_BWM_COUNT(val)		bfin_write32(DMA45_BWM_COUNT, val)
    1949. 

  1949. #define bfin_read_DMA45_CURR_BWM_COUNT()	bfin_read32(DMA45_CURR_BWM_COUNT)
    1950. 

  1950. #define bfin_write_DMA45_CURR_BWM_COUNT(val)	bfin_write32(DMA45_CURR_BWM_COUNT, val)
    1951. 

  1951. 

  1952. /* DMA Channel 46 Registers */
    1953. 

  1953. 

  1954. #define bfin_read_DMA46_NEXT_DESC_PTR() 	bfin_read32(DMA46_NEXT_DESC_PTR)
    1955. 

  1955. #define bfin_write_DMA46_NEXT_DESC_PTR(val) 	bfin_write32(DMA46_NEXT_DESC_PTR, val)
    1956. 

  1956. #define bfin_read_DMA46_START_ADDR() 		bfin_read32(DMA46_START_ADDR)
    1957. 

  1957. #define bfin_write_DMA46_START_ADDR(val) 	bfin_write32(DMA46_START_ADDR, val)
    1958. 

  1958. #define bfin_read_DMA46_CONFIG()		bfin_read32(DMA46_CONFIG)
    1959. 

  1959. #define bfin_write_DMA46_CONFIG(val)		bfin_write32(DMA46_CONFIG, val)
    1960. 

  1960. #define bfin_read_DMA46_X_COUNT()		bfin_read32(DMA46_X_COUNT)
    1961. 

  1961. #define bfin_write_DMA46_X_COUNT(val)		bfin_write32(DMA46_X_COUNT, val)
    1962. 

  1962. #define bfin_read_DMA46_X_MODIFY()		bfin_read32(DMA46_X_MODIFY)
    1963. 

  1963. #define bfin_write_DMA46_X_MODIFY(val) 		bfin_write32(DMA46_X_MODIFY, val)
    1964. 

  1964. #define bfin_read_DMA46_Y_COUNT()		bfin_read32(DMA46_Y_COUNT)
    1965. 

  1965. #define bfin_write_DMA46_Y_COUNT(val)		bfin_write32(DMA46_Y_COUNT, val)
    1966. 

  1966. #define bfin_read_DMA46_Y_MODIFY()		bfin_read32(DMA46_Y_MODIFY)
    1967. 

  1967. #define bfin_write_DMA46_Y_MODIFY(val) 		bfin_write32(DMA46_Y_MODIFY, val)
    1968. 

  1968. #define bfin_read_DMA46_CURR_DESC_PTR() 	bfin_read32(DMA46_CURR_DESC_PTR)
    1969. 

  1969. #define bfin_write_DMA46_CURR_DESC_PTR(val) 	bfin_write32(DMA46_CURR_DESC_PTR, val)
    1970. 

  1970. #define bfin_read_DMA46_PREV_DESC_PTR() 	bfin_read32(DMA46_PREV_DESC_PTR)
    1971. 

  1971. #define bfin_write_DMA46_PREV_DESC_PTR(val) 	bfin_write32(DMA46_PREV_DESC_PTR, val)
    1972. 

  1972. #define bfin_read_DMA46_CURR_ADDR() 		bfin_read32(DMA46_CURR_ADDR)
    1973. 

  1973. #define bfin_write_DMA46_CURR_ADDR(val) 	bfin_write32(DMA46_CURR_ADDR, val)
    1974. 

  1974. #define bfin_read_DMA46_IRQ_STATUS()		bfin_read32(DMA46_IRQ_STATUS)
    1975. 

  1975. #define bfin_write_DMA46_IRQ_STATUS(val)	bfin_write32(DMA46_IRQ_STATUS, val)
    1976. 

  1976. #define bfin_read_DMA46_CURR_X_COUNT()		bfin_read32(DMA46_CURR_X_COUNT)
    1977. 

  1977. #define bfin_write_DMA46_CURR_X_COUNT(val)	bfin_write32(DMA46_CURR_X_COUNT, val)
    1978. 

  1978. #define bfin_read_DMA46_CURR_Y_COUNT()		bfin_read32(DMA46_CURR_Y_COUNT)
    1979. 

  1979. #define bfin_write_DMA46_CURR_Y_COUNT(val)	bfin_write32(DMA46_CURR_Y_COUNT, val)
    1980. 

  1980. #define bfin_read_DMA46_BWL_COUNT()		bfin_read32(DMA46_BWL_COUNT)
    1981. 

  1981. #define bfin_write_DMA46_BWL_COUNT(val)		bfin_write32(DMA46_BWL_COUNT, val)
    1982. 

  1982. #define bfin_read_DMA46_CURR_BWL_COUNT()	bfin_read32(DMA46_CURR_BWL_COUNT)
    1983. 

  1983. #define bfin_write_DMA46_CURR_BWL_COUNT(val)	bfin_write32(DMA46_CURR_BWL_COUNT, val)
    1984. 

  1984. #define bfin_read_DMA46_BWM_COUNT()		bfin_read32(DMA46_BWM_COUNT)
    1985. 

  1985. #define bfin_write_DMA46_BWM_COUNT(val)		bfin_write32(DMA46_BWM_COUNT, val)
    1986. 

  1986. #define bfin_read_DMA46_CURR_BWM_COUNT()	bfin_read32(DMA46_CURR_BWM_COUNT)
    1987. 

  1987. #define bfin_write_DMA46_CURR_BWM_COUNT(val)	bfin_write32(DMA46_CURR_BWM_COUNT, val)
    1988. 

  1988. 

  1989. 

  1990. /* EPPI1 Registers */
    1991. 

  1991. 

  1992. 

  1993. /* Port Interrubfin_read_()t 0 Registers (32-bit) */
    1994. 

  1994. 

  1995. #define bfin_read_PINT0_MASK_SET()		bfin_read32(PINT0_MASK_SET)
    1996. 

  1996. #define bfin_write_PINT0_MASK_SET(val)		bfin_write32(PINT0_MASK_SET, val)
    1997. 

  1997. #define bfin_read_PINT0_MASK_CLEAR()		bfin_read32(PINT0_MASK_CLEAR)
    1998. 

  1998. #define bfin_write_PINT0_MASK_CLEAR(val)	bfin_write32(PINT0_MASK_CLEAR, val)
    1999. 

  1999. #define bfin_read_PINT0_REQUEST()		bfin_read32(PINT0_REQUEST)
    2000. 

  2000. #define bfin_write_PINT0_REQUEST(val)		bfin_write32(PINT0_REQUEST, val)
    2001. 

  2001. #define bfin_read_PINT0_ASSIGN()		bfin_read32(PINT0_ASSIGN)
    2002. 

  2002. #define bfin_write_PINT0_ASSIGN(val)		bfin_write32(PINT0_ASSIGN, val)
    2003. 

  2003. #define bfin_read_PINT0_EDGE_SET()		bfin_read32(PINT0_EDGE_SET)
    2004. 

  2004. #define bfin_write_PINT0_EDGE_SET(val)		bfin_write32(PINT0_EDGE_SET, val)
    2005. 

  2005. #define bfin_read_PINT0_EDGE_CLEAR()		bfin_read32(PINT0_EDGE_CLEAR)
    2006. 

  2006. #define bfin_write_PINT0_EDGE_CLEAR(val)	bfin_write32(PINT0_EDGE_CLEAR, val)
    2007. 

  2007. #define bfin_read_PINT0_INVERT_SET()		bfin_read32(PINT0_INVERT_SET)
    2008. 

  2008. #define bfin_write_PINT0_INVERT_SET(val)	bfin_write32(PINT0_INVERT_SET, val)
    2009. 

  2009. #define bfin_read_PINT0_INVERT_CLEAR()		bfin_read32(PINT0_INVERT_CLEAR)
    2010. 

  2010. #define bfin_write_PINT0_INVERT_CLEAR(val)	bfin_write32(PINT0_INVERT_CLEAR, val)
    2011. 

  2011. #define bfin_read_PINT0_PINSTATE()		bfin_read32(PINT0_PINSTATE)
    2012. 

  2012. #define bfin_write_PINT0_PINSTATE(val)		bfin_write32(PINT0_PINSTATE, val)
    2013. 

  2013. #define bfin_read_PINT0_LATCH()			bfin_read32(PINT0_LATCH)
    2014. 

  2014. #define bfin_write_PINT0_LATCH(val)		bfin_write32(PINT0_LATCH, val)
    2015. 

  2015. 

  2016. /* Port Interrubfin_read_()t 1 Registers (32-bit) */
    2017. 

  2017. 

  2018. #define bfin_read_PINT1_MASK_SET()		bfin_read32(PINT1_MASK_SET)
    2019. 

  2019. #define bfin_write_PINT1_MASK_SET(val)		bfin_write32(PINT1_MASK_SET, val)
    2020. 

  2020. #define bfin_read_PINT1_MASK_CLEAR()		bfin_read32(PINT1_MASK_CLEAR)
    2021. 

  2021. #define bfin_write_PINT1_MASK_CLEAR(val)	bfin_write32(PINT1_MASK_CLEAR, val)
    2022. 

  2022. #define bfin_read_PINT1_REQUEST()		bfin_read32(PINT1_REQUEST)
    2023. 

  2023. #define bfin_write_PINT1_REQUEST(val)		bfin_write32(PINT1_REQUEST, val)
    2024. 

  2024. #define bfin_read_PINT1_ASSIGN()		bfin_read32(PINT1_ASSIGN)
    2025. 

  2025. #define bfin_write_PINT1_ASSIGN(val)		bfin_write32(PINT1_ASSIGN, val)
    2026. 

  2026. #define bfin_read_PINT1_EDGE_SET()		bfin_read32(PINT1_EDGE_SET)
    2027. 

  2027. #define bfin_write_PINT1_EDGE_SET(val)		bfin_write32(PINT1_EDGE_SET, val)
    2028. 

  2028. #define bfin_read_PINT1_EDGE_CLEAR()		bfin_read32(PINT1_EDGE_CLEAR)
    2029. 

  2029. #define bfin_write_PINT1_EDGE_CLEAR(val)	bfin_write32(PINT1_EDGE_CLEAR, val)
    2030. 

  2030. #define bfin_read_PINT1_INVERT_SET()		bfin_read32(PINT1_INVERT_SET)
    2031. 

  2031. #define bfin_write_PINT1_INVERT_SET(val)	bfin_write32(PINT1_INVERT_SET, val)
    2032. 

  2032. #define bfin_read_PINT1_INVERT_CLEAR()		bfin_read32(PINT1_INVERT_CLEAR)
    2033. 

  2033. #define bfin_write_PINT1_INVERT_CLEAR(val)	bfin_write32(PINT1_INVERT_CLEAR, val)
    2034. 

  2034. #define bfin_read_PINT1_PINSTATE()		bfin_read32(PINT1_PINSTATE)
    2035. 

  2035. #define bfin_write_PINT1_PINSTATE(val)		bfin_write32(PINT1_PINSTATE, val)
    2036. 

  2036. #define bfin_read_PINT1_LATCH()			bfin_read32(PINT1_LATCH)
    2037. 

  2037. #define bfin_write_PINT1_LATCH(val)		bfin_write32(PINT1_LATCH, val)
    2038. 

  2038. 

  2039. /* Port Interrubfin_read_()t 2 Registers (32-bit) */
    2040. 

  2040. 

  2041. #define bfin_read_PINT2_MASK_SET()		bfin_read32(PINT2_MASK_SET)
    2042. 

  2042. #define bfin_write_PINT2_MASK_SET(val)		bfin_write32(PINT2_MASK_SET, val)
    2043. 

  2043. #define bfin_read_PINT2_MASK_CLEAR()		bfin_read32(PINT2_MASK_CLEAR)
    2044. 

  2044. #define bfin_write_PINT2_MASK_CLEAR(val)	bfin_write32(PINT2_MASK_CLEAR, val)
    2045. 

  2045. #define bfin_read_PINT2_REQUEST()		bfin_read32(PINT2_REQUEST)
    2046. 

  2046. #define bfin_write_PINT2_REQUEST(val)		bfin_write32(PINT2_REQUEST, val)
    2047. 

  2047. #define bfin_read_PINT2_ASSIGN()		bfin_read32(PINT2_ASSIGN)
    2048. 

  2048. #define bfin_write_PINT2_ASSIGN(val)		bfin_write32(PINT2_ASSIGN, val)
    2049. 

  2049. #define bfin_read_PINT2_EDGE_SET()		bfin_read32(PINT2_EDGE_SET)
    2050. 

  2050. #define bfin_write_PINT2_EDGE_SET(val)		bfin_write32(PINT2_EDGE_SET, val)
    2051. 

  2051. #define bfin_read_PINT2_EDGE_CLEAR()		bfin_read32(PINT2_EDGE_CLEAR)
    2052. 

  2052. #define bfin_write_PINT2_EDGE_CLEAR(val)	bfin_write32(PINT2_EDGE_CLEAR, val)
    2053. 

  2053. #define bfin_read_PINT2_INVERT_SET()		bfin_read32(PINT2_INVERT_SET)
    2054. 

  2054. #define bfin_write_PINT2_INVERT_SET(val)	bfin_write32(PINT2_INVERT_SET, val)
    2055. 

  2055. #define bfin_read_PINT2_INVERT_CLEAR()		bfin_read32(PINT2_INVERT_CLEAR)
    2056. 

  2056. #define bfin_write_PINT2_INVERT_CLEAR(val)	bfin_write32(PINT2_INVERT_CLEAR, val)
    2057. 

  2057. #define bfin_read_PINT2_PINSTATE()		bfin_read32(PINT2_PINSTATE)
    2058. 

  2058. #define bfin_write_PINT2_PINSTATE(val)		bfin_write32(PINT2_PINSTATE, val)
    2059. 

  2059. #define bfin_read_PINT2_LATCH()			bfin_read32(PINT2_LATCH)
    2060. 

  2060. #define bfin_write_PINT2_LATCH(val)		bfin_write32(PINT2_LATCH, val)
    2061. 

  2061. 

  2062. /* Port Interrubfin_read_()t 3 Registers (32-bit) */
    2063. 

  2063. 

  2064. #define bfin_read_PINT3_MASK_SET()		bfin_read32(PINT3_MASK_SET)
    2065.