synchronousMemoryDatabase.h 2.6 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 1995 Waldorf GmbH
  7. * Copyright (C) 1994 - 2000, 06 Ralf Baechle
  8. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9. * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
  10. * Author: Maciej W. Rozycki <macro@mips.com>
  11. */
  12. #ifndef _ASM_IO_H
  13. #define _ASM_IO_H
  14. #include <linux/compiler.h>
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <linux/irqflags.h>
  18. #include <asm/addrspace.h>
  19. #include <asm/bug.h>
  20. #include <asm/byteorder.h>
  21. #include <asm/cpu.h>
  22. #include <asm/cpu-features.h>
  23. #include <asm-generic/iomap.h>
  24. #include <asm/page.h>
  25. #include <asm/pgtable-bits.h>
  26. #include <asm/processor.h>
  27. #include <asm/string.h>
  28. #include <ioremap.h>
  29. #include <mangle-port.h>
  30. /*
  31. * Slowdown I/O port space accesses for antique hardware.
  32. */
  33. #undef CONF_SLOWDOWN_IO
  34. /*
  35. * Raw operations are never swapped in software. OTOH values that raw
  36. * operations are working on may or may not have been swapped by the bus
  37. * hardware. An example use would be for flash memory that's used for
  38. * execute in place.
  39. */
  40. # define __raw_ioswabb(a, x) (x)
  41. # define __raw_ioswabw(a, x) (x)
  42. # define __raw_ioswabl(a, x) (x)
  43. # define __raw_ioswabq(a, x) (x)
  44. # define ____raw_ioswabq(a, x) (x)
  45. /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  46. #define IO_SPACE_LIMIT 0xffff
  47. /*
  48. * On MIPS I/O ports are memory mapped, so we access them using normal
  49. * load/store instructions. mips_io_port_base is the virtual address to
  50. * which all ports are being mapped. For sake of efficiency some code
  51. * assumes that this is an address that can be loaded with a single lui
  52. * instruction, so the lower 16 bits must be zero. Should be true on
  53. * on any sane architecture; generic code does not use this assumption.
  54. */
  55. extern const unsigned long mips_io_port_base;
  56. /*
  57. * Gcc will generate code to load the value of mips_io_port_base after each
  58. * function call which may be fairly wasteful in some cases. So we don't
  59. * play quite by the book. We tell gcc mips_io_port_base is a long variable
  60. * which solves the code generation issue. Now we need to violate the
  61. * aliasing rules a little to make initialization possible and finally we
  62. * will need the barrier() to fight side effects of the aliasing chat.
  63. * This trickery will eventually collapse under gcc's optimizer. Oh well.
  64. */
  65. static inline void set_io_port_base(unsigned long base)
  66. {
  67. * (unsigned long *) &mips_io_port_base = base;
  68. barrier();
  69. }