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- /*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF547_H
- #define _DEF_BF547_H
- /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
- #include "defBF54x_base.h"
- /* The following are the #defines needed by ADSP-BF547 that are not in the common header */
- /* Timer Registers */
- #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
- #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
- #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
- #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
- #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
- #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
- #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
- #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
- #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
- #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
- #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
- #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
- /* Timer Group of 3 Registers */
- #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
- #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
- #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
- /* SPORT0 Registers */
- #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
- #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
- #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
- #define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
- #define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
- #define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
- #define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
- #define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
- #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
- #define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
- #define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
- #define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
- #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
- #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
- #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
- #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
- #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
- #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
- #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
- #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
- #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
- #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
- /* EPPI0 Registers */
- #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
- #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
- #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
- #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
- #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
- #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
- #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
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