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connectionSignalSlot.h

connectionSignalSlot.h 3.0 KB
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  1. #ifndef _ASM_M32R_M32R_MP_FPGA_
    2. 

  2. #define _ASM_M32R_M32R_MP_FPGA_
    3. 

  3. 

  4. /*
    5. 

  5.  * Renesas M32R-MP-FPGA
    6. 

  6.  *
    7. 

  7.  * Copyright (c) 2002  Hitoshi Yamamoto
    8. 

  8.  * Copyright (c) 2003, 2004  Renesas Technology Corp.
    9. 

  9.  */
    10. 

  10. 

  11. /*
    12. 

  12.  * ========================================================
    13. 

  13.  * M32R-MP-FPGA Memory Map
    14. 

  14.  * ========================================================
    15. 

  15.  * 0x00000000 : Block#0 : 64[MB]
    16. 

  16.  *              0x03E00000 : SFR
    17. 

  17.  *                           0x03E00000 : reserved
    18. 

  18.  *                           0x03EF0000 : FPGA
    19. 

  19.  *                           0x03EF1000 : reserved
    20. 

  20.  *                           0x03EF4000 : CKM
    21. 

  21.  *                           0x03EF4000 : BSELC
    22. 

  22.  *                           0x03EF5000 : reserved
    23. 

  23.  *                           0x03EFC000 : MFT
    24. 

  24.  *                           0x03EFD000 : SIO
    25. 

  25.  *                           0x03EFE000 : reserved
    26. 

  26.  *                           0x03EFF000 : ICU
    27. 

  27.  *              0x03F00000 : Internal SRAM 64[KB]
    28. 

  28.  *              0x03F10000 : reserved
    29. 

  29.  * --------------------------------------------------------
    30. 

  30.  * 0x04000000 : Block#1 : 64[MB]
    31. 

  31.  *              0x04000000 : Debug board SRAM 4[MB]
    32. 

  32.  *              0x04400000 : reserved
    33. 

  33.  * --------------------------------------------------------
    34. 

  34.  * 0x08000000 : Block#2 : 64[MB]
    35. 

  35.  * --------------------------------------------------------
    36. 

  36.  * 0x0C000000 : Block#3 : 64[MB]
    37. 

  37.  * --------------------------------------------------------
    38. 

  38.  * 0x10000000 : Block#4 : 64[MB]
    39. 

  39.  * --------------------------------------------------------
    40. 

  40.  * 0x14000000 : Block#5 : 64[MB]
    41. 

  41.  * --------------------------------------------------------
    42. 

  42.  * 0x18000000 : Block#6 : 64[MB]
    43. 

  43.  * --------------------------------------------------------
    44. 

  44.  * 0x1C000000 : Block#7 : 64[MB]
    45. 

  45.  * --------------------------------------------------------
    46. 

  46.  * 0xFE000000 : TLB
    47. 

  47.  *              0xFE000000 : ITLB
    48. 

  48.  *              0xFE000080 : reserved
    49. 

  49.  *              0xFE000800 : DTLB
    50. 

  50.  *              0xFE000880 : reserved
    51. 

  51.  * --------------------------------------------------------
    52. 

  52.  * 0xFF000000 : System area
    53. 

  53.  *              0xFFFF0000 : MMU
    54. 

  54.  *              0xFFFF0030 : reserved
    55. 

  55.  *              0xFFFF8000 : Debug function
    56. 

  56.  *              0xFFFFA000 : reserved
    57. 

  57.  *              0xFFFFC000 : CPU control
    58. 

  58.  * 0xFFFFFFFF
    59. 

  59.  * ========================================================
    60. 

  60.  */
    61. 

  61. 

  62. /*======================================================================*
    63. 

  63.  * Special Function Register
    64. 

  64.  *======================================================================*/
    65. 

  65. #define M32R_SFR_OFFSET  (0x00E00000)  /* 0x03E00000-0x03EFFFFF 1[MB] */
    66. 

  66. 

  67. /*
    68. 

  68.  * FPGA registers.
    69. 

  69.  */
    70. 

  70. #define M32R_FPGA_TOP  (0x000F0000+M32R_SFR_OFFSET)
    71. 

  71. 

  72. #define M32R_FPGA_NUM_OF_CPUS_PORTL  (0x00+M32R_FPGA_TOP)
    73. 

  73. #define M32R_FPGA_CPU_NAME0_PORTL    (0x10+M32R_FPGA_TOP)
    74. 

  74. #define M32R_FPGA_CPU_NAME1_PORTL    (0x14+M32R_FPGA_TOP)
    75. 

  75. #define M32R_FPGA_CPU_NAME2_PORTL    (0x18+M32R_FPGA_TOP)
    76. 

  76. #define M32R_FPGA_CPU_NAME3_PORTL    (0x1C+M32R_FPGA_TOP)
    77. 

  77. #define M32R_FPGA_MODEL_ID0_PORTL    (0x20+M32R_FPGA_TOP)
    78. 

  78. #define M32R_FPGA_MODEL_ID1_PORTL    (0x24+M32R_FPGA_TOP)
    79.