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- /*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF544_H
- #define _DEF_BF544_H
- /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
- #include "defBF54x_base.h"
- /* The following are the #defines needed by ADSP-BF544 that are not in the common header */
- /* Timer Registers */
- #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
- #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
- #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
- #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
- #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
- #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
- #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
- #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
- #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
- #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
- #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
- #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
- /* Timer Group of 3 Registers */
- #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
- #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
- #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
- /* EPPI0 Registers */
- #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
- #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
- #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
- #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
- #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
- #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
- #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
- #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
- #define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
- #define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
- #define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
- #define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
- #define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
- #define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
- /* Two Wire Interface Registers (TWI1) */
- #define TWI1_REGBASE 0xffc02200
- #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
- #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
- #define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
- #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
- #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
- #define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
- #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
- #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
- #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
- #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
- #define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
- #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
- #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
- #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
- #define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
- #define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
- /* CAN Controller 1 Config 1 Registers */
- #define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
- #define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
- #define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
- #define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
- #define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
- #define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
- #define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
- #define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
- #define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
- #define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
- #define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
- #define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
- #define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
- /* CAN Controller 1 Config 2 Registers */
- #define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
- #define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
- #define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
- #define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
- #define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
- #define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
- #define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
- #define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
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