aiot/waterDataStatistics/alarmDataCalculation/realizationOfDataCalculation.c

/*
 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
 *
 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is automatically generated from the AM33XX hardware databases.
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/i2c-omap.h>

#include "omap_hwmod.h"
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>

#include "omap_hwmod_common_data.h"

#include "control.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
#include "i2c.h"
#include "mmc.h"

/*
 * IP blocks
 */

/*
 * 'emif_fw' class
 * instance(s): emif_fw
 */
static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
	.name		= "emif_fw",
};

/* emif_fw */
static struct omap_hwmod am33xx_emif_fw_hwmod = {
	.name		= "emif_fw",
	.class		= &am33xx_emif_fw_hwmod_class,
	.clkdm_name	= "l4fw_clkdm",
	.main_clk	= "l4fw_gclk",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'emif' class
 * instance(s): emif
 */
static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
	.rev_offs	= 0x0000,
};

static struct omap_hwmod_class am33xx_emif_hwmod_class = {
	.name		= "emif",
	.sysc		= &am33xx_emif_sysc,
};

static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
	{ .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
	{ .irq = -1 },
};

/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
	.name		= "emif",
	.class		= &am33xx_emif_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.mpu_irqs	= am33xx_emif_irqs,
	.main_clk	= "dpll_ddr_m2_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'l3' class
 * instance(s): l3_main, l3_s, l3_instr
 */
static struct omap_hwmod_class am33xx_l3_hwmod_class = {
	.name		= "l3",
};

/* l3_main (l3_fast) */
static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
	{ .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
	{ .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_l3_main_hwmod = {
	.name		= "l3_main",
	.class		= &am33xx_l3_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.mpu_irqs	= am33xx_l3_main_irqs,
	.main_clk	= "l3_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* l3_s */
static struct omap_hwmod am33xx_l3_s_hwmod = {
	.name		= "l3_s",
	.class		= &am33xx_l3_hwmod_class,
	.clkdm_name	= "l3s_clkdm",
};

/* l3_instr */
static struct omap_hwmod am33xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &am33xx_l3_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.main_clk	= "l3_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'l4' class
 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 */
static struct omap_hwmod_class am33xx_l4_hwmod_class = {
	.name		= "l4",
};

/* l4_ls */
static struct omap_hwmod am33xx_l4_ls_hwmod = {
	.name		= "l4_ls",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* l4_hs */
static struct omap_hwmod am33xx_l4_hs_hwmod = {
	.name		= "l4_hs",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4hs_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.main_clk	= "l4hs_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};


/* l4_wkup */
static struct omap_hwmod am33xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* l4_fw */
static struct omap_hwmod am33xx_l4_fw_hwmod = {
	.name		= "l4_fw",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4fw_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'mpu' class
 */
static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
	.name	= "mpu",
};

/* mpu */
static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
	{ .name = "emuint", .irq = 0 + OMAP_INTC_START, },
	{ .name = "commtx", .irq = 1 + OMAP_INTC_START, },
	{ .name = "commrx", .irq = 2 + OMAP_INTC_START, },
	{ .name = "bench", .irq = 3 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &am33xx_mpu_hwmod_class,
	.clkdm_name	= "mpu_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.mpu_irqs	= am33xx_mpu_irqs,
	.main_clk	= "dpll_mpu_m2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'wakeup m3' class
 * Wakeup controller sub-system under wakeup domain
 */
static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
	.name		= "wkup_m3",
};

static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};

static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
	{ .name = "txev", .irq = 78 + OMAP_INTC_START, },
	{ .irq = -1 },
};

/* wkup_m3  */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
	.name		= "wkup_m3",
	.class		= &am33xx_wkup_m3_hwmod_class,
	.clkdm_name	= "l4_wkup_aon_clkdm",
	.flags		= HWMOD_INIT_NO_RESET,	/* Keep hardreset asserted */
	.mpu_irqs	= am33xx_wkup_m3_irqs,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_wkup_m3_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
};

/*
 * 'pru-icss' class
 * Programmable Real-Time Unit and Industrial Communication Subsystem
 */
static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
	.name	= "pruss",
};

static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
	{ .name = "pruss", .rst_shift = 1 },
};

static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
	{ .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
	{ .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
	{ .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
	{ .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
	{ .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
	{ .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
	{ .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
	{ .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
	{ .irq = -1 },
};

/* pru-icss */
/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod am33xx_pruss_hwmod = {
	.name		= "pruss",
	.class		= &am33xx_pruss_hwmod_class,
	.clkdm_name	= "pruss_ocp_clkdm",
	.mpu_irqs	= am33xx_pruss_irqs,
	.main_clk	= "pruss_ocp_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM33XX_RM_PER_RSTCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_pruss_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_pruss_resets),
};

/* gfx */
/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
	.name	= "gfx",
};

static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
	{ .name = "gfx", .rst_shift = 0 },
};

static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
	{ .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_gfx_hwmod = {
	.name		= "gfx",
	.class		= &am33xx_gfx_hwmod_class,
	.clkdm_name	= "gfx_l3_clkdm",
	.mpu_irqs	= am33xx_gfx_irqs,
	.main_clk	= "gfx_fck_div_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_gfx_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_gfx_resets),
};

/*
 * 'prcm' class
 * power and reset manager (whole prcm infrastructure)
 */
static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
	.name	= "prcm",
};

/* prcm */
static struct omap_hwmod am33xx_prcm_hwmod = {
	.name		= "prcm",
	.class		= &am33xx_prcm_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
};

/*
 * 'adc/tsc' class
 * TouchScreen Controller (Anolog-To-Digital Converter)
 */
static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x10,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
	.name		= "adc_tsc",
	.sysc		= &am33xx_adc_tsc_sysc,
};

static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
	{ .irq = 16 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_adc_tsc_hwmod = {
	.name		= "adc_tsc",
	.class		= &am33xx_adc_tsc_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.mpu_irqs	= am33xx_adc_tsc_irqs,
	.main_clk	= "adc_tsc_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *    - cEFUSE (doesn't fall under any ocp_if)
 *    - clkdiv32k
 *    - debugss
 *    - ocmc ram
 *    - ocp watch point
 *    - aes0
 *    - sha0
 */
#if 0
/*
 * 'cefuse' class
 */
static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
	.name		= "cefuse",
};

static struct omap_hwmod am33xx_cefuse_hwmod = {
	.name		= "cefuse",
	.class		= &am33xx_cefuse_hwmod_class,
	.clkdm_name	= "l4_cefuse_clkdm",
	.main_clk	= "cefuse_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'clkdiv32k' class
 */
static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
	.name		= "clkdiv32k",
};

static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
	.name		= "clkdiv32k",
	.class		= &am33xx_clkdiv32k_hwmod_class,
	.clkdm_name	= "clk_24mhz_clkdm",
	.main_clk	= "clkdiv32k_ick",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'debugss' class
 * debug sub system
 */
static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
	.name		= "debugss",
};

static struct omap_hwmod am33xx_debugss_hwmod = {
	.name		= "debugss",
	.class		= &am33xx_debugss_hwmod_class,
	.clkdm_name	= "l3_aon_clkdm",
	.main_clk	= "debugss_ick",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
	.name = "ocmcram",
};

static struct omap_hwmod am33xx_ocmcram_hwmod = {
	.name		= "ocmcram",
	.class		= &am33xx_ocmcram_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.main_clk	= "l3_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
	.name		= "ocpwp",
};

static struct omap_hwmod am33xx_ocpwp_hwmod = {
	.name		= "ocpwp",
	.class		= &am33xx_ocpwp_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'aes' class
 */
static struct omap_hwmod_class am33xx_aes_hwmod_class = {
	.name		= "aes",
};

static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
	{ .irq = 102 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_aes0_hwmod = {
	.name		= "aes0",
	.class		= &am33xx_aes_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.mpu_irqs	= am33xx_aes0_irqs,
	.main_clk	= "l3_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* sha0 */
static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
	.name		= "sha0",
};

static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
	{ .irq = 108 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_sha0_hwmod = {
	.name		= "sha0",
	.class		= &am33xx_sha0_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.mpu_irqs	= am33xx_sha0_irqs,
	.main_clk	= "l3_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

#endif

/* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
	.name		= "smartreflex",
};

/* smartreflex0 */
static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
	{ .irq = 120 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_smartreflex0_hwmod = {
	.name		= "smartreflex0",
	.class		= &am33xx_smartreflex_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.mpu_irqs	= am33xx_smartreflex0_irqs,
	.main_clk	= "smartreflex0_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* smartreflex1 */
static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
	{ .irq = 121 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_smartreflex1_hwmod = {
	.name		= "smartreflex1",
	.class		= &am33xx_smartreflex_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.mpu_irqs	= am33xx_smartreflex1_irqs,
	.main_clk	= "smartreflex1_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'control' module class
 */
static struct omap_hwmod_class am33xx_control_hwmod_class = {
	.name		= "control",
};

static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
	{ .irq = 8 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_control_hwmod = {
	.name		= "control",
	.class		= &am33xx_control_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.mpu_irqs	= am33xx_control_irqs,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'cpgmac' class
 * cpsw/cpgmac sub system
 */
static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x8,
	.syss_offs	= 0x4,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
			   MSTANDBY_NO),
	.sysc_fields	= &omap_hwmod_sysc_type3,
};

static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
	.name		= "cpgmac0",
	.sysc		= &am33xx_cpgmac_sysc,
};

static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
	{ .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
	{ .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
	{ .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
	{ .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_cpgmac0_hwmod = {
	.name		= "cpgmac0",
	.class		= &am33xx_cpgmac0_hwmod_class,
	.clkdm_name	= "cpsw_125mhz_clkdm",
	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
	.mpu_irqs	= am33xx_cpgmac0_irqs,
	.main_clk	= "cpsw_125mhz_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * mdio class
 */
static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
	.name		= "davinci_mdio",
};

static struct omap_hwmod am33xx_mdio_hwmod = {
	.name		= "davinci_mdio",
	.class		= &am33xx_mdio_hwmod_class,
	.clkdm_name	= "cpsw_125mhz_clkdm",
	.main_clk	= "cpsw_125mhz_gclk",
};

/*
 * dcan class
 */
static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
	.name = "d_can",
};

/* dcan0 */
static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
	{ .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
	{ .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_dcan0_hwmod = {
	.name		= "d_can0",
	.class		= &am33xx_dcan_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_dcan0_irqs,
	.main_clk	= "dcan0_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* dcan1 */
static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
	{ .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
	{ .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
	{ .irq = -1 },
};
static struct omap_hwmod am33xx_dcan1_hwmod = {
	.name		= "d_can1",
	.class		= &am33xx_dcan_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_dcan1_irqs,
	.main_clk	= "dcan1_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* elm */
static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am33xx_elm_hwmod_class = {
	.name		= "elm",
	.sysc		= &am33xx_elm_sysc,
};

static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
	{ .irq = 4 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_elm_hwmod = {
	.name		= "elm",
	.class		= &am33xx_elm_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_elm_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
 */
static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x4,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
	.name		= "epwmss",
	.sysc		= &am33xx_epwmss_sysc,
};

/* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
	{ .name = "int", .irq = 86 + OMAP_INTC_START, },
	{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
	.name		= "ehrpwm0",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_ehrpwm0_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
	{ .name = "int", .irq = 87 + OMAP_INTC_START, },
	{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
	.name		= "ehrpwm1",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_ehrpwm1_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
	{ .name = "int", .irq = 39 + OMAP_INTC_START, },
	{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
	.name		= "ehrpwm2",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_ehrpwm2_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ecap0 */
static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
	{ .irq = 31 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ecap0_hwmod = {
	.name		= "ecap0",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_ecap0_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ecap1 */
static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
	{ .irq = 47 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ecap1_hwmod = {
	.name		= "ecap1",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= am33xx_ecap1_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ecap2 */
static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
	{ .irq = 61 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_ecap2_hwmod = {
	.name		= "ecap2",
	.mpu_irqs	= am33xx_ecap2_irqs,
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'gpio' class: for gpio 0,1,2,3
 */
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0114,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			  SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			  SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			  SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
	.name		= "gpio",
	.sysc		= &am33xx_gpio_sysc,
	.rev		= 2,
};

static struct omap_gpio_dev_attr gpio_dev_attr = {
	.bank_width	= 32,
	.dbck_flag	= true,
};

/* gpio0 */
static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio0_dbclk" },
};

static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
	{ .irq = 96 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_gpio0_hwmod = {
	.name		= "gpio1",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= am33xx_gpio0_irqs,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio0_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio1 */
static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
	{ .irq = 98 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio1_dbclk" },
};

static struct omap_hwmod am33xx_gpio1_hwmod = {
	.name		= "gpio2",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= am33xx_gpio1_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio2 */
static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
	{ .irq = 32 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio2_dbclk" },
};

static struct omap_hwmod am33xx_gpio2_hwmod = {
	.name		= "gpio3",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= am33xx_gpio2_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio3 */
static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
	{ .irq = 62 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio3_dbclk" },
};

static struct omap_hwmod am33xx_gpio3_hwmod = {
	.name		= "gpio4",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= am33xx_gpio3_irqs,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.syss_offs	= 0x14,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
	.name		= "gpmc",
	.sysc		= &gpmc_sysc,
};

static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
	{ .irq = 100 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_gpmc_hwmod = {
	.name		= "gpmc",
	.class		= &am33xx_gpmc_hwmod_class,
	.clkdm_name	= "l3s_clkdm",
	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
	.mpu_irqs	= am33xx_gpmc_irqs,
	.main_clk	= "l3s_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* 'i2c' class */
static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0090,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			  SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			  SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &am33xx_i2c_sysc,
	.rev		= OMAP_I2C_IP_VERSION_2,
	.reset		= &omap_i2c_reset,
};

static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};

/* i2c1 */
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
	{ .irq = 70 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
	{ .name = "tx", .dma_req = 0, },
	{ .name = "rx", .dma_req = 0, },
	{ .dma_req = -1 }
};

static struct omap_hwmod am33xx_i2c1_hwmod = {
	.name		= "i2c1",
	.class		= &i2c_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.mpu_irqs	= i2c1_mpu_irqs,
	.sdma_reqs	= i2c1_edma_reqs,
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c1 */
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
	{ .irq = 71 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
	{ .name = "tx", .dma_req = 0, },
	{ .name = "rx", .dma_req = 0, },
	{ .dma_req = -1 }
};

static struct omap_hwmod am33xx_i2c2_hwmod = {
	.name		= "i2c2",
	.class		= &i2c_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= i2c2_mpu_irqs,
	.sdma_reqs	= i2c2_edma_reqs,
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.main_clk	= "dpll_per_m2_div4_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c3 */
static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
	{ .name = "tx", .dma_req = 0, },
	{ .name = "rx", .dma_req = 0, },
	{ .dma_req = -1 }
};

static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
	{ .irq = 30 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod am33xx_i2c3_hwmod = {
	.name		= "i2c3",
	.class		= &i2c_class,
	.clkdm_name	= "l4ls_clkdm",
	.mpu_irqs	= i2c3_mpu_irqs,
	.sdma_reqs	= i2c3_edma_reqs,
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.main_clk	= "dpll_per_m2_div4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};


/* lcdc */
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x54,