aiot/waterDataDiscreteRateMining/varianceCalculation/synchronousMemoryDatabase.c

/*
 * bonito board support
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */

#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/videodev2.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/r8a7740.h>
#include <mach/irqs.h>
#include <video/sh_mobile_lcdc.h>

/*
 * CS	Address		device			note
 *----------------------------------------------------------------
 * 0	0x0000_0000	NOR Flash (64MB)	SW12 : bit3 = OFF
 * 2	0x0800_0000	ExtNOR (64MB)		SW12 : bit3 = OFF
 * 4			-
 * 5A			-
 * 5B	0x1600_0000	SRAM (8MB)
 * 6	0x1800_0000	FPGA (64K)
 *	0x1801_0000	Ether (4KB)
 *	0x1801_1000	USB (4KB)
 */

/*
 * SW12
 *
 *	bit1			bit2			bit3
 *----------------------------------------------------------------------------
 * ON	NOR WriteProtect	NAND WriteProtect	CS0 ExtNOR / CS2 NOR
 * OFF	NOR Not WriteProtect	NAND Not WriteProtect	CS0 NOR    / CS2 ExtNOR
 */

/*
 * SCIFA5 (CN42)
 *
 * S38.3 = ON
 * S39.6 = ON
 * S43.1 = ON
 */

/*
 * LCDC0 (CN3/CN4/CN7)
 *
 * S38.1 = OFF
 * S38.2 = OFF
 */

/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};

/*
 * FPGA
 */
#define IRQSR0		0x0020
#define IRQSR1		0x0022
#define IRQMR0		0x0030
#define IRQMR1		0x0032
#define BUSSWMR1	0x0070
#define BUSSWMR2	0x0072
#define BUSSWMR3	0x0074
#define BUSSWMR4	0x0076

#define LCDCR		0x10B4
#define DEVRSTCR1	0x10D0
#define DEVRSTCR2	0x10D2
#define A1MDSR		0x10E0
#define BVERR		0x1100

/* FPGA IRQ */
#define FPGA_IRQ_BASE		(512)
#define FPGA_IRQ0		(FPGA_IRQ_BASE)
#define FPGA_IRQ1		(FPGA_IRQ_BASE + 16)
#define FPGA_ETH_IRQ		(FPGA_IRQ0 + 15)
static u16 bonito_fpga_read(u32 offset)
{
	return __raw_readw(IOMEM(0xf0003000) + offset);
}

static void bonito_fpga_write(u32 offset, u16 val)
{
	__raw_writew(val, IOMEM(0xf0003000) + offset);
}

static void bonito_fpga_irq_disable(struct irq_data *data)
{
	unsigned int irq = data->irq;
	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	int shift = irq % 16;

	bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
}

static void bonito_fpga_irq_enable(struct irq_data *data)
{
	unsigned int irq = data->irq;
	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	int shift = irq % 16;

	bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
}

static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
	.name		= "bonito FPGA",
	.irq_mask	= bonito_fpga_irq_disable,
	.irq_unmask	= bonito_fpga_irq_enable,
};

static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	u32 val =  bonito_fpga_read(IRQSR1) << 16 |
		   bonito_fpga_read(IRQSR0);
	u32 mask = bonito_fpga_read(IRQMR1) << 16 |
		   bonito_fpga_read(IRQMR0);

	int i;

	val &= ~mask;

	for (i = 0; i < 32; i++) {
		if (!(val & (1 << i)))
			continue;

		generic_handle_irq(FPGA_IRQ_BASE + i);
	}
}

static void bonito_fpga_init(void)
{
	int i;

	bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
	bonito_fpga_write(IRQMR1, 0xffff); /* mask all */

	/* Device reset */
	bonito_fpga_write(DEVRSTCR1,
		   (1 << 2));	/* Eth */

	/* FPGA irq require special handling */
	for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
		irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
					      handle_level_irq, "level");
		set_irq_flags(i, IRQF_VALID); /* yuck */
	}

	irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);