memoryCall.h 14 KB

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  1. #ifndef _IOP13XX_HW_H_
  2. #define _IOP13XX_HW_H_
  3. #ifndef __ASSEMBLY__
  4. /* The ATU offsets can change based on the strapping */
  5. extern u32 iop13xx_atux_pmmr_offset;
  6. extern u32 iop13xx_atue_pmmr_offset;
  7. void iop13xx_init_early(void);
  8. void iop13xx_init_irq(void);
  9. void iop13xx_map_io(void);
  10. void iop13xx_platform_init(void);
  11. void iop13xx_add_tpmi_devices(void);
  12. void iop13xx_init_irq(void);
  13. void iop13xx_restart(char, const char *);
  14. /* CPUID CP6 R0 Page 0 */
  15. static inline int iop13xx_cpu_id(void)
  16. {
  17. int id;
  18. asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
  19. return id;
  20. }
  21. /* WDTCR CP6 R7 Page 9 */
  22. static inline u32 read_wdtcr(void)
  23. {
  24. u32 val;
  25. asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
  26. return val;
  27. }
  28. static inline void write_wdtcr(u32 val)
  29. {
  30. asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
  31. }
  32. /* WDTSR CP6 R8 Page 9 */
  33. static inline u32 read_wdtsr(void)
  34. {
  35. u32 val;
  36. asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
  37. return val;
  38. }
  39. static inline void write_wdtsr(u32 val)
  40. {
  41. asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
  42. }
  43. /* RCSR - Reset Cause Status Register */
  44. static inline u32 read_rcsr(void)
  45. {
  46. u32 val;
  47. asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
  48. return val;
  49. }
  50. extern unsigned long get_iop_tick_rate(void);
  51. #endif
  52. /*
  53. * IOP13XX I/O and Mem space regions for PCI autoconfiguration
  54. */
  55. #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
  56. #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
  57. /* PCI MAP
  58. * bus range cpu phys cpu virt note
  59. * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
  60. * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
  61. * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
  62. *
  63. * IO MAP
  64. * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
  65. * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
  66. */
  67. #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
  68. #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
  69. #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
  70. #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
  71. #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  72. #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
  73. IOP13XX_PCIX_LOWER_MEM_BA)
  74. #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
  75. IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  76. #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
  77. IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  78. #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
  79. #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
  80. #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
  81. IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  82. #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
  83. IOP13XX_PCIX_LOWER_MEM_BA)
  84. /* PCI-E ranges */
  85. #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
  86. #define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
  87. #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
  88. #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
  89. #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  90. #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
  91. IOP13XX_PCIE_LOWER_MEM_BA)
  92. #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
  93. IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  94. #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
  95. IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  96. /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
  97. #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
  98. #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
  99. #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
  100. IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  101. #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
  102. IOP13XX_PCIE_LOWER_MEM_BA)
  103. /* PBI Ranges */
  104. #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
  105. #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
  106. #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
  107. #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
  108. #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
  109. IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
  110. /*
  111. * IOP13XX chipset registers
  112. */
  113. #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
  114. #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
  115. #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
  116. #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
  117. IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
  118. #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
  119. IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
  120. #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
  121. + IOP13XX_PMMR_PHYS_MEM_BASE)
  122. #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
  123. + IOP13XX_PMMR_VIRT_MEM_BASE)
  124. #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
  125. #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
  126. #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
  127. #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
  128. #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
  129. #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
  130. #define IOP13XX_PMMR_SIZE 0x00080000
  131. /*=================== Defines for Platform Devices =====================*/
  132. #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
  133. #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
  134. #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
  135. #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
  136. #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
  137. #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
  138. #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
  139. #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
  140. #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
  141. #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
  142. /* ATU selection flags */
  143. /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
  144. #define IOP13XX_INIT_ATU_DEFAULT (0)
  145. #define IOP13XX_INIT_ATU_ATUX (1 << 0)
  146. #define IOP13XX_INIT_ATU_ATUE (1 << 1)
  147. #define IOP13XX_INIT_ATU_NONE (1 << 2)
  148. /* UART selection flags */
  149. /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
  150. #define IOP13XX_INIT_UART_DEFAULT (0)
  151. #define IOP13XX_INIT_UART_0 (1 << 0)
  152. #define IOP13XX_INIT_UART_1 (1 << 1)
  153. /* I2C selection flags */
  154. /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
  155. #define IOP13XX_INIT_I2C_DEFAULT (0)
  156. #define IOP13XX_INIT_I2C_0 (1 << 0)
  157. #define IOP13XX_INIT_I2C_1 (1 << 1)
  158. #define IOP13XX_INIT_I2C_2 (1 << 2)
  159. /* ADMA selection flags */
  160. /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
  161. #define IOP13XX_INIT_ADMA_DEFAULT (0)
  162. #define IOP13XX_INIT_ADMA_0 (1 << 0)
  163. #define IOP13XX_INIT_ADMA_1 (1 << 1)
  164. #define IOP13XX_INIT_ADMA_2 (1 << 2)
  165. /* Platform devices */
  166. #define IQ81340_NUM_UART 2
  167. #define IQ81340_NUM_I2C 3
  168. #define IQ81340_NUM_PHYS_MAP_FLASH 1
  169. #define IQ81340_NUM_ADMA 3
  170. #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
  171. IQ81340_NUM_I2C + \
  172. IQ81340_NUM_PHYS_MAP_FLASH + \
  173. IQ81340_NUM_ADMA)
  174. /*========================== PMMR offsets for key registers ============*/
  175. #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
  176. #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
  177. #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
  178. #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
  179. #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
  180. #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
  181. #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
  182. #define IOP13XX_MU_PMMR_OFFSET 0x00004000
  183. #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
  184. #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
  185. #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
  186. #define IOP13XX_CONTROLLER_ONLY (1 << 14)
  187. #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
  188. #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
  189. #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
  190. IOP13XX_PMON_PMMR_OFFSET)
  191. #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
  192. IOP13XX_PMON_PMMR_OFFSET)
  193. #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
  194. #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
  195. #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
  196. #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
  197. #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
  198. #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
  199. #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
  200. #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
  201. #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
  202. #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
  203. #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
  204. #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
  205. #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
  206. #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
  207. /*================================ATU===================================*/
  208. #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
  209. iop13xx_atux_pmmr_offset + (ofs))
  210. #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
  211. iop13xx_atux_pmmr_offset + 0x2)
  212. #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
  213. iop13xx_atux_pmmr_offset + 0x4)
  214. #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
  215. iop13xx_atux_pmmr_offset + 0x6)
  216. #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
  217. #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
  218. #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
  219. #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
  220. #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
  221. #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
  222. #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
  223. #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
  224. #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
  225. #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
  226. #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
  227. #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
  228. #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
  229. #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
  230. #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
  231. #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
  232. #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
  233. #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
  234. #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
  235. #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
  236. #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
  237. #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
  238. #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
  239. #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
  240. #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
  241. #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
  242. #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
  243. #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
  244. #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
  245. #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
  246. #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
  247. #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
  248. #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
  249. #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
  250. #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
  251. #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
  252. #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
  253. #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
  254. #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
  255. #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
  256. #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
  257. #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
  258. #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
  259. #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
  260. #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
  261. #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
  262. #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
  263. #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
  264. #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
  265. #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
  266. #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
  267. #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
  268. #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
  269. #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
  270. #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
  271. #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
  272. #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
  273. #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
  274. #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
  275. #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
  276. #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
  277. #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
  278. #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
  279. #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
  280. #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
  281. #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
  282. #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
  283. iop13xx_atue_pmmr_offset + (ofs))
  284. #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
  285. iop13xx_atue_pmmr_offset + 0x2)
  286. #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
  287. iop13xx_atue_pmmr_offset + 0x4)
  288. #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
  289. iop13xx_atue_pmmr_offset + 0x6)
  290. #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
  291. #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
  292. #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
  293. #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
  294. #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
  295. #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
  296. #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
  297. #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
  298. #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
  299. #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
  300. #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
  301. #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
  302. #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)