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- #ifndef _ASM_ARCH_PXA27X_UDC_H
- #define _ASM_ARCH_PXA27X_UDC_H
- #ifdef _ASM_ARCH_PXA25X_UDC_H
- #error You cannot include both PXA25x and PXA27x UDC support
- #endif
- #define UDCCR __REG(0x40600000) /* UDC Control Register */
- #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
- #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
- Protocol Port Support */
- #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
- Support */
- #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
- Enable */
- #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
- #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
- #define UDCCR_ACN_S 11
- #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
- #define UDCCR_AIN_S 8
- #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
- Setting Number */
- #define UDCCR_AAISN_S 5
- #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
- Configuration */
- #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
- Error */
- #define UDCCR_UDR (1 << 2) /* UDC Resume */
- #define UDCCR_UDA (1 << 1) /* UDC Active */
- #define UDCCR_UDE (1 << 0) /* UDC Enable */
- #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
- #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
- #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
- #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
- #define UDC_INT_FIFOERROR (0x2)
- #define UDC_INT_PACKETCMP (0x1)
- #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
- #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
- #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
- #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
- #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
- #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
- #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
- #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
- #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
- #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
- #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
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