aiot/efDataDiscreteRateMining/averageCalculation/calculationOfAverageTemperature.h

/*
 * AM33XX Power Management register bits
 *
 * This file is automatically generated from the AM33XX hardware databases.
 * Vaibhav Hiremath <hvaibhav@ti.com>
 *
 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */


#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H

/*
 * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
 */
#define AM33XX_AUTO_DPLL_MODE_SHIFT			0
#define AM33XX_AUTO_DPLL_MODE_WIDTH			3
#define AM33XX_AUTO_DPLL_MODE_MASK			(0x7 << 0)

/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT		14
#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK		(1 << 16)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT		11
#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH		1
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK			(1 << 11)

/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT		4
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK		(1 << 4)

/* Used by CM_PER_CPSW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT	4
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH	1
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK	(1 << 4)

/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT	4
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH	1
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK	(1 << 4)

/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT	5
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH	1
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK		(1 << 5)

/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT		6
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK		(1 << 6)

/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT		6
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK		(1 << 6)

/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT	9
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH	1
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK	(1 << 9)

/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT		2
#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK		(1 << 2)

/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT		4
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH		1
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK		(1 << 4)

/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT		2
#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK		(1 << 2)

/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT		9
#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK		(1 << 9)

/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT		8
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK		(1 << 8)

/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT		8
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK		(1 << 8)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT		19
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK		(1 << 19)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT		20
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK		(1 << 20)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT		21
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK		(1 << 21)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT		22
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK		(1 << 22)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT		26
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK		(1 << 26)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT		18
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK		(1 << 18)

/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT		11
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK		(1 << 11)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT		24
#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK		(1 << 24)

/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT		5
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK		(1 << 5)

/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT		4
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK		(1 << 4)

/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT	6
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH	1
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK		(1 << 6)

/* Used by CM_PER_L3S_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT		3
#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK		(1 << 3)

/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT		3
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK		(1 << 3)

/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT		4
#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK			(1 << 4)

/* Used by CM_PER_L4FW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT		8
#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK		(1 << 8)

/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT		3
#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK		(1 << 3)

/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT		8
#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK		(1 << 8)

/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT		8
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH		1
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK		(1 << 8)