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waterDataPreprocessing
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monitoringDataProcessing
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connectTheSignalSlot.h

connectTheSignalSlot.h 3.1 KB
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  1. /*
    2. 

  2.  * Analog Devices SPI3 controller driver
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2011 Analog Devices Inc.
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  *
    10. 

  10.  * This program is distributed in the hope that it will be useful,
    11. 

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13.  * GNU General Public License for more details.
    14. 

  14.  *
    15. 

  15.  * You should have received a copy of the GNU General Public License
    16. 

  16.  * along with this program; if not, write to the Free Software
    17. 

  17.  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
    18. 

  18.  */
    19. 

  19. 

  20. #ifndef _SPI_CHANNEL_H_
    21. 

  21. #define _SPI_CHANNEL_H_
    22. 

  22. 

  23. #include <linux/types.h>
    24. 

  24. 

  25. /* SPI_CONTROL */
    26. 

  26. #define SPI_CTL_EN                  0x00000001    /* Enable */
    27. 

  27. #define SPI_CTL_MSTR                0x00000002    /* Master/Slave */
    28. 

  28. #define SPI_CTL_PSSE                0x00000004    /* controls modf error in master mode */
    29. 

  29. #define SPI_CTL_ODM                 0x00000008    /* Open Drain Mode */
    30. 

  30. #define SPI_CTL_CPHA                0x00000010    /* Clock Phase */
    31. 

  31. #define SPI_CTL_CPOL                0x00000020    /* Clock Polarity */
    32. 

  32. #define SPI_CTL_ASSEL               0x00000040    /* Slave Select Pin Control */
    33. 

  33. #define SPI_CTL_SELST               0x00000080    /* Slave Select Polarity in-between transfers */
    34. 

  34. #define SPI_CTL_EMISO               0x00000100    /* Enable MISO */
    35. 

  35. #define SPI_CTL_SIZE                0x00000600    /* Word Transfer Size */
    36. 

  36. #define SPI_CTL_SIZE08              0x00000000    /* SIZE: 8 bits */
    37. 

  37. #define SPI_CTL_SIZE16              0x00000200    /* SIZE: 16 bits */
    38. 

  38. #define SPI_CTL_SIZE32              0x00000400    /* SIZE: 32 bits */
    39. 

  39. #define SPI_CTL_LSBF                0x00001000    /* LSB First */
    40. 

  40. #define SPI_CTL_FCEN                0x00002000    /* Flow-Control Enable */
    41. 

  41. #define SPI_CTL_FCCH                0x00004000    /* Flow-Control Channel Selection */
    42. 

  42. #define SPI_CTL_FCPL                0x00008000    /* Flow-Control Polarity */
    43. 

  43. #define SPI_CTL_FCWM                0x00030000    /* Flow-Control Water-Mark */
    44. 

  44. #define SPI_CTL_FIFO0               0x00000000    /* FCWM: TFIFO empty or RFIFO Full */
    45. 

  45. #define SPI_CTL_FIFO1               0x00010000    /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
    46. 

  46. #define SPI_CTL_FIFO2               0x00020000    /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
    47. 

  47. #define SPI_CTL_FMODE               0x00040000    /* Fast-mode Enable */
    48. 

  48. #define SPI_CTL_MIOM                0x00300000    /* Multiple I/O Mode */
    49. 

  49. #define SPI_CTL_MIO_DIS             0x00000000    /* MIOM: Disable */
    50. 

  50. #define SPI_CTL_MIO_DUAL            0x00100000    /* MIOM: Enable DIOM (Dual I/O Mode) */
    51. 

  51. #define SPI_CTL_MIO_QUAD            0x00200000    /* MIOM: Enable QUAD (Quad SPI Mode) */
    52. 

  52. #define SPI_CTL_SOSI                0x00400000    /* Start on MOSI */
    53. 

  53. /* SPI_RX_CONTROL */
    54. 

  54. #define SPI_RXCTL_REN               0x00000001    /* Receive Channel Enable */
    55. 

  55. #define SPI_RXCTL_RTI               0x00000004    /* Receive Transfer Initiate */
    56. 

  56. #define SPI_RXCTL_RWCEN             0x00000008    /* Receive Word Counter Enable */
    57.