aiot/waterDataStatistics/alarmDataCalculation/synchronousMemoryDatabase.c

/*
 * Hardware modules present on the OMAP44xx chips
 *
 * Copyright (C) 2009-2012 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Benoit Cousson
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/i2c-omap.h>

#include <linux/omap-dma.h>

#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/iommu-omap.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"

/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START	32

/* Base offset for all OMAP4 dma requests */
#define OMAP44XX_DMA_REQ_START	1

/*
 * IP blocks
 */

/*
 * 'c2c_target_fw' class
 * instance(s): c2c_target_fw
 */
static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
	.name	= "c2c_target_fw",
};

/* c2c_target_fw */
static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
	.name		= "c2c_target_fw",
	.class		= &omap44xx_c2c_target_fw_hwmod_class,
	.clkdm_name	= "d2d_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'dmm' class
 * instance(s): dmm
 */
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
	.name	= "dmm",
};

/* dmm */
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod omap44xx_dmm_hwmod = {
	.name		= "dmm",
	.class		= &omap44xx_dmm_hwmod_class,
	.clkdm_name	= "l3_emif_clkdm",
	.mpu_irqs	= omap44xx_dmm_irqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'emif_fw' class
 * instance(s): emif_fw
 */
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
	.name	= "emif_fw",
};

/* emif_fw */
static struct omap_hwmod omap44xx_emif_fw_hwmod = {
	.name		= "emif_fw",
	.class		= &omap44xx_emif_fw_hwmod_class,
	.clkdm_name	= "l3_emif_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 */
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
	.name	= "l3",
};

/* l3_instr */
static struct omap_hwmod omap44xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &omap44xx_l3_hwmod_class,
	.clkdm_name	= "l3_instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* l3_main_1 */
static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
	{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
	{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
	.name		= "l3_main_1",
	.class		= &omap44xx_l3_hwmod_class,
	.clkdm_name	= "l3_1_clkdm",
	.mpu_irqs	= omap44xx_l3_main_1_irqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
		},
	},
};

/* l3_main_2 */
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
	.name		= "l3_main_2",
	.class		= &omap44xx_l3_hwmod_class,
	.clkdm_name	= "l3_2_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
		},
	},
};

/* l3_main_3 */
static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
	.name		= "l3_main_3",
	.class		= &omap44xx_l3_hwmod_class,
	.clkdm_name	= "l3_instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'l4' class
 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 */
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
	.name	= "l4",
};

/* l4_abe */
static struct omap_hwmod omap44xx_l4_abe_hwmod = {
	.name		= "l4_abe",
	.class		= &omap44xx_l4_hwmod_class,
	.clkdm_name	= "abe_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
			.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
			.flags	      = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/* l4_cfg */
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
	.name		= "l4_cfg",
	.class		= &omap44xx_l4_hwmod_class,
	.clkdm_name	= "l4_cfg_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
		},
	},
};

/* l4_per */
static struct omap_hwmod omap44xx_l4_per_hwmod = {
	.name		= "l4_per",
	.class		= &omap44xx_l4_hwmod_class,
	.clkdm_name	= "l4_per_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
		},
	},
};

/* l4_wkup */
static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &omap44xx_l4_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'mpu_bus' class
 * instance(s): mpu_private
 */
static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
	.name	= "mpu_bus",
};

/* mpu_private */
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
	.name		= "mpu_private",
	.class		= &omap44xx_mpu_bus_hwmod_class,
	.clkdm_name	= "mpuss_clkdm",
	.prcm = {
		.omap4 = {
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/*
 * 'ocp_wp_noc' class
 * instance(s): ocp_wp_noc
 */
static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
	.name	= "ocp_wp_noc",
};

/* ocp_wp_noc */
static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
	.name		= "ocp_wp_noc",
	.class		= &omap44xx_ocp_wp_noc_hwmod_class,
	.clkdm_name	= "l3_instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 * usim
 */

/*
 * 'aess' class
 * audio engine sub system
 */

static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
			   MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
	.name	= "aess",
	.sysc	= &omap44xx_aess_sysc,
};

/* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
	{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
	{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod omap44xx_aess_hwmod = {
	.name		= "aess",
	.class		= &omap44xx_aess_hwmod_class,
	.clkdm_name	= "abe_clkdm",
	.mpu_irqs	= omap44xx_aess_irqs,
	.sdma_reqs	= omap44xx_aess_sdma_reqs,
	.main_clk	= "aess_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
			.lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'c2c' class
 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 * soc
 */

static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
	.name	= "c2c",
};

/* c2c */
static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
	{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
	{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod omap44xx_c2c_hwmod = {
	.name		= "c2c",
	.class		= &omap44xx_c2c_hwmod_class,
	.clkdm_name	= "d2d_clkdm",
	.mpu_irqs	= omap44xx_c2c_irqs,
	.sdma_reqs	= omap44xx_c2c_sdma_reqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'counter' class
 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 */

static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0004,