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							- /*
 
-  * Copyright 2005-2010 Analog Devices Inc.
 
-  *
 
-  * Licensed under the GPL-2 or later
 
-  */
 
- #ifndef _CDEF_BF532_H
 
- #define _CDEF_BF532_H
 
- /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
 
- #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
 
- #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 
- #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
 
- #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
 
- #define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
 
- #define bfin_read_CHIPID()                   bfin_read32(CHIPID)
 
- #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 
- #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 
- #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
 
- /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
 
- #define bfin_read_SWRST()                    bfin_read16(SWRST)
 
- #define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
 
- #define bfin_read_SYSCR()                    bfin_read16(SYSCR)
 
- #define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
 
- #define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
 
- #define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
 
- #define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
 
- #define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
 
- #define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
 
- #define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
 
- #define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
 
- #define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
 
- #define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
 
- #define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
 
- #define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
 
- #define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
 
- #define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
 
- #define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
 
- /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
 
- #define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
 
- #define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
 
- #define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
 
- #define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
 
- #define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
 
 
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