Home Esplora Aiuto
Accedi
lixinru
/
aiot
1
0
Forka 0
File Problemi 0 Pull Requests 0 Wiki
Albero (Tree): 1464bfc817
Rami (Branch) Tag
aiot
/
efDataDiscreteRateMining
/
averageCalculation
/
averageVoltageCalculation.h

averageVoltageCalculation.h 4.8 KB
Cronologia Originale

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103 
  1. /*
    2. 

  2.  * AM33XX CM offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
    5. 

  5.  * Vaibhav Hiremath <hvaibhav@ti.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or
    8. 

  8.  * modify it under the terms of the GNU General Public License as
    9. 

  9.  * published by the Free Software Foundation version 2.
    10. 

  10.  *
    11. 

  11.  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
    12. 

  12.  * kind, whether express or implied; without even the implied warranty
    13. 

  13.  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    14. 

  14.  * GNU General Public License for more details.
    15. 

  15.  */
    16. 

  16. 

  17. #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
    18. 

  18. #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
    19. 

  19. 

  20. #include <linux/delay.h>
    21. 

  21. #include <linux/errno.h>
    22. 

  22. #include <linux/err.h>
    23. 

  23. #include <linux/io.h>
    24. 

  24. 

  25. #include "common.h"
    26. 

  26. 

  27. #include "cm.h"
    28. 

  28. #include "cm-regbits-33xx.h"
    29. 

  29. #include "cm33xx.h"
    30. 

  30. 

  31. /* CM base address */
    32. 

  32. #define AM33XX_CM_BASE		0x44e00000
    33. 

  33. 

  34. #define AM33XX_CM_REGADDR(inst, reg)				\
    35. 

  35. 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
    36. 

  36. 

  37. /* CM instances */
    38. 

  38. #define AM33XX_CM_PER_MOD		0x0000
    39. 

  39. #define AM33XX_CM_WKUP_MOD		0x0400
    40. 

  40. #define AM33XX_CM_DPLL_MOD		0x0500
    41. 

  41. #define AM33XX_CM_MPU_MOD		0x0600
    42. 

  42. #define AM33XX_CM_DEVICE_MOD		0x0700
    43. 

  43. #define AM33XX_CM_RTC_MOD		0x0800
    44. 

  44. #define AM33XX_CM_GFX_MOD		0x0900
    45. 

  45. #define AM33XX_CM_CEFUSE_MOD		0x0A00
    46. 

  46. 

  47. /* CM */
    48. 

  48. 

  49. /* CM.PER_CM register offsets */
    50. 

  50. #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
    51. 

  51. #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
    52. 

  52. #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
    53. 

  53. #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
    54. 

  54. #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
    55. 

  55. #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
    56. 

  56. #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
    57. 

  57. #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
    58. 

  58. #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
    59. 

  59. #define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
    60. 

  60. #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
    61. 

  61. #define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
    62. 

  62. #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
    63. 

  63. #define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
    64. 

  64. #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
    65. 

  65. #define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
    66. 

  66. #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
    67. 

  67. #define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
    68. 

  68. #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
    69. 

  69. #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
    70. 

  70. #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
    71. 

  71. #define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
    72. 

  72. #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
    73. 

  73. #define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
    74. 

  74. #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
    75. 

  75. #define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
    76. 

  76. #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
    77. 

  77. #define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
    78. 

  78. #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
    79. 

  79. #define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
    80. 

  80. #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
    81. 

  81. #define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
    82. 

  82. #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
    83. 

  83. #define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
    84. 

  84. #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
    85. 

  85. #define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
    86. 

  86. #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
    87. 

  87. #define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
    88. 

  88. #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
    89. 

  89. #define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
    90. 

  90. #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
    91. 

  91. #define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
    92. 

  92. #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
    93. 

  93. #define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
    94. 

  94. #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
    95. 

  95. #define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
    96. 

  96. #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
    97. 

  97. #define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
    98. 

  98. #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
    99. 

  99. #define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
    100. 

  100. #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
    101. 

  101. #define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
    102. 

  102. #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
    103. 

  103. #define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
    104.