| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100 |
- /*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF542_H
- #define _DEF_BF542_H
- /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
- #include "defBF54x_base.h"
- /* The following are the #defines needed by ADSP-BF542 that are not in the common header */
- /* ATAPI Registers */
- #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
- #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
- #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
- #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
- #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
- #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
- #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
- #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
- #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
- #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
- #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
- #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
- #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
- #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
- #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
- #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
- #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
- #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
- #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
- #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
- #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
- #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
- #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
- #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
- #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
- /* SDH Registers */
- #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
- #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
- #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
- #define SDH_COMMAND 0xffc0390c /* SDH Command */
- #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
- #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
- #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
- #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
- #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
- #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
- #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
- #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
- #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
- #define SDH_STATUS 0xffc03934 /* SDH Status */
- #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
- #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
- #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
- #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
- #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
- #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
- #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
- #define SDH_CFG 0xffc039c8 /* SDH Configuration */
- #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
- #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
- #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
- #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
- #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
- #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
- #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
- #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
- #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
- /* USB Control Registers */
- #define USB_FADDR 0xffc03c00 /* Function address register */
- #define USB_POWER 0xffc03c04 /* Power management register */
- #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
- #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
- #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
- #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
- #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
- #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
- #define USB_FRAME 0xffc03c20 /* USB frame number */
- #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
- #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
- #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
- #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
- /* USB Packet Control Registers */
- #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
- #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
- #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
- #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
- #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
- #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
