Home Explore Help
Sign In
lixinru
/
aiot
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 106f10c345
Branches Tags
aiot
/
efDataStatistics
/
dataSharedMemory
/
statisticsMemoryDefinition.h

statisticsMemoryDefinition.h 5.6 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165 
  1. /*
    2. 

  2.  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
    3. 

  3.  *		http://www.samsung.com
    4. 

  4.  *
    5. 

  5.  * EXYNOS - IRQ definitions
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License version 2 as
    9. 

  9.  * published by the Free Software Foundation.
    10. 

  10. */
    11. 

  11. 

  12. #ifndef __ASM_ARCH_IRQS_H
    13. 

  13. #define __ASM_ARCH_IRQS_H __FILE__
    14. 

  14. 

  15. #include <plat/irqs.h>
    16. 

  16. 

  17. /* PPI: Private Peripheral Interrupt */
    18. 

  18. 

  19. #define IRQ_PPI(x)			(x + 16)
    20. 

  20. 

  21. /* SPI: Shared Peripheral Interrupt */
    22. 

  22. 

  23. #define IRQ_SPI(x)			(x + 32)
    24. 

  24. 

  25. /* COMBINER */
    26. 

  26. 

  27. #define MAX_IRQ_IN_COMBINER		8
    28. 

  28. #define COMBINER_GROUP(x)		((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
    29. 

  29. #define COMBINER_IRQ(x, y)		(COMBINER_GROUP(x) + y)
    30. 

  30. 

  31. /* For EXYNOS4 and EXYNOS5 */
    32. 

  32. 

  33. #define EXYNOS_IRQ_MCT_LOCALTIMER	IRQ_PPI(12)
    34. 

  34. 

  35. #define EXYNOS_IRQ_EINT16_31		IRQ_SPI(32)
    36. 

  36. 

  37. /* For EXYNOS4 SoCs */
    38. 

  38. 

  39. #define EXYNOS4_IRQ_EINT0		IRQ_SPI(16)
    40. 

  40. #define EXYNOS4_IRQ_EINT1		IRQ_SPI(17)
    41. 

  41. #define EXYNOS4_IRQ_EINT2		IRQ_SPI(18)
    42. 

  42. #define EXYNOS4_IRQ_EINT3		IRQ_SPI(19)
    43. 

  43. #define EXYNOS4_IRQ_EINT4		IRQ_SPI(20)
    44. 

  44. #define EXYNOS4_IRQ_EINT5		IRQ_SPI(21)
    45. 

  45. #define EXYNOS4_IRQ_EINT6		IRQ_SPI(22)
    46. 

  46. #define EXYNOS4_IRQ_EINT7		IRQ_SPI(23)
    47. 

  47. #define EXYNOS4_IRQ_EINT8		IRQ_SPI(24)
    48. 

  48. #define EXYNOS4_IRQ_EINT9		IRQ_SPI(25)
    49. 

  49. #define EXYNOS4_IRQ_EINT10		IRQ_SPI(26)
    50. 

  50. #define EXYNOS4_IRQ_EINT11		IRQ_SPI(27)
    51. 

  51. #define EXYNOS4_IRQ_EINT12		IRQ_SPI(28)
    52. 

  52. #define EXYNOS4_IRQ_EINT13		IRQ_SPI(29)
    53. 

  53. #define EXYNOS4_IRQ_EINT14		IRQ_SPI(30)
    54. 

  54. #define EXYNOS4_IRQ_EINT15		IRQ_SPI(31)
    55. 

  55. 

  56. #define EXYNOS4_IRQ_MDMA0		IRQ_SPI(33)
    57. 

  57. #define EXYNOS4_IRQ_MDMA1		IRQ_SPI(34)
    58. 

  58. #define EXYNOS4_IRQ_PDMA0		IRQ_SPI(35)
    59. 

  59. #define EXYNOS4_IRQ_PDMA1		IRQ_SPI(36)
    60. 

  60. #define EXYNOS4_IRQ_TIMER0_VIC		IRQ_SPI(37)
    61. 

  61. #define EXYNOS4_IRQ_TIMER1_VIC		IRQ_SPI(38)
    62. 

  62. #define EXYNOS4_IRQ_TIMER2_VIC		IRQ_SPI(39)
    63. 

  63. #define EXYNOS4_IRQ_TIMER3_VIC		IRQ_SPI(40)
    64. 

  64. #define EXYNOS4_IRQ_TIMER4_VIC		IRQ_SPI(41)
    65. 

  65. #define EXYNOS4_IRQ_MCT_L0		IRQ_SPI(42)
    66. 

  66. #define EXYNOS4_IRQ_WDT			IRQ_SPI(43)
    67. 

  67. #define EXYNOS4_IRQ_RTC_ALARM		IRQ_SPI(44)
    68. 

  68. #define EXYNOS4_IRQ_RTC_TIC		IRQ_SPI(45)
    69. 

  69. #define EXYNOS4_IRQ_GPIO_XB		IRQ_SPI(46)
    70. 

  70. #define EXYNOS4_IRQ_GPIO_XA		IRQ_SPI(47)
    71. 

  71. #define EXYNOS4_IRQ_MCT_L1		IRQ_SPI(48)
    72. 

  72. 

  73. #define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
    74. 

  74. #define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
    75. 

  75. #define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
    76. 

  76. #define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
    77. 

  77. #define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
    78. 

  78. #define EXYNOS4_IRQ_MCT_G0		IRQ_SPI(57)
    79. 

  79. #define EXYNOS4_IRQ_IIC			IRQ_SPI(58)
    80. 

  80. #define EXYNOS4_IRQ_IIC1		IRQ_SPI(59)
    81. 

  81. #define EXYNOS4_IRQ_IIC2		IRQ_SPI(60)
    82. 

  82. #define EXYNOS4_IRQ_IIC3		IRQ_SPI(61)
    83. 

  83. #define EXYNOS4_IRQ_IIC4		IRQ_SPI(62)
    84. 

  84. #define EXYNOS4_IRQ_IIC5		IRQ_SPI(63)
    85. 

  85. #define EXYNOS4_IRQ_IIC6		IRQ_SPI(64)
    86. 

  86. #define EXYNOS4_IRQ_IIC7		IRQ_SPI(65)
    87. 

  87. #define EXYNOS4_IRQ_SPI0		IRQ_SPI(66)
    88. 

  88. #define EXYNOS4_IRQ_SPI1		IRQ_SPI(67)
    89. 

  89. #define EXYNOS4_IRQ_SPI2		IRQ_SPI(68)
    90. 

  90. 

  91. #define EXYNOS4_IRQ_USB_HOST		IRQ_SPI(70)
    92. 

  92. #define EXYNOS4_IRQ_USB_HSOTG		IRQ_SPI(71)
    93. 

  93. #define EXYNOS4_IRQ_MODEM_IF		IRQ_SPI(72)
    94. 

  94. #define EXYNOS4_IRQ_HSMMC0		IRQ_SPI(73)
    95. 

  95. #define EXYNOS4_IRQ_HSMMC1		IRQ_SPI(74)
    96. 

  96. #define EXYNOS4_IRQ_HSMMC2		IRQ_SPI(75)
    97. 

  97. #define EXYNOS4_IRQ_HSMMC3		IRQ_SPI(76)
    98. 

  98. #define EXYNOS4_IRQ_DWMCI		IRQ_SPI(77)
    99. 

  99. 

  100. #define EXYNOS4_IRQ_MIPI_CSIS0		IRQ_SPI(78)
    101. 

  101. #define EXYNOS4_IRQ_MIPI_CSIS1		IRQ_SPI(80)
    102. 

  102. 

  103. #define EXYNOS4_IRQ_ONENAND_AUDI	IRQ_SPI(82)
    104. 

  104. #define EXYNOS4_IRQ_ROTATOR		IRQ_SPI(83)
    105. 

  105. #define EXYNOS4_IRQ_FIMC0		IRQ_SPI(84)
    106. 

  106. #define EXYNOS4_IRQ_FIMC1		IRQ_SPI(85)
    107. 

  107. #define EXYNOS4_IRQ_FIMC2		IRQ_SPI(86)
    108. 

  108. #define EXYNOS4_IRQ_FIMC3		IRQ_SPI(87)
    109. 

  109. #define EXYNOS4_IRQ_JPEG		IRQ_SPI(88)
    110. 

  110. #define EXYNOS4_IRQ_2D			IRQ_SPI(89)
    111. 

  111. #define EXYNOS4_IRQ_PCIE		IRQ_SPI(90)
    112. 

  112. 

  113. #define EXYNOS4_IRQ_MIXER		IRQ_SPI(91)
    114. 

  114. #define EXYNOS4_IRQ_HDMI		IRQ_SPI(92)
    115. 

  115. #define EXYNOS4_IRQ_IIC_HDMIPHY		IRQ_SPI(93)
    116. 

  116. #define EXYNOS4_IRQ_MFC			IRQ_SPI(94)
    117. 

  117. #define EXYNOS4_IRQ_SDO			IRQ_SPI(95)
    118. 

  118. 

  119. #define EXYNOS4_IRQ_AUDIO_SS		IRQ_SPI(96)
    120. 

  120. #define EXYNOS4_IRQ_I2S0		IRQ_SPI(97)
    121. 

  121. #define EXYNOS4_IRQ_I2S1		IRQ_SPI(98)
    122. 

  122. #define EXYNOS4_IRQ_I2S2		IRQ_SPI(99)
    123. 

  123. #define EXYNOS4_IRQ_AC97		IRQ_SPI(100)
    124. 

  124. 

  125. #define EXYNOS4_IRQ_SPDIF		IRQ_SPI(104)
    126. 

  126. #define EXYNOS4_IRQ_ADC0		IRQ_SPI(105)
    127. 

  127. #define EXYNOS4_IRQ_PEN0		IRQ_SPI(106)
    128. 

  128. #define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
    129. 

  129. #define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
    130. 

  130. #define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
    131. 

  131. #define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
    132. 

  132. #define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
    133. 

  133. #define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
    134. 

  134. #define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
    135. 

  135. 

  136. #define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
    137. 

  137. #define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
    138. 

  138. 

  139. #define EXYNOS4_IRQ_TMU_TRIG0		COMBINER_IRQ(2, 4)
    140. 

  140. #define EXYNOS4_IRQ_TMU_TRIG1		COMBINER_IRQ(3, 4)
    141. 

  141. 

  142. #define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
    143. 

  143. #define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
    144. 

  144. #define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
    145. 

  145. #define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
    146. 

  146. #define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
    147. 

  147. #define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
    148. 

  148. #define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
    149. 

  149. #define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
    150. 

  150. 

  151. #define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
    152. 

  152. #define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
    153. 

  153. #define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
    154. 

  154. #define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
    155. 

  155. #define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
    156. 

  156. #define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
    157. 

  157. #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
    158. 

  158. #define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
    159. 

  159. 

  160. #define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0	COMBINER_IRQ(16, 0)
    161. 

  161. #define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0	COMBINER_IRQ(16, 1)
    162. 

  162. #define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0	COMBINER_IRQ(16, 2)
    163. 

  163. #define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0	COMBINER_IRQ(16, 3)
    164. 

  164. #define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0	COMBINER_IRQ(16, 4)
    165. 

  165. #define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0	COMBINER_IRQ(16, 5)
    166.