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waterDataDiscreteRateMining
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averageCalculation
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averageValueOfWaterPressure.h

averageValueOfWaterPressure.h 8.4 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *	m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *	(C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
    7. 

  7.  */
    8. 

  8. 

  9. /****************************************************************************/
    10. 

  10. #ifndef	m527xsim_h
    11. 

  11. #define	m527xsim_h
    12. 

  12. /****************************************************************************/
    13. 

  13. 

  14. #define	CPU_NAME		"COLDFIRE(m527x)"
    15. 

  15. #define	CPU_INSTR_PER_JIFFY	3
    16. 

  16. #define	MCF_BUSCLK		(MCF_CLK / 2)
    17. 

  17. 

  18. #include <asm/m52xxacr.h>
    19. 

  19. 

  20. /*
    21. 

  21.  *	Define the 5270/5271 SIM register set addresses.
    22. 

  22.  */
    23. 

  23. #define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
    24. 

  24. #define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 1 */
    25. 

  25. 

  26. #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
    27. 

  27. #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
    28. 

  28. #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
    29. 

  29. #define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
    30. 

  30. #define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
    31. 

  31. #define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
    32. 

  32. #define	MCFINTC_IRLR		0x18		/* */
    33. 

  33. #define	MCFINTC_IACKL		0x19		/* */
    34. 

  34. #define	MCFINTC_ICR0		0x40		/* Base ICR register */
    35. 

  35. 

  36. #define	MCFINT_VECBASE		64		/* Vector base number */
    37. 

  37. #define	MCFINT_UART0		13		/* Interrupt number for UART0 */
    38. 

  38. #define	MCFINT_UART1		14		/* Interrupt number for UART1 */
    39. 

  39. #define	MCFINT_UART2		15		/* Interrupt number for UART2 */
    40. 

  40. #define	MCFINT_QSPI		18		/* Interrupt number for QSPI */
    41. 

  41. #define	MCFINT_FECRX0		23		/* Interrupt number for FEC0 */
    42. 

  42. #define	MCFINT_FECTX0		27		/* Interrupt number for FEC0 */
    43. 

  43. #define	MCFINT_FECENTC0		29		/* Interrupt number for FEC0 */
    44. 

  44. #define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */
    45. 

  45. 

  46. #define	MCFINT2_VECBASE		128		/* Vector base number 2 */
    47. 

  47. #define	MCFINT2_FECRX1		23		/* Interrupt number for FEC1 */
    48. 

  48. #define	MCFINT2_FECTX1		27		/* Interrupt number for FEC1 */
    49. 

  49. #define	MCFINT2_FECENTC1	29		/* Interrupt number for FEC1 */
    50. 

  50. 

  51. #define	MCF_IRQ_UART0	        (MCFINT_VECBASE + MCFINT_UART0)
    52. 

  52. #define	MCF_IRQ_UART1	        (MCFINT_VECBASE + MCFINT_UART1)
    53. 

  53. #define	MCF_IRQ_UART2	        (MCFINT_VECBASE + MCFINT_UART2)
    54. 

  54. 

  55. #define	MCF_IRQ_FECRX0		(MCFINT_VECBASE + MCFINT_FECRX0)
    56. 

  56. #define	MCF_IRQ_FECTX0		(MCFINT_VECBASE + MCFINT_FECTX0)
    57. 

  57. #define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)
    58. 

  58. #define	MCF_IRQ_FECRX1		(MCFINT2_VECBASE + MCFINT2_FECRX1)
    59. 

  59. #define	MCF_IRQ_FECTX1		(MCFINT2_VECBASE + MCFINT2_FECTX1)
    60. 

  60. #define	MCF_IRQ_FECENTC1	(MCFINT2_VECBASE + MCFINT2_FECENTC1)
    61. 

  61. 

  62. #define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)
    63. 

  63. #define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)
    64. 

  64. 

  65. /*
    66. 

  66.  *	SDRAM configuration registers.
    67. 

  67.  */
    68. 

  68. #ifdef CONFIG_M5271
    69. 

  69. #define	MCFSIM_DCR		(MCF_IPSBAR + 0x40)	/* Control */
    70. 

  70. #define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */
    71. 

  71. #define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */
    72. 

  72. #define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */
    73. 

  73. #define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */
    74. 

  74. #endif
    75. 

  75. #ifdef CONFIG_M5275
    76. 

  76. #define	MCFSIM_DMR		(MCF_IPSBAR + 0x40)	/* Mode */
    77. 

  77. #define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */
    78. 

  78. #define	MCFSIM_DCFG1		(MCF_IPSBAR + 0x48)	/* Configuration 1 */
    79. 

  79. #define	MCFSIM_DCFG2		(MCF_IPSBAR + 0x4c)	/* Configuration 2 */
    80. 

  80. #define	MCFSIM_DBAR0		(MCF_IPSBAR + 0x50)	/* Base address 0 */
    81. 

  81. #define	MCFSIM_DMR0		(MCF_IPSBAR + 0x54)	/* Address mask 0 */
    82. 

  82. #define	MCFSIM_DBAR1		(MCF_IPSBAR + 0x58)	/* Base address 1 */
    83. 

  83. #define	MCFSIM_DMR1		(MCF_IPSBAR + 0x5c)	/* Address mask 1 */
    84. 

  84. #endif
    85. 

  85. 

  86. /*
    87. 

  87.  *	DMA unit base addresses.
    88. 

  88.  */
    89. 

  89. #define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)
    90. 

  90. #define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)
    91. 

  91. #define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)
    92. 

  92. #define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)
    93. 

  93. 

  94. /*
    95. 

  95.  *	UART module.
    96. 

  96.  */
    97. 

  97. #define MCFUART_BASE0		(MCF_IPSBAR + 0x200)
    98. 

  98. #define MCFUART_BASE1		(MCF_IPSBAR + 0x240)
    99. 

  99. #define MCFUART_BASE2		(MCF_IPSBAR + 0x280)
    100. 

  100. 

  101. /*
    102. 

  102.  *	FEC ethernet module.
    103. 

  103.  */
    104. 

  104. #define	MCFFEC_BASE0		(MCF_IPSBAR + 0x1000)
    105. 

  105. #define	MCFFEC_SIZE0		0x800
    106. 

  106. #define	MCFFEC_BASE1		(MCF_IPSBAR + 0x1800)
    107. 

  107. #define	MCFFEC_SIZE1		0x800
    108. 

  108. 

  109. /*
    110. 

  110.  *	QSPI module.
    111. 

  111.  */
    112. 

  112. #define	MCFQSPI_BASE		(MCF_IPSBAR + 0x340)
    113. 

  113. #define	MCFQSPI_SIZE		0x40
    114. 

  114. 

  115. #ifdef CONFIG_M5271
    116. 

  116. #define	MCFQSPI_CS0		91
    117. 

  117. #define	MCFQSPI_CS1		92
    118. 

  118. #define	MCFQSPI_CS2		99
    119. 

  119. #define	MCFQSPI_CS3		103
    120. 

  120. #endif
    121. 

  121. #ifdef CONFIG_M5275
    122. 

  122. #define	MCFQSPI_CS0		59
    123. 

  123. #define	MCFQSPI_CS1		60
    124. 

  124. #define	MCFQSPI_CS2		61
    125. 

  125. #define	MCFQSPI_CS3		62
    126. 

  126. #endif
    127. 

  127. 

  128. /*
    129. 

  129.  *	GPIO module.
    130. 

  130.  */
    131. 

  131. #ifdef CONFIG_M5271
    132. 

  132. #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
    133. 

  133. #define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)
    134. 

  134. #define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
    135. 

  135. #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100003)
    136. 

  136. #define MCFGPIO_PODR_BS		(MCF_IPSBAR + 0x100004)
    137. 

  137. #define MCFGPIO_PODR_CS		(MCF_IPSBAR + 0x100005)
    138. 

  138. #define MCFGPIO_PODR_SDRAM	(MCF_IPSBAR + 0x100006)
    139. 

  139. #define MCFGPIO_PODR_FECI2C	(MCF_IPSBAR + 0x100007)
    140. 

  140. #define MCFGPIO_PODR_UARTH	(MCF_IPSBAR + 0x100008)
    141. 

  141. #define MCFGPIO_PODR_UARTL	(MCF_IPSBAR + 0x100009)
    142. 

  142. #define MCFGPIO_PODR_QSPI	(MCF_IPSBAR + 0x10000A)
    143. 

  143. #define MCFGPIO_PODR_TIMER	(MCF_IPSBAR + 0x10000B)
    144. 

  144. 

  145. #define MCFGPIO_PDDR_ADDR	(MCF_IPSBAR + 0x100010)
    146. 

  146. #define MCFGPIO_PDDR_DATAH	(MCF_IPSBAR + 0x100011)
    147. 

  147. #define MCFGPIO_PDDR_DATAL	(MCF_IPSBAR + 0x100012)
    148. 

  148. #define MCFGPIO_PDDR_BUSCTL	(MCF_IPSBAR + 0x100013)
    149. 

  149. #define MCFGPIO_PDDR_BS		(MCF_IPSBAR + 0x100014)
    150. 

  150. #define MCFGPIO_PDDR_CS		(MCF_IPSBAR + 0x100015)
    151. 

  151. #define MCFGPIO_PDDR_SDRAM	(MCF_IPSBAR + 0x100016)
    152. 

  152. #define MCFGPIO_PDDR_FECI2C	(MCF_IPSBAR + 0x100017)
    153. 

  153. #define MCFGPIO_PDDR_UARTH	(MCF_IPSBAR + 0x100018)
    154. 

  154. #define MCFGPIO_PDDR_UARTL	(MCF_IPSBAR + 0x100019)
    155. 

  155. #define MCFGPIO_PDDR_QSPI	(MCF_IPSBAR + 0x10001A)
    156. 

  156. #define MCFGPIO_PDDR_TIMER	(MCF_IPSBAR + 0x10001B)
    157. 

  157. 

  158. #define MCFGPIO_PPDSDR_ADDR	(MCF_IPSBAR + 0x100020)
    159. 

  159. #define MCFGPIO_PPDSDR_DATAH	(MCF_IPSBAR + 0x100021)
    160. 

  160. #define MCFGPIO_PPDSDR_DATAL	(MCF_IPSBAR + 0x100022)
    161. 

  161. #define MCFGPIO_PPDSDR_BUSCTL	(MCF_IPSBAR + 0x100023)
    162. 

  162. #define MCFGPIO_PPDSDR_BS	(MCF_IPSBAR + 0x100024)
    163. 

  163. #define MCFGPIO_PPDSDR_CS	(MCF_IPSBAR + 0x100025)
    164. 

  164. #define MCFGPIO_PPDSDR_SDRAM	(MCF_IPSBAR + 0x100026)
    165. 

  165. #define MCFGPIO_PPDSDR_FECI2C	(MCF_IPSBAR + 0x100027)
    166. 

  166. #define MCFGPIO_PPDSDR_UARTH	(MCF_IPSBAR + 0x100028)
    167. 

  167. #define MCFGPIO_PPDSDR_UARTL	(MCF_IPSBAR + 0x100029)
    168. 

  168. #define MCFGPIO_PPDSDR_QSPI	(MCF_IPSBAR + 0x10002A)
    169. 

  169. #define MCFGPIO_PPDSDR_TIMER	(MCF_IPSBAR + 0x10002B)
    170. 

  170. 

  171. #define MCFGPIO_PCLRR_ADDR	(MCF_IPSBAR + 0x100030)
    172. 

  172. #define MCFGPIO_PCLRR_DATAH	(MCF_IPSBAR + 0x100031)
    173. 

  173. #define MCFGPIO_PCLRR_DATAL	(MCF_IPSBAR + 0x100032)
    174. 

  174. #define MCFGPIO_PCLRR_BUSCTL	(MCF_IPSBAR + 0x100033)
    175. 

  175. #define MCFGPIO_PCLRR_BS	(MCF_IPSBAR + 0x100034)
    176. 

  176. #define MCFGPIO_PCLRR_CS	(MCF_IPSBAR + 0x100035)
    177. 

  177. #define MCFGPIO_PCLRR_SDRAM	(MCF_IPSBAR + 0x100036)
    178. 

  178. #define MCFGPIO_PCLRR_FECI2C	(MCF_IPSBAR + 0x100037)
    179. 

  179. #define MCFGPIO_PCLRR_UARTH	(MCF_IPSBAR + 0x100038)
    180. 

  180. #define MCFGPIO_PCLRR_UARTL	(MCF_IPSBAR + 0x100039)
    181. 

  181. #define MCFGPIO_PCLRR_QSPI	(MCF_IPSBAR + 0x10003A)
    182. 

  182. #define MCFGPIO_PCLRR_TIMER	(MCF_IPSBAR + 0x10003B)
    183. 

  183. 

  184. /*
    185. 

  185.  * Generic GPIO support
    186. 

  186.  */
    187. 

  187. #define MCFGPIO_PODR		MCFGPIO_PODR_ADDR
    188. 

  188. #define MCFGPIO_PDDR		MCFGPIO_PDDR_ADDR
    189. 

  189. #define MCFGPIO_PPDR		MCFGPIO_PPDSDR_ADDR
    190. 

  190. #define MCFGPIO_SETR		MCFGPIO_PPDSDR_ADDR
    191. 

  191. #define MCFGPIO_CLRR		MCFGPIO_PCLRR_ADDR
    192. 

  192. 

  193. #define MCFGPIO_PIN_MAX		100
    194. 

  194. #define MCFGPIO_IRQ_MAX		8
    195. 

  195. #define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE
    196. 

  196. 

  197. /*
    198. 

  198.  * Port Pin Assignment registers.
    199. 

  199.  */
    200. 

  200. #define MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100040)
    201. 

  201. #define MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100042)
    202. 

  202. #define MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100044)
    203. 

  203. #define MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100045)
    204. 

  204. #define MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100046)
    205. 

  205. #define MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100047)
    206. 

  206. #define MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x100048)
    207. 

  207. #define MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
    208. 

  208. #define MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
    209. 

  209. 

  210. #define UART0_ENABLE_MASK	0x000f
    211. 

  211. #define UART1_ENABLE_MASK	0x0ff0
    212. 

  212. #define UART2_ENABLE_MASK	0x3000
    213. 

  213. #endif /* CONFIG_M5271 */
    214. 

  214. 

  215. #ifdef CONFIG_M5275
    216. 

  216. #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100004)
    217. 

  217. #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100005)
    218. 

  218. #define MCFGPIO_PODR_CS		(MCF_IPSBAR + 0x100008)
    219. 

  219. #define MCFGPIO_PODR_FEC0H	(MCF_IPSBAR + 0x10000A)
    220. 

  220. #define MCFGPIO_PODR_FEC0L	(MCF_IPSBAR + 0x10000B)
    221. 

  221. #define MCFGPIO_PODR_FECI2C	(MCF_IPSBAR + 0x10000C)
    222. 

  222. #define MCFGPIO_PODR_QSPI	(MCF_IPSBAR + 0x10000D)
    223. 

  223. #define MCFGPIO_PODR_SDRAM	(MCF_IPSBAR + 0x10000E)
    224. 

  224. #define MCFGPIO_PODR_TIMERH	(MCF_IPSBAR + 0x10000F)
    225. 

  225. #define MCFGPIO_PODR_TIMERL	(MCF_IPSBAR + 0x100010)
    226. 

  226. #define MCFGPIO_PODR_UARTL	(MCF_IPSBAR + 0x100011)
    227. 

  227. #define MCFGPIO_PODR_FEC1H	(MCF_IPSBAR + 0x100012)
    228. 

  228. #define MCFGPIO_PODR_FEC1L	(MCF_IPSBAR + 0x100013)
    229. 

  229. #define MCFGPIO_PODR_BS		(MCF_IPSBAR + 0x100014)
    230.