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alarmDataOperation.h

alarmDataOperation.h 8.8 KB
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  1. /*
    2. 

  2.  * arch/arm/include/asm/hardware/iop3xx.h
    3. 

  3.  *
    4. 

  4.  * Intel IOP32X and IOP33X register definitions
    5. 

  5.  *
    6. 

  6.  * Author: Rory Bolt <rorybolt@pacbell.net>
    7. 

  7.  * Copyright (C) 2002 Rory Bolt
    8. 

  8.  * Copyright (C) 2004 Intel Corp.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __IOP3XX_H
    16. 

  16. #define __IOP3XX_H
    17. 

  17. 

  18. /*
    19. 

  19.  * IOP3XX GPIO handling
    20. 

  20.  */
    21. 

  21. #define GPIO_IN			0
    22. 

  22. #define GPIO_OUT		1
    23. 

  23. #define GPIO_LOW		0
    24. 

  24. #define GPIO_HIGH		1
    25. 

  25. #define IOP3XX_GPIO_LINE(x)	(x)
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. extern void gpio_line_config(int line, int direction);
    29. 

  29. extern int  gpio_line_get(int line);
    30. 

  30. extern void gpio_line_set(int line, int value);
    31. 

  31. extern int init_atu;
    32. 

  32. extern int iop3xx_get_init_atu(void);
    33. 

  33. #endif
    34. 

  34. 

  35. 

  36. /*
    37. 

  37.  * IOP3XX processor registers
    38. 

  38.  */
    39. 

  39. #define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
    40. 

  40. #define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000
    41. 

  41. #define IOP3XX_PERIPHERAL_SIZE		0x00002000
    42. 

  42. #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
    43. 

  43. 					IOP3XX_PERIPHERAL_SIZE - 1)
    44. 

  44. #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
    45. 

  45. 					IOP3XX_PERIPHERAL_SIZE - 1)
    46. 

  46. #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
    47. 

  47. 					(IOP3XX_PERIPHERAL_PHYS_BASE\
    48. 

  48. 					- IOP3XX_PERIPHERAL_VIRT_BASE))
    49. 

  49. #define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
    50. 

  50. 

  51. /* Address Translation Unit  */
    52. 

  52. #define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
    53. 

  53. #define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
    54. 

  54. #define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
    55. 

  55. #define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
    56. 

  56. #define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
    57. 

  57. #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
    58. 

  58. #define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
    59. 

  59. #define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
    60. 

  60. #define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
    61. 

  61. #define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
    62. 

  62. #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
    63. 

  63. #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
    64. 

  64. #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
    65. 

  65. #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
    66. 

  66. #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
    67. 

  67. #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
    68. 

  68. #define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
    69. 

  69. #define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
    70. 

  70. #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
    71. 

  71. #define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
    72. 

  72. #define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
    73. 

  73. #define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
    74. 

  74. #define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
    75. 

  75. #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
    76. 

  76. #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
    77. 

  77. #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
    78. 

  78. #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
    79. 

  79. #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
    80. 

  80. #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
    81. 

  81. #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
    82. 

  82. #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
    83. 

  83. #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
    84. 

  84. #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
    85. 

  85. #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
    86. 

  86. #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
    87. 

  87. #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
    88. 

  88. #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
    89. 

  89. #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
    90. 

  90. #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
    91. 

  91. #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
    92. 

  92. #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
    93. 

  93. #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
    94. 

  94. #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
    95. 

  95. #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
    96. 

  96. #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
    97. 

  97. #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
    98. 

  98. #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
    99. 

  99. #define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
    100. 

  100. #define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
    101. 

  101. #define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
    102. 

  102. #define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
    103. 

  103. #define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
    104. 

  104. #define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
    105. 

  105. #define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
    106. 

  106. #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
    107. 

  107. #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
    108. 

  108. #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
    109. 

  109. #define IOP3XX_PCSR_IN_Q_BUSY	(1 << 14)
    110. 

  110. #define IOP3XX_ATUCR_OUT_EN	(1 << 1)
    111. 

  111. 

  112. #define IOP3XX_INIT_ATU_DEFAULT 0
    113. 

  113. #define IOP3XX_INIT_ATU_DISABLE -1
    114. 

  114. #define IOP3XX_INIT_ATU_ENABLE	 1
    115. 

  115. 

  116. /* Messaging Unit  */
    117. 

  117. #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
    118. 

  118. #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
    119. 

  119. #define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
    120. 

  120. #define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
    121. 

  121. #define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
    122. 

  122. #define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
    123. 

  123. #define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
    124. 

  124. #define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
    125. 

  125. #define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
    126. 

  126. #define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
    127. 

  127. #define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
    128. 

  128. #define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
    129. 

  129. #define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
    130. 

  130. #define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
    131. 

  131. #define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
    132. 

  132. #define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
    133. 

  133. #define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
    134. 

  134. #define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
    135. 

  135. #define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
    136. 

  136. #define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
    137. 

  137. #define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)
    138. 

  138. 

  139. /* DMA Controller  */
    140. 

  140. #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
    141. 

  141. 					(0x400 + (chan << 6)))
    142. 

  142. #define IOP3XX_DMA_UPPER_PA(chan)  (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
    143. 

  143. 

  144. /* Peripheral bus interface  */
    145. 

  145. #define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
    146. 

  146. #define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
    147. 

  147. #define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
    148. 

  148. #define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
    149. 

  149. #define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
    150. 

  150. #define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
    151. 

  151. #define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
    152. 

  152. #define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
    153. 

  153. #define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
    154. 

  154. #define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
    155. 

  155. #define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
    156. 

  156. #define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
    157. 

  157. #define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
    158. 

  158. #define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
    159. 

  159. #define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
    160. 

  160. #define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
    161. 

  161. #define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
    162. 

  162. 

  163. /* Peripheral performance monitoring unit  */
    164. 

  164. #define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
    165. 

  165. #define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
    166. 

  166. #define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
    167. 

  167. #define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    168. 

  168. /* PERCR0 DOESN'T EXIST - index from 1! */
    169. 

  169. #define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    170. 

  170. 

  171. /* General Purpose I/O  */
    172. 

  172. #define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0000)
    173. 

  173. #define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)
    174. 

  174. #define IOP3XX_GPOD		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
    175. 

  175. 

  176. /* Timers  */
    177. 

  177. #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
    178. 

  178. #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
    179. 

  179. #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
    180. 

  180. #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
    181. 

  181. #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
    182. 

  182. #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
    183. 

  183. #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
    184. 

  184. #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
    185. 

  185. #define IOP_TMR_EN	    0x02
    186. 

  186. #define IOP_TMR_RELOAD	    0x04
    187. 

  187. #define IOP_TMR_PRIVILEGED 0x08
    188. 

  188. #define IOP_TMR_RATIO_1_1  0x00
    189.