aiot/waterDataDiscreteRateMining/externalListeningThread/commandProcessing.c

/*
 * R8A7740 processor support
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include <mach/intc.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

/*
 *		INTCA
 */
enum {
	UNUSED_INTCA = 0,

	/* interrupt sources INTCA */
	DIRC,
	ATAPI,
	IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
	AP_ARM_COMMTX, AP_ARM_COMMRX,
	MFI, MFIS,
	BBIF1, BBIF2,
	USBHSDMAC,
	USBF_OUL_SOF, USBF_IXL_INT,
	SGX540,
	CMT1_0, CMT1_1, CMT1_2, CMT1_3,
	CMT2,
	CMT3,
	KEYSC,
	SCIFA0, SCIFA1, SCIFA2, SCIFA3,
	MSIOF2, MSIOF1,
	SCIFA4, SCIFA5, SCIFB,
	FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
	SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
	AP_ARM_L2CINT,
	IRDA,
	TPU0,
	SCIFA6, SCIFA7,
	GbEther,
	ICBS0,
	DDM,
	SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
	RWDT0,
	DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
	DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
	DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
	DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
	DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
	DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
	SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
	HDMI,
	USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
	RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
	SPU2_0, SPU2_1,
	FSI, FMSI,
	HDMI_SSS, HDMI_KEY,
	IPMMU,
	AP_ARM_CTIIRQ, AP_ARM_PMURQ,
	MFIS2,
	CPORTR2S,
	CMT14, CMT15,
	MMCIF_0, MMCIF_1, MMCIF_2,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,

	/* interrupt groups INTCA */
	DMAC1_1, DMAC1_2,
	DMAC2_1, DMAC2_2,
	DMAC3_1, DMAC3_2,
	AP_ARM1, AP_ARM2,
	SDHI0, SDHI1, SDHI2,
	SHWYSTAT,
	USBF, USBH1, USBH2,
	RSPI, SPU2, FLCTL, IIC1,
};