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- /****************************************************************************/
- /*
- * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
- *
- * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
- */
- /****************************************************************************/
- #ifndef m527xsim_h
- #define m527xsim_h
- /****************************************************************************/
- #define CPU_NAME "COLDFIRE(m527x)"
- #define CPU_INSTR_PER_JIFFY 3
- #define MCF_BUSCLK (MCF_CLK / 2)
- #include <asm/m52xxacr.h>
- /*
- * Define the 5270/5271 SIM register set addresses.
- */
- #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
- #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
- #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
- #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
- #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
- #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
- #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
- #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
- #define MCFINTC_IRLR 0x18 /* */
- #define MCFINTC_IACKL 0x19 /* */
- #define MCFINTC_ICR0 0x40 /* Base ICR register */
- #define MCFINT_VECBASE 64 /* Vector base number */
- #define MCFINT_UART0 13 /* Interrupt number for UART0 */
- #define MCFINT_UART1 14 /* Interrupt number for UART1 */
- #define MCFINT_UART2 15 /* Interrupt number for UART2 */
- #define MCFINT_QSPI 18 /* Interrupt number for QSPI */
- #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
- #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
- #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
- #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
- #define MCFINT2_VECBASE 128 /* Vector base number 2 */
- #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
- #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
- #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
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